Turn-off circuit of power tube

Abstract

The invention discloses a turn-off circuit of a power tube. The input end of a first switch is coupled with the control end of the power tube, and the output end of the first switch is coupled with reference ground; the voltage division circuit is coupled with the control end of the power tube and outputs a first voltage and a second voltage; the first input end of the comparator receives first voltage, and the second input end receives first reference voltage; the input end of the control circuit is coupled with the output end of the comparator, and the output end is coupled with the control end of the first switch; the first input end of the first operational amplifier circuit receives the second voltage, the second input end receives the first reference voltage, the control end is coupled with the output end of the comparator, and the output end is coupled with the control end of the first switch; the second operational amplifier circuit is coupled to the control end of the first switch. The current of the power tube is quickly reduced by the control circuit, so that the time of the overcurrent state of the power tube is greatly reduced, and the current is slowly reduced by the first operational amplifier circuit, so that the sudden change of the current is avoided, and better turn-off protection can be provided.

Description

Technical Field

[0001] The present invention relates to the technical field of power tube shutdown, and in particular to a power tube shutdown circuit. Background Art

[0002] In modern power electronic systems, power transistors, namely insulated gate bipolar transistors (IGBTs) and silicon carbide (SiC) devices, are widely used in motor drive, power conversion and renewable energy generation due to their high efficiency, high frequency and high reliability. To ensure the safe and efficient operation of these power devices, it is essential to accurately control their switching process. Especially during the shutdown process, how to balance fast response and reduce shutdown overshoot, as well as protect the device from damage, has become the focus of current technology development.

[0003] At present, there are some power device driving solutions on the market that use 2-level turn-off technology. This type of technology realizes the turn-off of power devices (such as IGBT or SiC) in two stages: the first stage is fast turn-off, which aims to quickly reduce the gate voltage before the Miller Plateau appears to shorten the turn-off time; the second stage is slow turn-off (or soft turn-off), which slows down the turn-off speed when approaching the Miller Plateau, aiming to reduce turn-off overshoot and protect the device. The 2-level turn-off technology usually sets two fixed turn-off current values. The first stage uses a larger current to quickly lower the gate voltage, and the second stage uses a smaller current for smooth transition.

[0004] However, in the prior art, the actual shutdown process may deviate significantly from the expected one. Especially near the Miller platform, if the shutdown speed is improperly controlled, it is easy to cause the IGBT or SiC device (power tube) to shut down too quickly, increasing the risk of shutdown overshoot. In addition, the rapidly changing shutdown current may cause the gate voltage to produce large transient glitches at the output end. These glitches not only affect the reliability of the IGBT gate, but may also trigger unnecessary malfunctions and reduce system stability. Whether it is excessive shutdown overshoot caused by too fast a shutdown speed or gate damage caused by VGE glitches, it may cause permanent damage to the IGBT or SiC device, shorten its service life, increase maintenance costs, and even cause system failures. Summary of the invention

[0005] The purpose of the present invention is to provide a shutdown circuit for a power tube to solve the problem that when the two-stage circuit shutdown technology is used in the prior art, if the shutdown speed is improperly controlled, the shutdown speed of the power tube is easily caused to be too fast, the risk of shutdown overshoot is increased, and burrs are generated, which affects the reliability of the power tube and may also trigger unnecessary malfunctions and reduce stability.

[0006] To achieve one of the above-mentioned purposes of the invention, an embodiment of the present invention provides a shutdown circuit of a power tube, wherein the control terminal voltage of the power tube is a gate voltage, and the shutdown circuit comprises: a first switch, having a first terminal, a second terminal and a control terminal, wherein the first terminal of the first switch is coupled to the control terminal of the power tube, and the second terminal is coupled to a reference ground; a voltage divider circuit, coupled to the control terminal of the power tube and outputting a first voltage and a second voltage related to the gate voltage, wherein the second voltage is greater than the first voltage; a comparator, generating a comparison signal according to the first voltage and the first reference voltage; a control circuit, wherein the control circuit receives the comparison signal and controls the conduction and shutdown of the first switch according to the comparison signal; a first operational amplifier circuit, having a first input terminal, a second input terminal, a control terminal and an output terminal, wherein the first input terminal is connected to the control terminal of the power tube, and the second input terminal is connected to the reference ground; The input end receives the second voltage, the second input end receives the first reference voltage, the control end receives the comparison signal, and the output end is coupled to the control end of the first switch; and the second operational amplifier circuit is coupled to the control end of the first switch; wherein, when the first voltage is greater than the first reference voltage, the switch circuit operates in the first stage, the first switch is turned on, and the gate voltage decreases at a first rate; when the second voltage is greater than the first reference voltage, the shutdown circuit operates in the second stage, at a first time, the first switch is turned on, the gate voltage slowly decreases, and at a second time, the first switch is turned off, and the gate voltage remains unchanged; when the first stage and the second stage are over, the shutdown circuit operates in the third stage, the first switch is turned on, and the gate voltage decreases at a second rate, wherein the second rate is less than the first rate.

[0007] Compared with the prior art, the present invention has the following beneficial effects: the present invention adopts a three-stage shutdown protection, and utilizes a control circuit to quickly reduce the current of the power tube, so that the time of the overcurrent state of the power tube is greatly reduced. At the same time, when the first voltage is less than the first reference voltage and the second voltage is greater than the first reference voltage, the first operational amplifier circuit is used to slowly reduce the current, so as to avoid shutdown overshoot and burrs caused by current mutation when entering the control of the second operational amplifier circuit, thereby providing better shutdown protection and improving the reliability of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A schematic structural diagram of a power tube shutdown circuit 100 according to an embodiment of the present invention is provided.

[0009] Figure 2 A specific structural schematic diagram of a power tube shutdown circuit 200 in one embodiment of the present invention is given.

[0010] Figure 3 A specific structural schematic diagram of a power tube shutdown circuit 300 in another embodiment of the present invention is provided.

[0011] Figure 4 A specific structural schematic diagram of a shutdown circuit 400 of a power tube in another embodiment of the present invention is provided.

[0012] Figure 5 A schematic diagram of the structure of the duration control circuit 6 in one embodiment of the present invention is given.

[0013] Figure 6 A timing diagram of the control of the circuit by the duration control circuit 6 in one embodiment of the present invention is given. DETAILED DESCRIPTION

[0014] The present invention will be described in detail below in conjunction with the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional changes made by a person skilled in the art based on these embodiments are all within the scope of protection of the present invention.

[0015] It should be noted that the term "comprises" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In addition, the terms "first", "second", "third", etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance.

[0016] The phrases "one embodiment", "an embodiment", "an example", and "example" that appear in various places throughout the specification do not necessarily refer to the same embodiment or example. It should be understood by those skilled in the art that the various specific features, structures or parameters, steps, etc. disclosed in one or more embodiments of the present disclosure can be combined in any suitable manner.

[0017] In the present invention, the power tube G is used to drive a load such as a motor. It can drive the load to run according to the control voltage. When the control voltage is too high, it is easy to cause overvoltage or overcurrent. Therefore, the power tube G needs to be turned off in time to prevent the power tube G from being damaged by voltage shock, and to prevent the load from being damaged by overvoltage or overcurrent.

[0018] In the art, a control voltage is applied to a control terminal of a power tube G to drive the power tube G to operate, thereby driving a load to operate. The voltage at the control terminal of the power tube G is a gate voltage VG.

[0019] Figure 1A schematic diagram of the structure of a shutdown circuit 100 of a power tube according to an embodiment of the present invention is given. The shutdown circuit 100 of the power tube includes a first switch K1, a voltage divider circuit 1, a comparator A1, a control circuit 2, a first operational amplifier circuit 3 and a second operational amplifier circuit 4. The first switch K1 has a first end, a second end and a control end, the first end of the first switch K1 is coupled to the control end of the power tube G, and the second end of the first switch K1 is coupled to the reference ground GND. The voltage divider circuit 1 is coupled to the control end of the power tube G and outputs a first voltage V1 and a second voltage V2 related to the gate voltage VG, wherein the second voltage V2 is greater than the first voltage V1. The comparator A1 generates a comparison signal COMP_OUT according to the first voltage V1 and the first reference voltage VREF1. The control circuit 2 receives the comparison signal COMP_OUT and controls the on and off of the first switch K1 according to the comparison signal COMP_OUT. The first operational amplifier circuit 3 has a first input terminal, a second input terminal, a control terminal and an output terminal. The first input terminal of the first operational amplifier circuit 3 receives the second voltage V2, the second input terminal of the first operational amplifier circuit 3 receives the first reference voltage VREF1, and the control terminal of the first operational amplifier circuit 3 is coupled to the output terminal of the comparator A1 to receive the comparison signal COMP_OUT. The output terminal of the first operational amplifier circuit 3 is coupled to the control terminal of the first switch K1. The second operational amplifier circuit 4 is coupled to the control terminal of the first switch K1.

[0020] refer to Figure 1 As shown, the comparator A1 has a first input terminal, a second input terminal and an output terminal. The first input terminal of the comparator A1 receives a first voltage V1 , and the second input terminal of the comparator A1 receives a first reference voltage VREF1 .

[0021] The control circuit 2 has an input terminal and an output terminal. The input terminal of the control circuit 2 is coupled to the output terminal of the comparator A1 , and the output terminal of the control circuit 2 is coupled to the control terminal of the first switch K1 .

[0022] The comparator A1 compares the first voltage V1 and the first reference voltage VREF1 and generates a comparison signal COMP_OUT. In one embodiment, when the first voltage V1 is greater than the first reference voltage VREF1, the shutdown circuit 100 of the power tube operates in the first stage. The first switch K1 is turned on, and the gate voltage VG decreases at a first rate. In another embodiment, when the second voltage V2 is greater than the first reference voltage VREF1, the shutdown circuit 100 of the power tube operates in the second stage. At the first time, the first switch K1 is turned on, and the gate voltage VG decreases slowly. At the second time, the first switch K1 is turned off, and the gate voltage VG remains unchanged. In one embodiment, after the first stage and the second stage are over, the shutdown circuit 100 of the power tube operates in the third stage, the first switch is turned on, and the gate voltage VG decreases at a second rate, wherein the second rate is less than the first rate.

[0023] When the first voltage V1 decreases to be equal to the first reference voltage VREF1, the first stage ends. The sum of the durations of the first stage and the second stage is the first off-time, and the first off-time is a fixed value. In one embodiment, the first off-time is 2us. When the gate voltage VG decreases to zero, the third stage ends. The duration of the third stage is the second off-time, and the second off-time is a fixed value.

[0024] In one embodiment, the comparison signal COMP_OUT generated by the comparator A1 is at a high level, the shutdown circuit 100 of the power tube works in the first stage, the control circuit 2 works, and the first operational amplifier circuit 3 is turned off. The control circuit 2 controls the first switch K1 to be turned on, and there is a first current I1 between the control end of the power tube G and the input end of the first switch K1. In this way, the first switch K1 discharges the current of the power tube G with the value of the first current I1. The comparison signal COMP_OUT generated by the comparator A1 is at a low level, the shutdown circuit 100 of the power tube works in the second stage, the first operational amplifier circuit 3 works, and the control circuit 2 is turned off. The first operational amplifier circuit 3 controls the first switch K1 to be turned on, and there is a second current I2 between the control end of the power tube G and the input end of the first switch K1. In this way, the first switch K1 discharges the current of the power tube G with the value of the second current I2. Among them, the second current I2 is less than the first current I1. In this way, the first operational amplifier circuit 3 can discharge the current of the power tube G slower than the control circuit 2, so that the control of the current discharge of the power tube G is more stable and reliable.

[0025] As the first operational amplifier circuit 3 discharges the current of the power tube G, the gate voltage VG gradually decreases, the first voltage V1 and the second voltage V2 gradually decrease, and the second current I2 gradually decreases. When the second voltage V2 decreases to the first reference voltage VREF1, the second current I2 decreases to 0. In this way, during the process of the first operational amplifier circuit 3 discharging the current of the power tube G, the speed of the discharge current gradually slows down, ensuring that the gate voltage VG can slowly decrease, ensuring that the current will not suddenly change, and preventing the generation of burrs when the power tube G is turned off.

[0026] When the power tube shutdown circuit 100 works in the third stage, the second operational amplifier circuit 4 controls the first switch K1 to be turned on, and a third current I3 flows between the control end of the power tube G and the input end of the first switch K1, and the third current I3 is smaller than the first current I1. In this way, the second operational amplifier circuit 4 is used to discharge the current of the power tube G until the gate voltage VG drops to 0V, thereby turning off the power tube G.

[0027] continue Figure 1As described above, the shutdown circuit 100 of the power tube also includes a first current limiting resistor Z1, a second current limiting resistor Z2 and an inductor L. The first end of the inductor L is coupled to the control end of the power tube G. The first end of the first current limiting resistor Z1 is coupled to the second end of the inductor L, and the second end of the first current limiting resistor Z1 is coupled to the voltage divider circuit 1. The first end of the second current limiting resistor Z2 is coupled to the second end of the inductor L, and the second end of the second current limiting resistor Z2 is coupled to the input end of the first switch K1. In one embodiment, the second end of the second current limiting resistor Z2 is also coupled to the control circuit 2 and the first operational amplifier circuit 3.

[0028] Figure 2 A schematic diagram of the specific structure of a shutdown circuit 200 of a power tube in one embodiment of the present invention is given. The shutdown circuit 200 of the power tube includes: Figure 1 The first switch K1, the voltage divider circuit 1, the comparator A1, the control circuit 2, the first operational amplifier circuit 3 and the second operational amplifier circuit 4 in the embodiment.

[0029] exist Figure 2 In the embodiment, the voltage divider circuit 1 includes a first resistor R1, a second resistor R2 and a third resistor R3. The first resistor R1 is coupled between the control end of the power tube G and the first voltage divider node H1. The second resistor R2 is coupled between the first voltage divider node H1 and the second voltage divider node H2. The third resistor R3 is coupled between the second voltage divider node H2 and the reference ground GND. The first voltage divider node H1 outputs the second voltage V2, and the second voltage divider node H2 outputs the first voltage V1. V1 = (GATE*R3) / (R1+R2+R3), V2 = GATE*(R2+R3) / (R1+R2+R3), wherein GATE is the gate voltage VG of the first switch K1. In one embodiment, when the first voltage V1 is reduced to the first reference voltage VREF1, the second voltage V2 is greater than the first voltage V1 by ten percent.

[0030] exist Figure 2 In the embodiment, the control circuit 2 includes a first transistor M1, a second transistor M2 and a third transistor M3. The first transistor M1, the second transistor M2 and the third transistor M3 each have a first end, a second end and a control end. The first end of the first transistor M1 is coupled to the control end of the power transistor G, and the second end of the first transistor M1 is coupled to the control end of the first transistor M1. The first end of the second transistor M2 is coupled to the control end of the power transistor G, the control end of the second transistor M2 is coupled to the control end of the first transistor M1, and the second end of the second transistor M2 is coupled to the control end of the first switch K1. The first end of the third transistor M3 is coupled to the second end of the first transistor M1, the second end of the third transistor M3 is coupled to the reference ground GND, and the control end of the third transistor M3 is coupled to the output end of the comparator A1.

[0031] When the shutdown circuit 200 of the power tube works in the first stage, the third transistor M3 is turned on, so that the first transistor M1 and the second transistor M2 are both turned on, and the first transistor M1 and the second transistor M2 form a mirror relationship. The second transistor M2 pulls up the control terminal voltage of the first switch K1 to turn on the first switch K1, and the first current I1 is output at the control terminal of the power tube G, flows through the first switch K1, and is discharged to the reference ground GND.

[0032] When the power tube shut-down circuit 200 operates in the second stage, the third transistor M3 is turned off, thereby controlling the circuit 2 to be turned off.

[0033] exist Figure 2In the embodiment, the first operational amplifier circuit 3 includes a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13 and a fourth resistor R4. The first end of the fourth transistor M4 is coupled to the control end of the power transistor G, and the second end of the fourth transistor M4 is coupled to the control end of the fourth transistor M4. The first end of the fifth transistor M5 is coupled to the control end of the power transistor G, the control end of the fifth transistor M5 is coupled to the control end of the fourth transistor M4, and the second end of the fifth transistor M5 is coupled to the control end of the first switch K1. The first end of the sixth transistor M6 is coupled to the control end of the power transistor G, and the second end of the sixth transistor M6 is coupled to the control end of the sixth transistor M6. The first end of the seventh transistor M7 is coupled to the control end of the power transistor G, and the control end of the seventh transistor M7 is coupled to the control end of the sixth transistor M6. The first end of the eighth transistor M8 is coupled to the second end of the fourth transistor M4, and the control end of the eighth transistor M8 receives the second voltage V2. The first end of the ninth transistor M9 is coupled to the second end of the sixth transistor M6, the control end of the ninth transistor M9 receives the first reference voltage VREF1, and the second end of the ninth transistor M9 is coupled to the second end of the eighth transistor M8. The fourth resistor R4 has a first end and a second end, and the first end of the fourth resistor R4 is coupled to the second ends of the eighth transistor M8 and the ninth transistor M9. The first end of the tenth transistor M10 is coupled to the second end of the fourth resistor R4, the output end of the tenth transistor M10 is coupled to the reference ground GND, and the control end of the tenth transistor M10 receives an enable signal S1 for controlling the tenth transistor M10 to be turned on. The first end of the eleventh transistor M11 is coupled to the second end of the seventh transistor M7, the control end of the eleventh transistor M11 is coupled to the output end of the comparator A1, and the second end of the eleventh transistor M11 is coupled to the reference ground GND. The first end of the twelfth transistor M12 is coupled to the second end of the seventh transistor M7, the control end of the twelfth transistor M12 is coupled to the first end of the twelfth transistor M12, and the second end of the twelfth transistor M12 is coupled to the reference ground GND. A first terminal of the thirteenth transistor M13 is coupled to the second terminal of the fifth transistor M5 , a control terminal of the thirteenth transistor M13 is coupled to the control terminal of the twelfth transistor M12 , and a second terminal of the thirteenth transistor M13 is coupled to the reference ground GND.

[0034] When the power tube shutdown circuit 200 operates in the first stage, the eleventh transistor M11 is turned on, and the twelfth transistor M12 and the thirteenth transistor M13 are turned off. The first operational amplifier circuit 3 is turned off.

[0035] When the shutdown circuit 200 of the power tube works in the second stage, the eleventh transistor M11 is turned off, the twelfth transistor M12 and the thirteenth transistor M13 are turned on, the first operational amplifier circuit 3 works, the fifth transistor M5 pulls up the voltage of the control end of the first switch K1, and the power tube G outputs the second current I2, which flows through the second switch K2 and is discharged to the reference ground GND.

[0036] When the first operational amplifier circuit 3 is working, within the first time, the current output by the fifth transistor M5 is greater than the current at the thirteenth transistor M13, and thereafter the voltage drop output by the fifth transistor M5 gradually decreases until the second voltage V2 is equal to the first reference voltage VREF1, at which time the gate voltage VG slowly decreases and reaches the set value, and the second current I2 approaches 0. Within the second time, since the second voltage V2 is equal to the first reference voltage VREF1, the voltage output by the fifth transistor M5 turns off the first switch K1, and the gate voltage VG remains unchanged.

[0037] exist Figure 2 In the embodiment, the second operational amplifier circuit 4 includes a second switch K2, a first operational amplifier tube OP1 and a fifth resistor R5. The second switch K2 has a first end, a second end and a control end. The first end of the second switch K2 is coupled to the control end of the power tube G, and the control end of the second switch K2 is coupled to the control end of the first switch K1. The first operational amplifier tube OP1 has a first input end, a second input end and an output end. The first input end of the first operational amplifier tube OP1 is coupled to the second end of the second switch K2. The second input end of the first operational amplifier tube OP1 receives the second reference voltage VREF2, and the output end of the first operational amplifier tube OP1 is coupled to the control end of the first switch K1. The fifth resistor R5 has a first end and a second end. The first end of the fifth resistor R5 is coupled to the second end of the second switch K2, and the second end of the fifth resistor R5 is coupled to the reference ground GND.

[0038] When the shutdown circuit 200 of the power tube works in the third stage, the second switch K2 mirrors the current Ir flowing through the first switch K1, and the voltage V3 at the output end of the second switch K2 is received by the first input end of the first operational amplifier tube OP1, V3=Ir*R5. In one embodiment, the mirror ratio K of the first switch K1 and the second switch K2 is any value from 100 to 1000. The first switch K1 discharges the voltage of the power tube G with a current of K*Ir until the voltage of the power tube G drops to 0V.

[0039] Figure 3 A schematic diagram of the specific structure of a power tube shutdown circuit 300 in another embodiment of the present invention is given. Figure 2The shutdown circuit 200 of the power tube shown is different in that the shutdown circuit 300 of the power tube includes a step-down circuit 5, the step-down circuit 5 has a first end and a second end, the first end of the step-down circuit 5 is coupled to the control end of the power tube G, and the second end of the step-down circuit 5 is coupled to the control circuit 2 and the first operational amplifier circuit 3. The step-down circuit 5 is used to step down the gate voltage VG to a third voltage V3 to supply power to the control circuit 2 and the first operational amplifier circuit 3.

[0040] exist Figure 3 In the embodiment, the first end of the fourth transistor M4 is coupled to the second end of the step-down circuit 5, and the second end of the fourth transistor M4 is coupled to the control end of the fourth transistor M4. The first end of the fifth transistor M5 is coupled to the second end of the step-down circuit 5, the control end of the fifth transistor M5 is coupled to the control end of the fourth transistor M4, and the second end of the fifth transistor M5 is coupled to the control end of the first switch K1. The first end of the sixth transistor M6 is coupled to the second end of the step-down circuit 5, and the second end of the sixth transistor M6 is coupled to the control end of the sixth transistor M6. The first end of the seventh transistor M7 is coupled to the second end of the step-down circuit 5, and the control end of the seventh transistor M7 is coupled to the control end of the sixth transistor M6. The first end of the eighth transistor M8 is coupled to the second end of the fourth transistor M4, and the control end of the eighth transistor M8 receives the second voltage V2. The first end of the ninth transistor M9 is coupled to the second end of the sixth transistor M6, the control end of the ninth transistor M9 receives the first reference voltage VREF1, and the second end of the ninth transistor M9 is coupled to the second end of the eighth transistor M8. The fourth resistor R4 has a first end and a second end, and the first end of the fourth resistor R4 is coupled to the second ends of the eighth transistor M8 and the ninth transistor M9. The first end of the tenth transistor M10 is coupled to the second end of the fourth resistor R4, the second end of the tenth transistor M10 is coupled to the reference ground GND, and the control end of the tenth transistor M10 receives an enable signal S1, which is used to control the tenth transistor M10 to be turned on. The first end of the eleventh transistor M11 is coupled to the second end of the seventh transistor M7, the control end of the eleventh transistor M11 is coupled to the second end of the comparator A1, and the second end of the eleventh transistor M11 is coupled to the reference ground GND. The first end of the twelfth transistor M12 is coupled to the second end of the seventh transistor M7, the control end of the twelfth transistor M12 is coupled to the first end of the twelfth transistor M12, and the second end of the twelfth transistor M12 is coupled to the reference ground GND. The first end of the thirteenth transistor M13 is coupled to the second end of the fifth transistor M5, the control end of the thirteenth transistor M13 is coupled to the control end of the twelfth transistor M12, and the second end of the thirteenth transistor M13 is coupled to the reference ground GND.

[0041] Figure 4 A specific structural diagram of a power tube shutdown circuit 400 in another embodiment of the present invention is given. Figure 2The shutdown circuit 200 of the power tube shown in the figure is different in that the shutdown circuit 400 of the power tube includes a step-down circuit 5. The first operational amplifier circuit 3 includes a second operational amplifier tube OP2. The step-down circuit 5 has a first end and a second end, and the first end of the step-down circuit 5 is coupled to the control end of the power tube G. The second end of the step-down circuit 5 is coupled to the control circuit 2 and the first operational amplifier circuit 3.

[0042] The second operational amplifier OP2 has a first input terminal, a second input terminal, a third input terminal and an output terminal. The first input terminal of the second operational amplifier OP2 receives the second voltage V2, the second input terminal of the second operational amplifier OP2 receives the first reference voltage VREF1, the third input terminal of the second operational amplifier OP2 is coupled to the second terminal of the step-down circuit 5, and the output terminal of the second operational amplifier OP2 is coupled to the control terminal of the first switch K1.

[0043] When the shutdown circuit 400 of the power tube works in the second stage, at the first time, the second operational amplifier tube OP2 works, and the second operational amplifier tube OP2 is used to compare the voltage values ​​of the second voltage V2 and the first reference voltage VREF1. When the second voltage V2 is greater than or equal to the first reference voltage VREF1, the first switch K1 is controlled to be turned on, and the second current I2 at the power tube G flows through the first switch K1 and is then discharged to the reference ground GND. The gate voltage VG gradually decreases, and the second voltage V2 gradually decreases and approaches the first reference voltage VREF1. The control of the output end of the second operational amplifier tube OP2 on the first switch K1 gradually weakens, and the second current I2 gradually decreases. When the second voltage V2 decreases to the first reference voltage VREF1, the gate voltage VG slowly decreases and reaches the set value, and the second current I2 approaches 0. At the second time, since the second voltage V2 is equal to the first reference voltage VREF1, the control of the first switch K1 is weakened, so that the first switch K1 is turned off, and the gate voltage VG remains unchanged.

[0044] Figure 5 The schematic diagram of the structure of the duration control circuit 6 in one embodiment of the present invention is given. The duration control circuit 6 receives the enable signal S1 and generates the first and second stage duration control signal S2 and the third stage duration control signal S3 according to the enable signal S1. The enable signal S1, the first and second stage duration control signal S2 and the third stage duration control signal S3 are all used to Figures 1 to 4 Specifically, the first and second stage duration control signal S2 enables the comparator A1 and the first operational amplifier circuit 3, and the third stage duration control signal S3 enables the second operational amplifier circuit 4.

[0045] When the current flowing through the power tube G is greater than the overcurrent threshold, when the enable signal S1 jumps from the first state to the second state, the first and second stage duration control signal S2 jumps from the first state to the second state, and the first and second stage duration control signal S2 remains in the second state for the first off time, and when the first and second stage duration control signal S2 jumps from the second state to the first state, the third stage duration control signal S3 jumps from the first state to the second state and remains in the second state for the second off time. In one embodiment, the first state of the enable signal S1 represents a low level, and the second state represents a high level. The first state of the first and second stage duration control signal S2 represents a low level, and the second state represents a high level. The first state of the third stage duration control signal S3 represents a low level, and the second state represents a high level.

[0046] continue Figure 5 As described above, the duration control circuit 6 includes a first delay TD1, a first inverter INV1, a first AND gate AND1, a second delay TD2, a second inverter INV2, and a second AND gate AND2. The first delay TD1 has an input end and an output end, and the input end of the first delay TD1 receives the enable signal S1. The first inverter INV1 has an input end and an output end, and the input end of the first inverter INV1 is coupled to the output end of the first delay TD1. The first AND gate AND1 has a first input end, a second input end, and an output end, the first input end of the first AND gate AND1 receives the enable signal S1, the second input end of the first AND gate AND1 is coupled to the output end of the first inverter INV1, and the output end of the first AND gate AND1 outputs the first two-stage duration control signal S2. The second delay TD2 has an input end and an output end, and the input end of the second delay TD2 is coupled to the output end of the first delay TD1. The second inverter INV2 has an input terminal and an output terminal, and the input terminal of the second inverter INV2 is coupled to the output terminal of the second delay device TD2. The second AND gate AND2 has a first input terminal, a second input terminal and an output terminal, the first input terminal of the second AND gate AND2 is coupled to the output terminal of the second inverter INV2, the second input terminal of the second AND gate AND2 is coupled to the output terminal of the first delay device TD1, and the output terminal of the second AND gate AND2 outputs the third stage duration control signal S3.

[0047] Figure 6A control timing diagram of the circuit by the duration control circuit 6 in one embodiment of the present invention is given. When the enable signal S1 is switched to a high level, the first input end of the first AND gate AND1 receives a high level, and at the current moment, the second input end of the first AND gate AND1 receives a high level after being inverted by the first inverter INV1. The first AND gate AND1 outputs the first two-stage duration control signal S2 as a high level and maintains the first off-time (T_FAULT). In one embodiment, the first off-time is 2us. After the first off-time is delayed by the first delay TD1, at the beginning of the second off-time, the first delay TD1 outputs a high level, which is inverted to a low level by the first inverter INV1, and the first AND gate AND1 outputs a low level. At this time, the second input end of the second AND gate AND2 receives a high level from the delayed output of the first delay device TD1, and the first input end of the second AND gate AND2 is still in the delay stage because the second delay device TD2 is set, so the output of the second delay device TD2 is still a low level, which is inverted to a high level by the second inverter INV2, and the second AND gate AND2 outputs the third stage duration control signal S3 as a high level and maintains the second off-time (T_SSD). After the second off-time, the second delay device TD2 outputs a high level, which is inverted to a low level by the second inverter INV2, and the second AND gate AND2 outputs a low level.

[0048] In summary, the present invention adopts the first switch K1, the voltage divider circuit 1, the comparator A1, the control circuit 2, the first operational amplifier circuit 3 and the second operational amplifier circuit 4 to form a shutdown protection circuit, and uses the control circuit 2 to control the first switch K1 to quickly discharge the current at the power tube G. When the first voltage V1 reaches the first reference voltage VREF1, the first operational amplifier circuit 3 is switched to control the first switch K1 to discharge the current at the power tube G. The discharge current of the first operational amplifier circuit 3 controlling the first switch K1 is small, and during continuous discharge, the discharge current gradually slows down as the second voltage V2 decreases until the first switch K1 is turned off. Finally, the closed-loop regulation of the second operational amplifier circuit 4 is switched to control the first switch K1 to discharge the current at the power tube G to 0 with a fixed current, so that the power tube G is turned off. The present invention adopts a three-stage shutdown circuit, firstly, the current of the power tube G is quickly reduced so that the time of the overcurrent state of the power tube G is greatly reduced, then the current is slowly reduced to avoid the power tube G generating a sudden change of current near the Miller platform, causing shutdown overshoot and burrs, and finally the power tube G is shut down with a fixed current, so that the shutdown is smoother as a whole, thereby providing better shutdown protection and improving the reliability of the circuit.

[0049] It should be understood that although this specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation mode may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

[0050] The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the present invention. They are not intended to limit the scope of protection of the present invention. Any equivalent implementation methods or changes that do not deviate from the technical spirit of the present invention should be included in the scope of protection of the present invention.

Claims

1. A shutdown circuit for a power tube, wherein the control terminal voltage of the power tube is a gate voltage, and the shutdown circuit comprises: A first switch having a first end, a second end and a control end, wherein the first end of the first switch is coupled to the control end of the power tube, and the second end of the first switch is coupled to a reference ground; A voltage divider circuit is coupled to the control end of the power tube and outputs a first voltage and a second voltage related to the gate voltage, wherein the second voltage is greater than the first voltage; a comparator, generating a comparison signal according to the first voltage and a first reference voltage; A control circuit, the control circuit receives the comparison signal and controls the on and off of the first switch according to the comparison signal; A first operational amplifier circuit has a first input terminal, a second input terminal, a control terminal and an output terminal, wherein the first input terminal receives a second voltage, the second input terminal receives a first reference voltage, the control terminal receives a comparison signal, and the output terminal is coupled to the control terminal of the first switch; as well as A second operational amplifier circuit is coupled to the control terminal of the first switch; Wherein, when the first voltage is greater than the first reference voltage, the shutdown circuit operates in the first stage, the first switch is turned on, and the gate voltage decreases at a first rate; When the second voltage is greater than the first reference voltage, the shutdown circuit operates in the second stage, at the first time, the first switch is turned on, the gate voltage slowly decreases, and at the second time, the first switch is turned off, and the gate voltage remains unchanged; When the first stage and the second stage are finished, the shutdown circuit operates in the third stage, the first switch is turned on, and the gate voltage decreases at a second rate, wherein the second rate is less than the first rate.

2. The shutdown circuit of the power tube according to claim 1, wherein the first stage ends when the first voltage decreases to be equal to the first reference voltage.

3. The shutdown circuit of the power tube according to claim 1, wherein the sum of the duration of the first stage and the second stage is a first shutdown time, and the first shutdown time is a fixed value. 4 . The shutdown circuit of the power tube according to claim 3 , wherein the first shutdown time is 2 us. 5 . The shutdown circuit of the power tube according to claim 1 , wherein the third stage ends when the gate voltage decreases to zero. 6 . The shutdown circuit of the power tube according to claim 1 , wherein the duration of the third stage is the second shutdown time, and the second shutdown time is a fixed value.

7. The shutdown circuit of the power tube according to claim 1, wherein the voltage divider circuit comprises: A first resistor, coupled between the control end of the power tube and the first voltage dividing node; A second resistor is coupled between the first voltage division node and the second voltage division node; as well as A third resistor is coupled between the second voltage division node and a reference ground; The first voltage-dividing node outputs the second voltage, and the second voltage-dividing node outputs the first voltage.

8. The shutdown circuit of the power tube according to claim 1, wherein the control circuit comprises: A first transistor having a first end, a second end and a control end, wherein the first end is coupled to the control end of the power tube, and the second end is coupled to the control end of the first transistor; A second transistor having a first end, a second end and a control end, wherein the first end is coupled to the control end of the power tube, the control end is coupled to the control end of the first transistor, and the second end is coupled to the control end of the first switch; and The third transistor has a first end, a second end and a control end, wherein the first end is coupled to the second end of the first transistor, the second end is coupled to the reference ground, and the control end is coupled to the output end of the comparator.

9. The shutdown circuit of the power tube according to claim 1, wherein the first operational amplifier circuit comprises: A fourth transistor has a first end, a second end and a control end, wherein the first end is coupled to the control end of the power tube, and the second end is coupled to the control end of the fourth transistor; a fifth transistor having a first end, a second end and a control end, wherein the first end is coupled to the control end of the power tube, the control end is coupled to the control end of the fourth transistor, and the second end is coupled to the control end of the first switch; A sixth transistor has a first end, a second end and a control end, wherein the first end is coupled to the control end of the power tube, and the second end is coupled to the control end of the sixth transistor; a seventh transistor having a first end, a second end and a control end, wherein the first end is coupled to the control end of the power transistor, and the control end is coupled to the control end of the sixth transistor; an eighth transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the second terminal of the fourth transistor, and the control terminal receives a second voltage; a ninth transistor having a first end, a second end and a control end, wherein the first end is coupled to the second end of the sixth transistor, the control end receives a first reference voltage, and the second end is coupled to the second end of the eighth transistor; A fourth resistor has a first end and a second end, wherein the first end is coupled to the second ends of the eighth transistor and the ninth transistor; a tenth transistor having a first end, a second end and a control end, wherein the first end is coupled to the second end of the fourth resistor, the second end is coupled to the reference ground, and the control end receives an enable signal for controlling the tenth transistor to be turned on; an eleventh transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the second terminal of the seventh transistor, the control terminal is coupled to the comparator output terminal, and the second terminal is coupled to the reference ground; A twelfth transistor has a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the second terminal of the seventh transistor, the control terminal is coupled to the first terminal, and the second terminal is coupled to the reference ground; and The thirteenth transistor has a first end, a second end and a control end, wherein the first end is coupled to the second end of the fifth transistor, the control end is coupled to the control end of the twelfth transistor, and the second end is coupled to the reference ground.

10. The shutdown circuit of the power tube according to claim 1, wherein the second operational amplifier circuit comprises: A second switch having a first end, a second end and a control end, wherein the first end is coupled to the control end of the power tube, and the control end is coupled to the control end of the first switch; A first operational amplifier tube has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the second terminal of the second switch, the second input terminal receives a second reference voltage, and the output terminal is coupled to the control terminal of the first switch; as well as The fifth resistor has a first end and a second end, wherein the first end is coupled to the output end of the second switch, and the second end is coupled to the reference ground.

11. The shutdown circuit of the power tube according to claim 1, further comprising: The step-down circuit is coupled between the control end of the power tube and the control circuit so as to step down the gate voltage into a third voltage to supply power to the control circuit and the first operational amplifier circuit.

12. The shutdown circuit of the power tube according to claim 1, wherein the shutdown circuit of the power tube further comprises: The duration control circuit receives an enable signal and generates first and second stage duration control signals and a third stage duration control signal according to the enable signal; Among them, when the current flowing through the power tube is greater than the overcurrent threshold, the enable signal jumps from the first state to the second state, the first and second stage time length control signal jumps from the first state to the second state, and the first and second stage time length control signal remains in the second state for the first off time; when the first and second stage time length control signal jumps from the second state to the first state, the third stage time length control signal jumps from the first state to the second state and remains in the second state for the second off time. 13 . The shutdown circuit of the power tube according to claim 12 , wherein the first and second stage duration control signals enable the comparator and the first operational amplifier circuit, and the third stage duration control signal enables the second operational amplifier circuit.

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