Low-power-consumption wake-up logic circuit for low-power-consumption Bluetooth SOC chip
By using low-power wake-up logic circuits composed of AND gate, OR gate, inverter and D flip-flop, the problem of large power consumption in the standby state of low-power Bluetooth SOC chips in the prior art is solved, and a significant reduction in power consumption and simplification of the wake-up process is achieved.
Patent Information
- Application Number
- CN202510119400.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-24
- Publication Date
- 2025-05-16
AI Technical Summary
The existing low-power Bluetooth SOC chips consume a lot of power in standby state, mainly due to dynamic power and static power consumption caused by clock modules and complex wake-up logic circuits.
The low-power wake-up logic circuit composed of AND gate, OR gate, inverter and D flip-flop simplifies the wake-up process of the chip, eliminates the dynamic power consumption of the clock module in standby state, and only static power consumption is retained.
This greatly reduces the power consumption of the chip in standby state, reduces 80%, and simplifies the wake-up process, only the 2bits register needs to be kept to maintain the level.
Smart Images
Figure CN120017033A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of low-power Bluetooth technology, in particular to a low-power wake-up logic circuit for a low-power Bluetooth SOC chip. Background Art
[0002] In a BLE (Bluetooth Low Energy) SOC system, a chip in a standby state needs to be awakened by an external operation, and the power consumption of the chip needs to be maintained as low as possible when the chip is in the standby state.
[0003] Usually, when the chip is in standby mode, it is necessary to retain modules such as clock, digital power supply, logic circuit and register configuration to detect external wake-up. When the external wake-up action is performed, the logic circuit wakes up the chip through a series of timing logic under the control of the clock. This clock will generate dynamic power consumption in the logic circuit during the beating process. At the same time, the wake-up logic circuit itself contains more logic gates and will also generate static power consumption. At this time, the standby power consumption is generally above 500nA. Summary of the invention
[0004] In view of the above problems existing in the prior art, the present invention provides a low-power wake-up logic circuit for a low-power Bluetooth SOC chip. By using an AND gate, an OR gate, an inverter and a D flip-flop, the low-power wake-up process of the chip is realized, which greatly simplifies the wake-up process of the low-power Bluetooth SOC chip and significantly reduces the power consumption of the chip when in standby mode.
[0005] In order to achieve the above-mentioned purpose, a technical solution adopted by the present invention is: to provide a low-power wake-up logic circuit for a low-power Bluetooth SOC chip, including an AND gate; an input OR gate, which has multiple input terminals, each input terminal is connected to an external wake-up signal, and the output terminal is electrically connected to the first input terminal of the AND gate; a D flip-flop, whose reset terminal is connected to a reset control signal, and the clock input terminal is electrically connected to the output terminal of the AND gate; an inverter, whose input terminal is connected to a clock enable signal, and the output terminal is electrically connected to the second input terminal of the AND gate and the data input terminal of the D flip-flop respectively; a first output OR gate, whose first input terminal is connected to the clock enable signal, the second input terminal is electrically connected to the output terminal of the D flip-flop, and the output terminal outputs a clock output enable signal; a second output OR gate, whose first input terminal is connected to a power enable signal, the second input terminal is electrically connected to the output terminal of the D flip-flop, and the output terminal outputs a power output enable signal.
[0006] The beneficial effects of the present invention are as follows: the present invention uses an AND gate, an OR gate, an inverter and a D flip-flop to form a wake-up logic circuit, the circuit structure is simple, no clock module is required when in standby mode, the logic function is simple, and only a few logic gates are needed to realize a low-power wake-up process, which greatly simplifies the wake-up process of the low-power Bluetooth SOC chip, and only a 2-bit register needs to be maintained to maintain the level when in standby mode, thereby eliminating dynamic power consumption and only static power consumption generated by the logic gate, which greatly reduces the power consumption of the chip when in standby mode. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Figure 1 It is a wake-up logic schematic diagram of the prior art;
[0008] Figure 2 It is a schematic diagram of a specific implementation of a low-power wake-up logic circuit for a low-power Bluetooth SOC chip of the present invention;
[0009] Figure 3 It is a schematic diagram of a specific example of the low-power Bluetooth SOC chip of the present invention being in a standby state. DETAILED DESCRIPTION
[0010] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the protection scope of the present invention.
[0011] Figure 1 FIG. 4 is a schematic diagram of wake-up logic in the prior art.
[0012] like Figure 1 As shown, the standby state of a common low-power Bluetooth SOC chip includes: digital power supply, low-frequency clock (32KHz), wake-up logic circuit and multi-bit registers. When the external wake-up action is performed, the wake-up logic circuit generates various timing control signals under the control of the low-frequency clock to turn on other functions of the chip. Since there is a low-frequency clock in the chip at this time, the wake-up logic circuit in standby will continue to generate dynamic power consumption during the waiting time for wake-up. At the same time, in order for the chip to work quickly after wake-up, some register control signals will be saved, and these registers will also generate some standby power consumption. Therefore, the existing chip standby power consumption is relatively large due to the existence of a low-frequency clock, complex wake-up logic circuits, and a large number of registers that need to save status.
[0013] Figure 2 It is a schematic diagram of a specific implementation of the low-power wake-up logic circuit for a low-power Bluetooth SOC chip of the present invention.
[0014] exist Figure 2In a specific implementation manner shown, the low-power wake-up logic circuit for a low-power Bluetooth SOC chip of the present invention includes: an AND gate 201 .
[0015] exist Figure 2 In a specific embodiment shown, the low-power wake-up logic circuit for a low-power Bluetooth SOC chip of the present invention includes: an input OR gate 202, which has multiple input terminals, each input terminal is connected to an external wake-up signal, and the output terminal is electrically connected to the first input terminal of the AND gate.
[0016] In a specific embodiment of the present invention, the number of input terminals of the input OR gate is the same as the number of external paths to be awakened.
[0017] In this specific embodiment, input OR gates with different numbers of input terminals are used according to the number of external wake-up paths, that is, the number of input terminals of the input OR gate is determined by the number of external wake-up paths. Specifically, if two-way wake-up operations are required, an input OR gate with two input terminals is used; if three-way wake-up operations are required, an input OR gate with three input terminals is used, and so on. If N-way wake-up operations are required, an input OR gate with N input terminals is used.
[0018] exist Figure 2 In a specific embodiment shown, the low-power wake-up logic circuit for a low-power Bluetooth SOC chip of the present invention includes: a D flip-flop 203, whose reset terminal is connected to a reset control signal, and whose clock input terminal is electrically connected to the output terminal of an AND gate.
[0019] exist Figure 2 In a specific embodiment shown, the low-power wake-up logic circuit for a low-power Bluetooth SOC chip of the present invention includes: an inverter 204, whose input end is connected to a clock enable signal, and whose output end is electrically connected to the second input end of the AND gate and the data input end of the D flip-flop respectively.
[0020] exist Figure 2 In a specific embodiment shown, the low-power wake-up logic circuit for a low-power Bluetooth SOC chip of the present invention includes: a first output OR gate 205, a first input end of which is connected to a clock enable signal, a second input end is electrically connected to the output end of a D flip-flop, and an output end outputs a clock output enable signal.
[0021] exist Figure 2 In a specific embodiment shown, the low-power wake-up logic circuit for a low-power Bluetooth SOC chip of the present invention includes: a second output OR gate 206, a first input end of which is connected to a power enable signal, a second input end is electrically connected to an output end of a D flip-flop, and an output end outputs a power output enable signal.
[0022] In a specific embodiment of the present invention, the level of the clock enable signal and the level of the power enable signal are maintained by corresponding registers.
[0023] In this specific embodiment, Figure 2 As shown, the clock enable signal is EN_CLK, the power enable signal is EN_POWER, and the clock enable signal EN_CLK and the power enable signal EN_POWER both have corresponding registers, and the registers are used to maintain the levels of the clock enable signal EN_CLK and the power enable signal EN_POWER. The clock enable signal EN_CLK and the power enable signal EN_POWER require a total of 2 bits of registers, which greatly reduces the number of registers that continue to work when the low-power Bluetooth SOC chip is in standby mode.
[0024] Figure 3 It is a schematic diagram of a specific example of the low-power Bluetooth SOC chip of the present invention being in a standby state.
[0025] Combine the following Figure 2 and Figure 3 The working process of the low-power wake-up logic circuit for the low-power Bluetooth SOC chip of the present invention is described as follows:
[0026] In a specific embodiment of the present invention, when the reset control signal, the clock enable signal and the power enable signal are all at high levels, the low power consumption Bluetooth SOC chip operates normally.
[0027] In this specific embodiment, Figure 2 As shown, when the reset control signal RSTN, the clock enable signal EN_CLK and the power enable signal EN_POWER are all high levels, that is, RSTN=EN_CLK=EN_POWER=1, at this time, the data input terminal D of the D flip-flop DFF1=0, so the output terminal Q of the D flip-flop DFF1 is always kept at 0, and then after the logic operation of the first output OR gate OR1_OUT and the second output OR gate OR2_OUT, the clock output enable signal EN_CLK_OUT output by the first output OR gate OR1_OUT and the power output enable signal EN_POWER_OUT output by the second output OR gate OR2_OUT are both high levels, that is, EN_CLK_OUT=EN_POWER_OUT=1, and the low-power Bluetooth SOC chip works normally.
[0028] In a specific embodiment of the present invention, the clock output enable signal controls the switch of the clock in the low-power Bluetooth SOC chip, and the power output enable signal controls the switch of the high-power power supply in the low-power Bluetooth SOC chip.
[0029] In this specific embodiment, the high-power power supply in the low-power Bluetooth SOC chip refers to all power supplies except the low-power digital power supply, because the low-power digital power supply is always in working state regardless of whether the low-power Bluetooth SOC chip is in working state or standby state.
[0030] In a specific example of the present invention, when the clock output enable signal EN_CLK_OUT is at a high level and the power output enable signal EN_POWER_OUT is also at a high level, that is, EN_CLK_OUT = EN_POWER_OUT = 1, at this time, all clocks and high-power power switches of the low-power Bluetooth SOC chip are turned on, that is, at this time, the clock and power supply in the low-power Bluetooth SOC chip are valid.
[0031] In a specific embodiment of the present invention, when the low-power Bluetooth SOC chip is ready to enter the standby state, the D flip-flop is reset by setting the reset control signal connected to its reset terminal to a low level and then to a high level, and the output terminal of the D flip-flop remains at a low level.
[0032] In this specific embodiment, when the low-power Bluetooth SOC chip is ready to enter the standby state, such as Figure 2 As shown, the D flip-flop DFF1 is reset by setting the reset control signal RSTN connected to its reset terminal to 0 or 1, and then the output terminal Q of the D flip-flop DFF1 is kept at 0.
[0033] In a specific embodiment of the present invention, when the low-power Bluetooth SOC chip is in standby state, only the low-power digital power supply, the low-power wake-up logic circuit and the corresponding registers that respectively maintain the levels of the clock enable signal and the power enable signal continue to work in the low-power Bluetooth SOC to detect the external wake-up signal.
[0034] In this specific embodiment, when the low-power Bluetooth SOC chip enters the standby state, Figure 3 As shown, all clocks and high-power power supplies in the low-power Bluetooth SOC chip are turned off, and only the low-power digital power supply, low-power wake-up logic circuit, and the 2-bit register that maintains the clock enable signal EN_CLK and the power enable signal EN_POWER continue to work, thereby detecting the external wake-up signal to determine whether there is an external wake-up operation. The power consumption of the digital power supply is usually within 100nA, and the static power consumption of the wake-up logic circuit and the 2-bit register of the present invention is very small and almost negligible. Therefore, the wake-up logic circuit of the present invention can make the power consumption of the chip in the standby state about 100nA, which is 80% less than 500nA.
[0035] In a specific embodiment of the present invention, when the low-power Bluetooth SOC chip is in a standby state, the clock enable signal and the power enable signal both maintain a low level.
[0036] In this specific embodiment, when the low-power Bluetooth SOC chip is in standby mode, Figure 2 As shown, the clock enable signal EN_CLK and the power enable signal EN_POWER both maintain a low level, that is, EN_CLK=EN_POWER=0.
[0037] In a specific embodiment of the present invention, when the external wake-up signal is at a high level, a wake-up operation is performed on the low-power Bluetooth SOC chip.
[0038] In a specific embodiment of the present invention, when an external wake-up operation is performed, the clock output enable signal and the power output enable signal are both changed from a low level to a high level. At this time, the clock switch and the high-power power switch in the low-power Bluetooth SOC chip are both turned on.
[0039] Specifically, when the external wake-up signal is high, such as Figure 2 As shown, when the external wake-up signal input to any input end of the input OR gate is high level, the input OR gate OR outputs 1, and EN_CLK=0 at this time, so the data input end D of the D flip-flop DFF1 and one end of the AND gate AND1 are both 1. When the external wake-up signal is detected to be high level, the AND gate AND1 outputs 1, and a rising edge is generated at the clock input end CK of the D flip-flop DFF1, so that the output end Q of the D flip-flop DFF1 is Q=D=1, and finally the clock output enable signal EN_CLK_OUT and the power output enable signal EN_POWER_OUT are both changed to high level, that is, EN_CLK_OUT=EN_POWER_OUT=1, thereby turning on the clock and high-power power supply in the low-power Bluetooth SOC chip. When the clock and power supply are established, the low-power Bluetooth SOC chip can operate the chip wake-up program.
[0040] In the low-power wake-up logic circuit for the low-power Bluetooth SOC chip of the present invention, the present invention uses an AND gate, an OR gate, an inverter and a D flip-flop to form a wake-up logic circuit. The circuit structure is simple, no clock module is required when in standby mode, the logic function is simple, and only a few logic gates are needed to realize the low-power wake-up process, which greatly simplifies the wake-up process of the low-power Bluetooth SOC chip. Moreover, only a 2-bit register needs to be maintained to maintain the level when in standby mode, thereby eliminating dynamic power consumption. Only static power consumption is generated by the logic gate, which greatly reduces the power consumption of the chip when in standby mode.
[0041] In the embodiments provided by the present invention, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.
[0042] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0043] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention's specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.
Claims
1. A low-power wake-up logic circuit for a low-power Bluetooth SOC chip, characterized in that: include: AND gate; An input OR gate having a plurality of input terminals, each of which is connected to an external wake-up signal, and an output terminal electrically connected to the first input terminal of the AND gate; A D flip-flop, whose reset terminal is connected to a reset control signal, and whose clock input terminal is electrically connected to the output terminal of the AND gate; An inverter, whose input terminal is connected to the clock enable signal, and whose output terminal is electrically connected to the second input terminal of the AND gate and the data input terminal of the D flip-flop respectively; A first output OR gate, wherein a first input terminal thereof is connected to the clock enable signal, a second input terminal thereof is electrically connected to the output terminal of the D flip-flop, and an output terminal thereof outputs a clock output enable signal; The second output OR gate has a first input terminal connected to a power enable signal, a second input terminal electrically connected to the output terminal of the D flip-flop, and an output terminal outputting a power output enable signal.
2. The wake-up logic circuit for a low-power Bluetooth chip according to claim 1, characterized in that: The number of input terminals of the input OR gate is the same as the number of external paths to be awakened.
3. The low-power wake-up logic circuit for a low-power Bluetooth SOC chip according to claim 1, characterized in that: The level of the clock enable signal and the level of the power enable signal are maintained by corresponding registers.
4. The wake-up logic circuit for a low-power Bluetooth chip according to claim 1, characterized in that: When the external wake-up signal is at a high level, a wake-up operation is performed on the low-power Bluetooth SOC chip.
5. The low-power wake-up logic circuit for a low-power Bluetooth SOC chip according to claim 1, characterized in that: The clock output enable signal controls the switch of the clock in the low-power Bluetooth SOC chip, and the power output enable signal controls the switch of the high-power power supply in the low-power Bluetooth SOC chip.
6. The wake-up logic circuit for a low-power Bluetooth SOC chip according to claim 1, characterized in that: When the reset control signal, the clock enable signal and the power enable signal are all at high levels, the low-power Bluetooth SOC chip operates normally.
7. The low-power wake-up logic circuit for a low-power Bluetooth SOC chip according to claim 1, characterized in that: When the low-power Bluetooth SOC chip is ready to enter the standby state, the D flip-flop is reset by setting the reset control signal connected to its reset terminal to a low level and then to a high level, and the output terminal of the D flip-flop remains at a low level.
8. The low-power wake-up logic circuit for a low-power Bluetooth SOC chip according to claim 3, characterized in that: When the low-power Bluetooth SOC chip is in a standby state, only the low-power digital power supply, the low-power wake-up logic circuit and the corresponding registers that respectively maintain the levels of the clock enable signal and the power enable signal continue to work in the low-power Bluetooth SOC to detect the external wake-up signal.
9. The low-power wake-up logic circuit for a low-power Bluetooth SOC chip according to claim 1, characterized in that: When the low-power Bluetooth SOC chip is in a standby state, the clock enable signal and the power enable signal both maintain a low level.
10. The low-power wake-up logic circuit for a low-power Bluetooth SOC chip according to claim 5, characterized in that: When an external wake-up operation is performed, the clock output enable signal and the power output enable signal are both changed from a low level to a high level. At this time, the clock switch and the high-power power switch in the low-power Bluetooth SOC chip are both turned on.