Charge pump circuit, phase-locked loop circuit and integrated circuit chip

Abstract

The embodiment of the invention provides a charge pump circuit, a phase-locked loop circuit and an integrated circuit chip. The charge pump circuit comprises a first adjusting module, a second adjusting module, a charging module and a discharging module, the charging module comprises a first PMOS tube and a charging control unit. The charging control unit is used for receiving a charging signal and controlling the on-off of the first PMOS tube according to the charging signal; the discharge module comprises a first NMOS tube and a discharge control unit; the discharge control unit is used for receiving a discharge signal and controlling the on-off of the first NMOS tube according to the discharge signal; the first adjusting module is used for adjusting the charging current of the charging module according to the output voltage so as to maintain the charging current constant; the second adjusting module is used for adjusting the discharge current of the discharge module according to the output voltage so as to maintain the discharge current constant. The output current of the charging and discharging module is adjusted through the first adjusting module and the second adjusting module, so that the charging and discharging current is kept constant, and the problem of mismatching of the charging and discharging current is solved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit design, and in particular to a charge pump circuit, a phase-locked loop circuit and an integrated circuit chip. Background Art

[0002] The charge pump circuit is a very important circuit structure in the phase-locked loop (PPL). It converts the phase difference information output by the phase frequency detector (PFD) into a control voltage to adjust the frequency of the voltage-controlled oscillator (VCO). The charge pump circuit adjusts the control voltage of the VCO by providing charging current and discharging current, thereby achieving precise control of the output frequency.

[0003] When the output voltage of a traditional charge pump circuit is close to the power supply voltage or ground, there will be a serious mismatch between the charging current and the discharging current. For example, when the output voltage is close to the power supply voltage, the discharge current is the largest and the charging current is almost zero, which seriously limits the phase-locked loop's demand for a wide output voltage range of the charge pump circuit.

[0004] In addition, when the process deviation during integrated circuit manufacturing is taken into account, the mismatch between the charging current and the discharging current of the traditional charge pump circuit will be further amplified. Summary of the invention

[0005] The embodiments of the present application provide a charge pump circuit, a phase-locked loop circuit and an integrated circuit chip to solve the problem of charge and discharge current mismatch.

[0006] In a first aspect, an embodiment of the present application provides a charge pump circuit, including: a first regulating module, a second regulating module, a charging module and a discharging module;

[0007] The charging module includes a first PMOS tube and a charging control unit, wherein the source of the first PMOS tube is connected to the first power source, the gate of the first PMOS tube is connected to the output end of the charging control unit, and the drain of the first PMOS tube is used to output the output voltage; the charging control unit is used to receive a charging signal and control the on and off of the first PMOS tube according to the charging signal;

[0008] The discharge module includes a first NMOS tube and a discharge control unit, wherein the drain of the first NMOS tube is connected to the drain of the first PMOS tube, the source of the first NMOS tube is grounded, and the gate of the first NMOS tube is connected to the output end of the discharge control unit; the discharge control unit is used to receive a discharge signal and control the on and off of the first NMOS tube according to the discharge signal;

[0009] The first end of the first regulating module is connected to the drain of the first PMOS tube, and the second end of the first regulating module is connected to the charging module; the first regulating module is used to adjust the charging current of the charging module according to the output voltage to maintain the charging current constant;

[0010] The first end of the second regulating module is connected to the drain of the first PMOS tube, and the second end of the second regulating module is connected to the discharge module; the second regulating module is used to adjust the discharge current of the discharge module according to the output voltage to maintain the discharge current constant.

[0011] In one of the embodiments, the first regulating module includes: a charging current regulating unit, the charging current regulating unit includes a first feedback subunit, a first current source, a second current source and a first current mirror;

[0012] A first end of the first feedback subunit is connected to the drain of the first PMOS tube, a second end of the first feedback subunit is grounded through a first current source, and an output end of the first feedback subunit is connected to a first end of the first current mirror;

[0013] The second end of the first current mirror is connected to the charging control unit, the third end of the first current mirror is connected to the first power supply, and the fourth end of the first current mirror is grounded through the second current source;

[0014] The first feedback subunit is used to output a first signal when the output voltage is greater than or equal to a first preset value, and the first signal is used to control the voltage difference between the source and the drain of the first PMOS tube to maintain a constant charging current;

[0015] The currents output by the first current source and the second current source are equal.

[0016] In one embodiment, the second regulating module includes: a discharge current regulating unit; the discharge current regulating unit includes a second feedback subunit, a third current source, a fourth current source and a second current mirror;

[0017] A first end of the second feedback subunit is connected to the drain of the first PMOS tube, a second end of the second feedback subunit is connected to the third current source, and an output end of the second feedback subunit is connected to the second end of the second current mirror;

[0018] The second end of the second current mirror is connected to the discharge control unit, the third end of the second current mirror is connected to the first power supply through the fourth current source, and the fourth section of the first current mirror is grounded;

[0019] The second feedback subunit is used to output a second signal when the output voltage is less than or equal to a second preset value, and the second signal is used to control the voltage difference between the source and the drain of the first NMOS tube to maintain a constant discharge current;

[0020] The currents output by the third current source and the fourth current source are equal.

[0021] In one of the embodiments, the first regulating module includes: a first switch, a first voltage dividing unit, and a second voltage dividing unit;

[0022] A first end of the first voltage dividing unit is connected to the first power supply, and a second end of the first voltage dividing unit is connected to the first end of the first switch and the substrate of the first PMOS tube;

[0023] The second end of the first switch is connected to the first end of the second voltage dividing unit, the control end of the first switch is connected to the output voltage; the second end of the second voltage dividing unit is grounded;

[0024] The first switch is used to be in a conducting state when the output voltage is greater than or equal to a first preset value, and the first voltage dividing unit and the second voltage dividing unit are used to control the threshold voltage of the first PMOS tube to maintain a constant charging current.

[0025] In one embodiment, the second regulating module includes: a second switch, a third voltage dividing unit and a fourth voltage dividing unit;

[0026] A first end of the third voltage dividing unit is connected to the first power supply, and a second end of the third voltage dividing unit is connected to the first end of the second switch;

[0027] The second end of the second switch is connected to the first end of the fourth voltage dividing unit and the substrate of the first NMOS tube, and the control end of the second switch is connected to the drain of the first PMOS tube; the second end of the fourth voltage dividing unit is grounded;

[0028] The second switch is used to be in a conducting state when the output voltage is less than or equal to a second preset value. The third voltage dividing unit and the fourth voltage dividing unit are used to control the threshold voltage of the first NMOS tube to maintain a constant charging current.

[0029] In one of the embodiments, the charging control unit includes a first selection subunit, a second selection subunit, a fifth current source, a third current mirror, and a fourth current mirror;

[0030] A first end of the third current mirror is connected to the first power supply, a second end of the third current mirror is connected to a third end of the current mirror and a first end of the first selection subunit; a fourth end of the third current mirror is connected to a third end of the fourth current mirror and a second end of the first regulation module;

[0031] A first end of the fourth current mirror is connected to the first power supply, a second end of the fourth current mirror is connected to a fourth end of the fourth current mirror and a first end of the second selection subunit, and a fourth end of the fourth current mirror is connected to the gate of the first PMOS tube;

[0032] The second end of the first selection subunit is connected to the second end of the second selection subunit and the fourth current mirror;

[0033] The control end of the first selection subunit is controlled by the complementary signal of the charging signal, and the control unit of the second selection subunit is controlled by the charging signal; the second selection subunit is used to turn on when receiving the charging signal, and the first selection subunit is used to turn on when receiving the complementary signal of the charging signal.

[0034] In one of the embodiments, the discharge control unit includes a third selection subunit, a fourth selection subunit, a sixth current source, a fifth current mirror and a sixth current mirror;

[0035] A first end of the sixth current source is connected to the first power source, and a second end of the sixth power source is connected to a first end of the third selection subunit and a first end of the fourth selection subunit;

[0036] The second end of the third selection subunit is connected to the first end of the fifth current mirror, and the control end of the third selection subunit is controlled by a complementary signal of the discharge signal;

[0037] The second end of the fifth current mirror is grounded, the third end of the fifth current mirror is connected to the fourth end of the sixth current mirror and the second end of the second regulating module, and the fourth end of the fifth current mirror is connected to the first end of the fifth current mirror;

[0038] The second end of the fourth selection subunit is connected to the first end of the sixth current mirror, and the control end of the fourth selection subunit is controlled by the discharge signal;

[0039] The second end of the sixth current mirror is grounded, and the third end of the sixth current mirror is connected to the gate of the first NMOS tube and the first end of the sixth current mirror.

[0040] In one embodiment, when the first switch is turned on, the voltage across the first voltage dividing unit is less than the turn-on voltage of the PN junction of the first PMOS tube;

[0041] When the second switch is turned on, the voltage across the fourth voltage dividing unit is less than the turn-on voltage of the PN junction of the first NMOS tube.

[0042] In a second aspect, an embodiment of the present application provides a phase-locked loop circuit, comprising any of the above-mentioned charge pump circuits.

[0043] In a third aspect, an embodiment of the present application provides an integrated circuit chip, comprising any of the above-mentioned charge pump circuits.

[0044] The embodiment of the present application provides a charge pump circuit, a phase-locked loop circuit and an integrated circuit chip, wherein the charge pump circuit comprises: a first regulating module, a second regulating module, a charging module and a discharging module; the charging module comprises a first PMOS tube and a charging control unit, the source of the first PMOS tube is connected to a first power supply, the gate of the first PMOS tube is connected to an output end of the charging control unit, and the drain of the first PMOS tube is used to output an output voltage; the charging control unit is used to receive a charging signal and control the on and off of the first PMOS tube according to the charging signal; the discharging module comprises a first NMOS tube and a discharging control unit, the drain of the first NMOS tube is connected to the drain of the first PMOS tube, and the first The source of the NMOS tube is grounded, and the gate of the first NMOS tube is connected to the output end of the discharge control unit; the discharge control unit is used to receive a discharge signal and control the on and off of the first NMOS tube according to the discharge signal; the first end of the first adjustment module is connected to the drain of the first PMOS tube, and the second end of the first adjustment module is connected to the charging module; the first adjustment module is used to adjust the charging current of the charging module according to the output voltage to maintain the charging current constant; the first end of the second adjustment module is connected to the drain of the first PMOS tube, and the second end of the second adjustment module is connected to the discharge module; the second adjustment module is used to adjust the discharge current of the discharge module according to the output voltage to maintain the discharge current constant. This application solves the problem of charge and discharge current mismatch caused by output voltage and process deviation by adjusting the output current of the charging module when the output voltage is close to the first power supply voltage by the first adjustment module; and adjusting the output current of the discharge module when the output voltage is close to zero by the second adjustment module to maintain the charge and discharge current constant. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0046] Figure 1 A schematic diagram of the structure of a charge pump circuit provided in one embodiment of the present application;

[0047] Figure 2 A schematic diagram of the structure of a charge pump circuit provided in another embodiment of the present application;

[0048] Figure 3 A schematic diagram of the structure of a charge pump circuit provided in one embodiment of the present application.

[0049] Reference numerals:

[0050] 110, charging module; 120, first regulating module; 130, discharging module; 140, second regulating module; 111, charging control unit; In1, first current source; In2, second current source; In3, fifth current source; Ip1, third current source; Ip2, fourth current source; Ip3, sixth current source; 131, discharging control unit; U1, first error amplifier; U2, second error amplifier; P1, first PMOS tube; N1, first NMOS tube.

[0051] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0052] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0053] The charge pump circuit is a very important circuit structure in the phase-locked loop (PPL). It converts the phase difference information output by the phase frequency detector (PFD) into a control voltage to adjust the frequency of the voltage-controlled oscillator (VCO). The charge pump circuit adjusts the control voltage of the VCO by providing charging current and discharging current, thereby achieving precise control of the output frequency.

[0054] When the output voltage of a traditional charge pump circuit is close to the power supply voltage or ground, the charging current and the discharging current will have a serious mismatch. When the voltage-controlled oscillator needs to output a very high frequency, the charge pump circuit needs to output a high voltage, but the excessively high output voltage will press the charged PMOS tube into the linear region, and the drain current is proportional to the voltage difference VDS between the source and the drain, thus causing the current of the PMOS tube drain to decrease; when the voltage-controlled oscillator needs to output a very low frequency, the discharged NMOS will also face the same problem, and the matching of the discharge current and the charging current will be relatively poor. For example, when the output voltage is close to the power supply voltage, the discharge current is the largest and the charging current is almost zero, which seriously limits the phase-locked loop's demand for a wide output voltage range of the charge pump circuit.

[0055] In traditional charge pump circuits, MOS tubes are usually used as switch tubes to control the charge and discharge of the charge pump. They can be placed at the drain, source or gate of the current tube. When placed at the drain or source, the output voltage swing will be severely reduced at low voltage, especially at the drain, which is directly connected to the output, so the charge injection and charge sharing effects will be very obvious. If placed at the gate, the on and off time of the charge pump charge and discharge will increase due to the gate capacitance of the current tube, and the output impedance of the charge pump is small, which is easily affected by the output voltage, resulting in current mismatch. In addition, when considering the problem of process deviation in the integrated circuit manufacturing process, the mismatch of the charging current and discharge current of the traditional charge pump circuit will be amplified again.

[0056] In combination with the above scenarios, it can be seen that in the prior art, the charge pump circuit has a problem of charge and discharge current mismatch when the output voltage is too high or too low.

[0057] The charge pump circuit provided in the present application includes a first regulating module, a second regulating module, a charging module and a discharging module; the charging module includes a first PMOS tube P1 and a charging control unit, the source of the first PMOS tube is connected to a first power source, the gate of the first PMOS tube is connected to an output end of the charging control unit, and the drain of the first PMOS tube is used to output an output voltage; the charging control unit is used to receive a charging signal and control the on and off of the first PMOS tube according to the charging signal; the discharging module includes a first NMOS tube and a discharging control unit, the drain of the first NMOS tube is connected to the drain of the first PMOS tube, the source of the first NMOS tube is grounded, The gate of the first NMOS tube is connected to the output end of the discharge control unit; the discharge control unit is used to receive the discharge signal and control the on and off of the first NMOS tube according to the discharge signal; the first end of the first regulating module is connected to the drain of the first PMOS tube, and the second end of the first regulating module is connected to the charging module; the first regulating module is used to adjust the charging current of the charging module according to the output voltage to maintain the charging current constant; the first end of the second regulating module is connected to the drain of the first PMOS tube, and the second end of the second regulating module is connected to the discharge module; the second regulating module is used to adjust the discharge current of the discharge module according to the output voltage to maintain the discharge current constant. This application solves the problem of charge and discharge current mismatch caused by output voltage and process deviation by adjusting the output current of the charging module when the output voltage is close to the first power supply voltage through the first regulating module; and adjusting the output current of the discharge module when the output voltage is close to zero through the second regulating module to maintain the charge and discharge current constant.

[0058] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0059] like Figure 1 As shown, Figure 1 A structural schematic diagram of a charge pump circuit is provided for an embodiment of the present application. The charge pump circuit includes: a first regulating module 120, a second regulating module 140, a charging module 110 and a discharging module 130; the charging module 110 includes a first PMOS tube P1 and a charging control unit 111, the source of the first PMOS tube P1 is connected to the first power supply, the gate of the first PMOS tube P1 is connected to the output end of the charging control unit 111, and the drain of the first PMOS tube P1 is used to output an output voltage; the charging control unit 111 is used to receive a charging signal and control the on and off of the first PMOS tube P1 according to the charging signal; the discharging module 130 includes a first NMOS tube N1 and a discharging control unit 131, the drain of the first NMOS tube N1 is connected to the drain of the first PMOS tube P1, the source of the first NMOS tube N1 is grounded, and the discharge ... gate of the first PMOS tube N1 A gate of an NMOS tube N1 is connected to an output end of a discharge control unit 131; the discharge control unit 131 is used to receive a discharge signal and control the on and off of the first NMOS tube N1 according to the discharge signal; a first end of the first regulating module 120 is connected to a drain of the first PMOS tube P1, and a second end of the first regulating module 120 is connected to the charging module 110; the first regulating module 120 is used to regulate the charging current of the charging module 110 according to the output voltage to maintain the charging current constant; a first end of the second regulating module 140 is connected to the drain of the first PMOS tube P1, and a second end of the second regulating module 140 is connected to the discharge module 130; the second regulating module 140 is used to regulate the discharge current of the discharge module 130 according to the output voltage to maintain the discharge current constant.

[0060] Specifically, the first PMOS tube P1 is a charge-controlled transistor, which realizes charging of the output node of the charge pump circuit, pulls up the output voltage to the first power supply voltage, and the charging control unit 111 is used to control whether the first PMOS tube P1 is charged; the first NMOS tube N1 is a discharge-controlled transistor, which realizes the discharge of the output node of the charge pump circuit, pulls down the output voltage to zero, and the discharge control unit 131 is used to control whether the first NMOS tube N1 is discharged. This application improves the current mismatch characteristics of the traditional charge pump circuit by introducing the first adjustment module 120 and the second adjustment module 140, maintains the constant charge and discharge current, and increases the output voltage range of the charge pump, which has great application in phase-locked loop circuits with low noise design requirements and voltage-controlled oscillators with a wide output range.

[0061] In one embodiment, if Figure 1 As shown, the charging control unit 111 includes a first selection subunit, a second selection subunit, a fifth current source In3, a third current mirror and a fourth current mirror; the first end of the third current mirror is connected to the first power supply, the second end of the third current mirror is connected to the third end of the current mirror and the first end of the first selection subunit; the fourth end of the third current mirror is connected to the third end of the fourth current mirror and the second end of the first adjustment module 120; the first end of the fourth current mirror is connected to the first power supply, the second end of the fourth current mirror is connected to the fourth end of the fourth current mirror and the first end of the second selection subunit, and the fourth end of the fourth current mirror is connected to the gate of the first PMOS tube P1; the second end of the first selection subunit is connected to the second end of the second selection subunit and the fourth current mirror; the control end of the first selection subunit is controlled by the complementary signal of the charging signal, and the control unit of the second selection subunit is controlled by the charging signal; the second selection subunit is used to turn on when receiving the charging signal, and the first selection subunit is used to turn on when receiving the complementary signal of the charging signal.

[0062] Specifically, the first selection subunit includes an N-type MOS transistor N11 and a P-type MOS transistor P11, wherein the source of N11 is connected to the drain of P11, the drain of N11 is connected to the source of P11, the gate of N11 is connected to the complementary signal UPN of the charging signal, and the gate of P11 is connected to the charging signal UP, and the charging signal UP is a pulse signal generated by the frequency and phase detector. The second selection subunit includes N12 and P12, the drain of N12 is connected to the source of P12, the source of N12 is connected to the drain of P12 and is grounded through the fifth current source In3, the gate of N12 is controlled by the charging signal UP, and the gate of P12 is controlled by the complementary signal UPN of the charging signal. The third current mirror includes P5 and P6, and the fourth current mirror includes P7 and P8, wherein the sources of P5 and P6 are connected to the first power supply, the gate of P5 is connected to the drain of P5 and to the drain of N11, and the drain of P6 is connected to the drain of P5; the fourth current mirror includes P7 and P8, wherein the sources of P7 and P8 are connected to the first power supply, the drain of P7 is connected to the drain of P8 and to the drain of N11, the gate of P7 is connected to the gate of P6, the gate of P8 is connected to the gate of the first PMOS tube P1, and the gate of P8 is connected to the drain of P8. When the first selection subunit receives the complementary signal of the charging signal, that is, when UPN is high and UP is low, N11 and P11 are turned on, N12 and P12 are not turned on, and the first power supply is grounded through the third current mirror, the first selection subunit, and the fifth current source In3. At this time, the gate of the first PMOS tube P1 is pulled up to the first power supply voltage, and charging stops. When the second selection subunit receives the charging signal, that is, UP is high and UPN is low, the first selection subunit is not turned on, N12 and P12 are turned on, P8 and the gate of the first PMOS tube P1 are pulled low, and the first PMOS tube P1 is turned on, and charging starts.

[0063] In one embodiment, if Figure 1 As shown, the discharge control unit 131 includes a third selection subunit, a fourth selection subunit, a sixth current source Ip3, a fifth current mirror and a sixth current mirror; the first end of the sixth current source Ip3 is connected to the first power supply, and the second end of the sixth power supply is connected to the first end of the third selection subunit and the first end of the fourth selection subunit; the second end of the third selection subunit is connected to the first end of the fifth current mirror, and the control end of the third selection subunit is controlled by the complementary signal of the discharge signal; the second end of the fifth current mirror is grounded, the third end of the fifth current mirror is connected to the fourth end of the sixth current mirror and the second end of the second regulating module 140, and the fourth end of the fifth current mirror is connected to the first end of the fifth current mirror; the second end of the fourth selection subunit is connected to the first end of the sixth current mirror, and the control end of the fourth selection subunit is controlled by the discharge signal; the second end of the sixth current mirror is grounded, and the third end of the sixth current mirror is connected to the gate of the first NMOS tube N1 and the first end of the sixth current mirror.

[0064] Specifically, the third selection subunit includes a P-type MOS tube P10 and an N-type MOS tube N10, wherein the source of P10 is connected to the drain of N10, the drain of P10 is connected to the source of N10, the gate of P10 is controlled by a discharge signal DN, and the gate of N10 is controlled by a complementary signal DNN of the discharge signal; the fifth current mirror includes N-type MOS tubes N5 and N6, the sources of N5 and N6 are grounded, the drain of N5 is connected to the drain of N6, and the gate of N5 is connected to the drain of N5 and to the source of N10. The fourth selection subunit includes a P-type MOS tube P9 and an N-type MOS tube N9, wherein the source of P9 is connected to the drain of N9, the drain of P9 is connected to the source of N9, the gate of P9 is controlled by the complementary signal DNN of the discharge signal, and the gate of N9 is controlled by the discharge signal DN; the sixth current mirror includes N-type MOS tubes N7 and N8, the sources of N7 and N8 are grounded, the drain of N7 is connected to the drain of N8, the gate of N8 is connected to the drain of N5 and to the source of N9, the gate of N7 is connected to the gate of N6, and the gate of N8 is also connected to the gate of the first NMOS tube N1. When the fourth selection subunit receives a discharge signal, that is, DN is high and DNN is low, at this time, N9 and P9 are turned on, P10 and N10 are turned off, the first NMOS tube N1 is turned on, and the discharge starts; if the third selection subunit receives a complementary signal of the discharge signal, that is, DNN is high and DN is low, the fourth selection subunit is turned off, and the gate of the first NMOS tube N1 is pulled up to the first power supply voltage, so the discharge stops, and the voltage of the first power supply passes through the sixth current source Ip3, the third selection subunit and the fifth current mirror.

[0065] In one embodiment, if Figure 2 As shown, Figure 2 A schematic diagram of the structure of a charge pump circuit provided in another embodiment of the present application. The first regulating module 120 includes: a charging current regulating unit, the charging current regulating unit includes a first feedback subunit, a first current source In1, a second current source In2 and a first current mirror; the first end of the first feedback subunit is connected to the drain of the first PMOS tube P1, the second end of the first feedback subunit is grounded through the first current source In1, and the output end of the first feedback subunit is connected to the first end of the first current mirror; the second end of the first current mirror is connected to the charging control unit 111, the third end of the first current mirror is connected to the first power supply, and the fourth end of the first current mirror is grounded through the second current source In2; the first feedback subunit is used to output a first signal when the output voltage is greater than or equal to the first preset value, and the first signal is used to control the voltage difference between the source and the drain of the first PMOS tube P1 to maintain a constant charging current; the currents output by the first current source In1 and the second current source In2 are equal.

[0066] Optionally, the first current source In1 , the second current source In2 , the third current source Ip1 , the fourth current source Ip2 , the fifth current source In3 and the sixth current source Ip3 are current sources with equal current magnitudes.

[0067] In one embodiment, the first current mirror includes PMOS transistors P3 and P4, the source of P3 and the source of P4 are connected to the first power supply, the drain of P3 and the drain of P4 are connected to the second current source In2.

[0068] In one embodiment, see Figure 2 The first feedback subunit includes a first error amplifier U1 and a PMOS tube P2. The negative input terminal of the first error amplifier U1 is connected to the drain of the first PMOS tube P1, the positive input terminal of the first error amplifier U1 is connected to the first current source In1, the output terminal of the first error amplifier U1 is connected to the gate of P2 and the gate of P3, the source of P2 is connected to the first power supply, and the drain of P2 is connected to the first current source In1.

[0069] Specifically, when the output voltage is at half of the first power supply voltage, the first regulating module 120 keeps the charging current relatively stable; when the output voltage is greater than or equal to the first preset value, that is, when the first preset value is close to the first power supply voltage, the voltage at the negative output terminal of the first error amplifier U1 rises, the first error amplifier U1 outputs a low level, and the gate voltages of P2 and P3 decrease. Since the second current source In2 is a constant current source, P3 and P4 are current mirrors, the current flowing through P3 increases, and the output current of P4 decreases. The current formula of the saturation region of the PMOS tube is as follows. According to the current formula of the saturation region of the PMOS tube, the voltage difference of VSG of P4 decreases, and the corresponding gate voltage of P4 increases, thereby the gate voltages of P6 and P7 tubes increase. Since the fifth current source In3 is a constant current source, when the charging signal is received, the second selection subunit is turned on, the gate voltages of P8 and the first PMOS tube P1 decrease, and the source-gate voltage difference VSG of the first PMOS tube P1 increases, thereby the output current of the first PMOS tube P1 The first regulating module 120 compensates for the problem of output current reduction caused by the increase of the drain voltage of the first PMOS tube P1, and maintains the charging current constant.

[0070]

[0071] Among them, KP is a process constant, VSG is the source-gate voltage difference of the PMOS tube, VTH is the threshold voltage, and the VTH of the PMOS tube is a negative value.

[0072] In one embodiment, see Figure 2, the second regulation module 140 includes: a discharge current regulation unit; the discharge current regulation unit includes a second feedback subunit, a third current source Ip1, a fourth current source Ip2 and a second current mirror; the first end of the second feedback subunit is connected to the drain of the first PMOS tube P1, the second end of the second feedback subunit is connected to the third current source Ip1, and the output end of the second feedback subunit is connected to the second end of the second current mirror; the second end of the second current mirror is connected to the discharge control unit 131, the third end of the second current mirror is connected to the first power supply through the fourth current source Ip2, and the fourth section of the first current mirror is grounded; the second feedback subunit is used to output a second signal when the output voltage is less than or equal to the second preset value, and the second signal is used to control the voltage difference between the source and the drain of the first NMOS tube N1 to maintain the discharge current constant; the currents output by the third current source Ip1 and the fourth current source Ip2 are equal.

[0073] In one embodiment, the second current mirror includes NMOS transistors N3 and N4, the source of N3 and the source of N4 are grounded, the drain of N3 and the drain of N4 are connected and connected to the fourth current source Ip2.

[0074] In one embodiment, see Figure 2 The second feedback subunit includes a second error amplifier U2 and an NMOS tube N2, the positive input terminal of the second error amplifier U2 is connected to the third current source Ip1, the negative input terminal of the second error amplifier U2 is connected to the drain of the first PMOS tube P1, and is used to receive the output voltage, the output terminal of the second error amplifier U2 is connected to the gate of N2, the drain of N2 is connected to the third current source Ip1, and the output terminal of the second error amplifier U2 is connected to the gate of N3.

[0075] Specifically, when the output voltage is less than or equal to the second preset value, the second preset value is close to the ground voltage, the second error amplifier U2 outputs a high level, N2 and N3 are turned on, the output current of N4 becomes smaller, the gate voltage of N4 decreases, and the gate voltages of N6 and N7 decrease at the same time. According to the current formula of the saturation region of the NMOS tube, when the discharge signal is received, the fourth selection subunit is turned on, the gate voltages of N8 and the first NMOS tube N1 increase, so that the gate-source voltage difference of the first NMOS tube N1 increases, thereby increasing the discharge current of the first NMOS tube N1 to reduce the problem of reduced output current due to the reduction of the drain voltage, and maintain the constant discharge current.

[0076]

[0077] Among them, KP is a process constant, VGS is the gate-source voltage difference of the NMOS tube, and VTH is the threshold voltage.

[0078] In one embodiment, if Figure 3As shown, Figure 3 A schematic diagram of the structure of a charge pump circuit provided in an embodiment of the present application. The first regulating module 120 includes: a first switch, a first voltage dividing unit, and a second voltage dividing unit; the first end of the first voltage dividing unit is connected to the first power supply, and the second end of the first voltage dividing unit is connected to the first end of the first switch and the substrate of the first PMOS tube P1; the second end of the first switch is connected to the first end of the second voltage dividing unit, and the control end of the first switch is connected to the output voltage; the second end of the second voltage dividing unit is grounded; the first switch is used to be in a conducting state when the output voltage is greater than or equal to the first preset value, and the first voltage dividing unit and the second voltage dividing unit are used to control the threshold voltage of the first PMOS tube P1 to maintain a constant charging current.

[0079] Optionally, the first voltage dividing unit is a first resistor, the second voltage dividing unit is a second resistor, and the first switch is an NMOS tube N13.

[0080] Specifically, when the output voltage of the first PMOS tube P1 is greater than or equal to the first preset value, N13 is turned on, and a VBP lower than the first power supply voltage is generated through voltage division by the first resistor and the second resistor. The substrate of the first PMOS tube P1 is connected to VBP, so that the threshold voltage VTH of the first PMOS tube P1 decreases. According to the current formula of the PMOS tube saturation region, the output current of the first PMOS tube P1 increases, thereby maintaining a constant charging current within a wide output voltage range.

[0081] In one embodiment, when the first switch is turned on, the voltage across the first voltage dividing unit is less than the turn-on voltage of the PN junction of the first PMOS tube P1.

[0082] Specifically, the voltage of VBP should satisfy the following formula to prevent the parasitic diode of the substrate of the first PMOS tube P1 from being turned on:

[0083]

[0084] Wherein, RN is the on-resistance of N13, Vpn is the on-voltage of the PN junction on the first PMOS tube P1, and VDD is the first power supply voltage.

[0085] In one embodiment, see Figure 3The second regulating module 140 includes: a second switch, a third voltage dividing unit and a fourth voltage dividing unit; the first end of the third voltage dividing unit is connected to the first power supply, and the second end of the third voltage dividing unit is connected to the first end of the second switch; the second end of the second switch is connected to the first end of the fourth voltage dividing unit and the substrate of the first NMOS tube N1, and the control end of the second switch is connected to the drain of the first PMOS tube P1; the second end of the fourth voltage dividing unit is grounded; the second switch is used to be in a conducting state when the output voltage is less than or equal to the second preset value, and the third voltage dividing unit and the fourth voltage dividing unit are used to control the threshold voltage of the first NMOS tube N1 to maintain a constant charging current.

[0086] Optionally, the third voltage dividing unit is a third resistor, the fourth voltage dividing unit is a fourth resistor, and the second switch is a PMOS tube P13.

[0087] Specifically, when the output voltage is less than or equal to the second preset value, P13 is turned on, the third resistor and the fourth resistor generate a voltage VBN, and the substrate of the first NMOS tube N1 is connected to the voltage divider VBN, so that the threshold voltage of the first NMOS tube N1 is reduced. According to the current formula of the NMOS tube saturation region mentioned above, the output current of the first NMOS tube N1 increases, thereby maintaining a constant discharge current within a wide output voltage range.

[0088] In one embodiment, when the second switch is turned on, the voltage across the fourth voltage dividing unit is less than the turn-on voltage of the PN junction of the first NMOS transistor N1.

[0089] Specifically, the voltage of VBN should satisfy the following formula to prevent the parasitic diode of the substrate of the first NMOS transistor N1 from being turned on.

[0090]

[0091] Wherein, RP is the on-state voltage of P13, and Vpn is the forward conduction voltage of the PN junction of the first NMOS tube N1.

[0092] In one embodiment, Figure 2 and Figure 3 The example scheme in can be implemented in one embodiment, wherein the principle is shown in Figure 2 and Figure 3 The description is not repeated here.

[0093] In one embodiment, the substrates of P2, P3, P4, P5, P6, P7 and P8 may all be connected to the second end of the first voltage divider unit to achieve better circuit matching.

[0094] In one embodiment, the substrates of N2, N3, N4, N5, N6, N7 and N8 may all be connected to the first end of the fourth voltage divider unit to achieve better circuit matching.

[0095] An embodiment of the present application provides a phase-locked loop circuit, comprising any of the above-mentioned charge pump circuits.

[0096] An embodiment of the present application provides an integrated circuit chip, comprising any of the above-mentioned charge pump circuits.

[0097] In the above embodiments, it should be understood that the processor can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the invention can be directly implemented as a hardware processor, or can be implemented by a combination of hardware and software modules in the processor.

[0098] The memory may include a high-speed memory (Random Access Memory, RAM), and may also include a non-volatile memory (NVM), such as at least one disk storage.

[0099] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the bus in the drawings of this application is not limited to only one bus or one type of bus.

[0100] The above-mentioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The readable storage medium can be any available medium that can be accessed by a general or special-purpose computer.

[0101] An exemplary readable storage medium is coupled to a processor so that the processor can read information from the readable storage medium and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can be located in an application specific integrated circuit (Application Specific Integrated Circuits, referred to as: ASIC). Of course, the processor and the readable storage medium can also exist in the device as discrete components.

[0102] The division of units is only a logical function division, and there may be other divisions in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other forms.

[0103] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0104] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0105] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0106] Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, disk or optical disk and other media that can store program codes.

[0107] Finally, it should be noted that those skilled in the art will readily conceive of other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. The present invention is intended to cover any variations, uses or adaptations of the present invention, which follow the general principles of the present invention and include common knowledge or customary technical means in the art not disclosed by the present invention, are not limited to the precise structure described above and shown in the drawings, and may be modified and changed in various ways without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A charge pump circuit, characterized in that: include: A first regulating module, a second regulating module, a charging module and a discharging module; The charging module includes a first PMOS tube and a charging control unit, wherein the source of the first PMOS tube is connected to the first power supply, the gate of the first PMOS tube is connected to the output end of the charging control unit, and the drain of the first PMOS tube is used to output an output voltage; the charging control unit is used to receive a charging signal and control the on and off of the first PMOS tube according to the charging signal; The discharge module includes a first NMOS tube and a discharge control unit, wherein the drain of the first NMOS tube is connected to the drain of the first PMOS tube, the source of the first NMOS tube is grounded, and the gate of the first NMOS tube is connected to the output end of the discharge control unit; the discharge control unit is used to receive a discharge signal and control the on and off of the first NMOS tube according to the discharge signal; The first end of the first regulating module is connected to the drain of the first PMOS tube, and the second end of the first regulating module is connected to the charging module; the first regulating module is used to regulate the charging current of the charging module according to the output voltage to maintain the charging current constant; The first end of the second regulating module is connected to the drain of the first PMOS tube, and the second end of the second regulating module is connected to the discharge module; the second regulating module is used to adjust the discharge current of the discharge module according to the output voltage to maintain the discharge current constant.

2. The charge pump circuit according to claim 1, characterized in that: The first regulating module comprises: a charging current regulating unit, the charging current regulating unit comprising a first feedback subunit, a first current source, a second current source and a first current mirror; A first end of the first feedback subunit is connected to the drain of the first PMOS tube, a second end of the first feedback subunit is grounded through the first current source, and an output end of the first feedback subunit is connected to a first end of the first current mirror; The second end of the first current mirror is connected to the charging control unit, the third end of the first current mirror is connected to the first power supply, and the fourth end of the first current mirror is grounded through the second current source; The first feedback subunit is used to output a first signal when the output voltage is greater than or equal to a first preset value, and the first signal is used to control the voltage difference between the source and the drain of the first PMOS tube to maintain the charging current constant; The first current source and the second current source output equal currents.

3. The charge pump circuit according to claim 1, characterized in that: The second regulating module comprises: a discharge current regulating unit; the discharge current regulating unit comprises a second feedback subunit, a third current source, a fourth current source and a second current mirror; The first end of the second feedback subunit is connected to the drain of the first PMOS tube, the second end of the second feedback subunit is connected to the third current source, and the output end of the second feedback subunit is connected to the second end of the second current mirror; The second end of the second current mirror is connected to the discharge control unit, the third end of the second current mirror is connected to the first power supply through the fourth current source, and the fourth section of the first current mirror is grounded; The second feedback subunit is used to output a second signal when the output voltage is less than or equal to a second preset value, and the second signal is used to control the voltage difference between the source and the drain of the first NMOS tube to maintain the discharge current constant; The third current source and the fourth current source output the same current.

4. The charge pump circuit according to claim 1, characterized in that: The first regulating module includes: a first switch, a first voltage dividing unit and a second voltage dividing unit; A first end of the first voltage dividing unit is connected to the first power supply, and a second end of the first voltage dividing unit is connected to a first end of the first switch and a substrate of the first PMOS tube; The second end of the first switch is connected to the first end of the second voltage dividing unit, the control end of the first switch is connected to the drain of the first PMOS tube; the second end of the second voltage dividing unit is grounded; The first switch is used to be in an on state when the output voltage is greater than or equal to a first preset value, and the first voltage dividing unit and the second voltage dividing unit are used to control the threshold voltage of the first PMOS tube to maintain the charging current constant.

5. The charge pump circuit according to claim 4, characterized in that: The second regulating module includes: a second switch, a third voltage dividing unit and a fourth voltage dividing unit; A first end of the third voltage dividing unit is connected to the first power supply, and a second end of the third voltage dividing unit is connected to a first end of the second switch; The second end of the second switch is connected to the first end of the fourth voltage dividing unit and the substrate of the first NMOS tube, and the control end of the second switch is connected to the drain of the first PMOS tube; the second end of the fourth voltage dividing unit is grounded; The second switch is used to be in an on state when the output voltage is less than or equal to a second preset value, and the third voltage dividing unit and the fourth voltage dividing unit are used to control the threshold voltage of the first NMOS tube to maintain the charging current constant.

6. The charge pump circuit according to any one of claims 1 to 5, characterized in that: The charging control unit comprises a first selection subunit, a second selection subunit, a fifth current source, a third current mirror and a fourth current mirror; The first end of the third current mirror is connected to the first power supply, the second end of the third current mirror is connected to the third end of the current mirror and the first end of the first selection subunit; the fourth end of the third current mirror is connected to the third end of the fourth current mirror and the second end of the first regulation module; The first end of the fourth current mirror is connected to the first power supply, the second end of the fourth current mirror is connected to the fourth end of the fourth current mirror and the first end of the second selection subunit, and the fourth end of the fourth current mirror is connected to the gate of the first PMOS tube; The second end of the first selection subunit is connected to the second end of the second selection subunit and the fourth current mirror; The control end of the first selection subunit is controlled by a complementary signal of the charging signal, and the control unit of the second selection subunit is controlled by the charging signal; the second selection subunit is used to turn on when receiving the charging signal, and the first selection subunit is used to turn on when receiving a complementary signal of the charging signal.

7. The charge pump circuit according to any one of claims 1 to 5, characterized in that: The discharge control unit includes a third selection subunit, a fourth selection subunit, a sixth current source, a fifth current mirror and a sixth current mirror; The first end of the sixth current source is connected to the first power source, and the second end of the sixth power source is connected to the first end of the third selection subunit and the first end of the fourth selection subunit; The second end of the third selection subunit is connected to the first end of the fifth current mirror, and the control end of the third selection subunit is controlled by a complementary signal of the discharge signal; The second end of the fifth current mirror is grounded, the third end of the fifth current mirror is connected to the fourth end of the sixth current mirror and the second end of the second regulating module, and the fourth end of the fifth current mirror is connected to the first end of the fifth current mirror; The second end of the fourth selection subunit is connected to the first end of the sixth current mirror, and the control end of the fourth selection subunit is controlled by the discharge signal; The second end of the sixth current mirror is grounded, and the third end of the sixth current mirror is connected to the gate of the first NMOS tube and the first end of the sixth current mirror.

8. The charge pump circuit according to claim 5, characterized in that: When the first switch is turned on, the voltage across the first voltage dividing unit is less than the turn-on voltage of the PN junction of the first PMOS tube; When the second switch is turned on, the voltage across the fourth voltage-dividing unit is less than the turn-on voltage of the PN junction of the first NMOS tube.

9. A phase-locked loop circuit, characterized in that: Comprising the charge pump circuit as claimed in any one of claims 1 to 8.

10. An integrated circuit chip, characterized in that: Comprising the charge pump circuit as claimed in any one of claims 1 to 8.

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