Power module

Abstract

This invention discloses a power module, comprising: a first PMIC module and a second PMIC module whose power input terminals are connected to a first power signal; and an enable input terminal of the first PMIC module and the second PMIC module connected to an external enable signal. The first PMIC module has a first power output port to a seventh power output port, its first signal output port and second signal output port connected to an external reset signal, its third signal output port for outputting fault signals of the first PMIC module and the second PMIC module, and its first signal input terminal and second signal input terminal connected to an external reset feedback signal. The second PMIC module's first power output port is connected to an external platform chip power supply terminal, its second power output port is connected to an external platform RAM module power supply terminal, its third power output port is connected to an external platform USB power supply terminal, its fourth power output port is connected to an external platform input / output port power supply terminal, and its fifth power output port is connected to an external platform phase-locked loop circuit power supply terminal.

Description

Technical Field

[0001] This invention relates to the field of electronic circuits, and in particular to a power supply module. Background Technology

[0002] PMIC (Power Management Integrated Circuits) is a power chip with multiple functions such as multi-output, configurable output voltage, fault monitoring, watchdog monitoring, and CPU fault monitoring. It is used in high reliability and high functional safety (ASIL_D) applications.

[0003] The design and development of power management technology is no longer limited to power technology itself, but requires a better integration of power supply with system-related safety functions to improve the overall system safety and stability. However, existing power management chips have the following shortcomings:

[0004] 1. The components are too separate, resulting in low integration and low peripheral resources and driving capabilities;

[0005] 2. The power module's fault protection and diagnostic mechanisms have a low safety level, failing to meet the high-functionality safety requirements of products such as intelligent driving domain controllers.

[0006] 3. The output voltage of the power module is fixed and cannot output multiple power rails according to design or usage requirements. Summary of the Invention

[0007] The summary of this invention introduces a series of simplified concepts, all of which are simplifications of existing technologies in the field, and will be further explained in detail in the detailed description section. This summary is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0008] The technical problem to be solved by the present invention is to provide a power module that can provide multiple different voltages and meet the ASILD safety level.

[0009] To solve the above-mentioned technical problems, the present invention provides a power module comprising:

[0010] The first PMIC module has a power input terminal connected to a first power signal, an enable input terminal connected to an external enable signal, a first communication port connected to a power configuration register and a power fault register, a second communication port connected to a watchdog configuration register and a watchdog fault register, a third communication port connected to the communication port of the second PMIC module, a first power output port connected to the external platform CPU power supply, a second power output port connected to the first external platform MCU domain power supply, a third power output port connected to the external PHY chip power supply, a fourth power output port connected to the external platform LPDDR4 power supply, and a fifth power output port. The source output port is connected to the input / output power supply terminal of the external platform MCU domain. It forms a sixth power output port connected to the power supply terminal of the external delay phase-locked loop (DDL) circuit. It forms a seventh power output port connected to the power supply terminal of the second external platform MCU domain. It forms a first signal output port connected to the external platform SOC reset signal receiving port. It forms a second signal output port connected to the external platform MCU reset signal receiving port. It forms a third signal output port for outputting fault signals of the first PMIC module and the second PMIC module. It forms a first signal input terminal connected to the external SOC domain reset feedback signal. It forms a second signal input terminal connected to the external MCU domain reset feedback signal.

[0011] The second PMIC module has a power input terminal connected to a first power signal, an enable input terminal connected to an external enable signal, a first power output port connected to the power supply terminal of an external platform chip, a second power output port connected to the power supply terminal of an external platform RAM module, a third power output port connected to the power supply terminal of an external platform USB, a fourth power output port connected to the power supply terminal of an external platform input / output port, and a fifth power output port connected to the power supply terminal of an external platform phase-locked loop (PLL) circuit.

[0012] Optionally, the power module can be further improved so that the first power signal is a 3.3V external hardware power supply signal.

[0013] Optionally, the power module can be further improved so that the first power output port and the second power output port of the first PMIC module output a 0.85V power signal.

[0014] Optionally, the power module can be further improved by having the third, fourth, fifth, and eighth power output ports of the first PMIC module output a 1.8V power signal.

[0015] Optionally, the power module can be further improved by having the sixth power output port of the first PMIC module output a 0.8V power signal.

[0016] Optionally, the power supply module can be further improved so that the first power output port of the second PMIC module outputs a 0.8V power signal.

[0017] Optionally, the power supply module can be further improved so that the second power output port of the second PMIC module outputs a 0.85V power signal.

[0018] Optionally, the power supply module can be further improved by having the third power output port of the second PMIC module output a 3.3V power signal.

[0019] Optionally, the power module can be further improved by having the fourth and fifth power output ports of the second PMIC module output 1.8V power signals.

[0020] Optionally, the power supply module can be further improved so that the electrical signals output from each power output port of the first PMIC module and the second PMIC module can be configured via an external platform or in the NVM of the PMIC module.

[0021] The power module provided by this invention can achieve at least the following technical effects:

[0022] 1. This invention can provide configurable sequence self-test and safe power-on / off for NVM (Non-volatile Memory), and provide different voltage rails for external controllers.

[0023] 2. By providing an external watchdog, this invention can be configured to meet the ASILD safety level in a question-and-answer mode, safely monitoring the input and output voltage rails, effectively preventing system short circuits and overcurrents, and avoiding damage to the external controller.

[0024] 3. This invention can provide different voltages based on complex MCUs and SOCs, and can independently reset the MCU domain and SOC domain when the system fails.

[0025] 4. This invention can be combined with the ESM (Error Signaling Module) of an external CPU. When the CPU malfunctions, it will transmit an error signal to the PMIC, and the PMIC will take corresponding safety measures according to different malfunctions.

[0026] 5. This invention can effectively detect its own temperature based on the temperature monitoring mechanism of the PMIC chip. When the temperature exceeds the set threshold, the associated enable pin closes the peripheral driver and reports the corresponding fault to the CPU via I2C.

[0027] 6. This invention provides an ADAS-oriented PDCU domain controller with high reliability and high functional safety (ASIL_D). Attached Figure Description

[0028] The accompanying drawings are intended to illustrate the general characteristics of the methods, structures, and / or materials used in specific exemplary embodiments of the invention, supplementing the description in the specification. However, the drawings are schematic diagrams not drawn to scale and may not accurately reflect the precise structural or performance characteristics of any of the given embodiments. The drawings should not be construed as limiting or restricting the range of numerical values ​​or properties covered by exemplary embodiments of the invention. The invention will now be described in further detail with reference to the accompanying drawings and specific embodiments:

[0029] Figure 1 This is a schematic diagram of the structure of the present invention.

[0030] Explanation of reference numerals in the attached figures

[0031] First PMIC Module 1

[0032] The first PMIC module power input terminal 1.1

[0033] Enable input 1.2 of the first PMIC module

[0034] The first communication port 1.3 of the first PMIC module.

[0035] The second communication port 1.4 of the first PMIC module.

[0036] The third communication port 1.5 of the first PMIC module

[0037] The first power output port 1.6 of the first PMIC module.

[0038] The second power output port 1.7 of the first PMIC module.

[0039] The third power output port 1.8 of the first PMIC module

[0040] The fourth power output port 1.9 of the first PMIC module.

[0041] The fifth power output port 1.10 of the first PMIC module

[0042] The sixth power output port 1.11 of the first PMIC module

[0043] The seventh power output port 1.12 of the first PMIC module

[0044] The first signal output port 1.13 of the first PMIC module

[0045] The second signal output port 1.14 of the first PMIC module

[0046] The first signal input terminal 1.15 of the first PMIC module.

[0047] The second signal input terminal 1.16 of the first PMIC module

[0048] The third signal output port 1.17 of the first PMIC module

[0049] Second PMIC module 2

[0050] The power input terminal 2.1 of the second PMIC module

[0051] Enable input 2.2 of the second PMIC module

[0052] The first power output port 2.3 of the second PMIC module.

[0053] The second power output port 2.4 of the second PMIC module.

[0054] The third power output port 2.5 of the second PMIC module.

[0055] The fourth power output port 2.6 of the second PMIC module

[0056] The fifth power output port 2.7 of the second PMIC module.

[0057] External platform 3. Detailed Implementation

[0058] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can fully understand other advantages and technical effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and the details in this specification can also be applied based on different viewpoints, with various modifications or changes made without departing from the overall design concept of the invention. It should be noted that, unless otherwise specified, the following embodiments and features can be combined with each other. The following exemplary embodiments of the present invention can be implemented in many different forms and should not be construed as being limited to the specific embodiments set forth herein. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete, and to fully convey the technical solutions of these exemplary embodiments to those skilled in the art.

[0059] It should be understood that when an element is referred to as "connected" or "joined" to another element, the element may be directly connected or joined to the other element, or there may be intermediate elements. In contrast, when an element is referred to as "directly connected" or "directly joined" to another element, there are no intermediate elements. Throughout the figures, the same reference numerals consistently denote the same elements.

[0060] refer to Figure 1As shown, the present invention provides a power module, comprising:

[0061] The first PMIC module 1 has a power input terminal 1.1 connected to a first power signal, an enable input terminal 1.2 connected to an external enable signal, and a first communication port 1.3 connected to a power configuration register and a power fault register. It also has a second communication port 1.4 connected to a watchdog configuration register and a watchdog fault register, a third communication port 1.5 connected to the communication port of the second PMIC module, a first power output port 1.6 connected to the external platform CPU power supply, a second power output port 1.7 connected to the first external platform MCU domain power supply, a third power output port 1.8 connected to the external PHY chip power supply, a fourth power output port 1.9 connected to the external platform LPDDR4 power supply, and a fifth power output port. Output port 1.10 connects to the input / output power supply terminal of the external platform MCU domain, forming a sixth power output port 1.11. Connects to the power supply terminal of the external delay phase-locked loop (DDL) circuit, forming a seventh power output port 1.12. Connects to the power supply terminal of the second external platform MCU domain, forming a first signal output port 1.13. Connects to the external platform SOC reset signal receiving port, forming a second signal output port 1.14. Connects to the external platform MCU reset signal receiving port, forming a third signal output port 1.17 for outputting fault signals of the first PMIC module and the second PMIC module, forming a first signal input terminal 1.15. Connects to the external SOC domain reset feedback signal, forming a second signal input terminal 1.16. Connects to the external MCU domain reset feedback signal.

[0062] The second PMIC module 2 has a power input terminal 2.1 connected to a first power signal, an enable input terminal 2.2 connected to an external enable signal, a first power output port 2.3 connected to the power supply terminal of an external platform chip, a second power output port 2.4 connected to the power supply terminal of an external platform RAM module, a third power output port 2.5 connected to the power supply terminal of an external platform USB, a fourth power output port 2.6 connected to the power supply terminal of an external platform input / output port, and a fifth power output port 2.7 connected to the power supply terminal of an external platform phase-locked loop (PLL) circuit.

[0063] Optional, wherein the first power signal is a 3.3V external hardware power supply signal.

[0064] Optionally, the first power output port and the second power output port of the first PMIC module output a 0.85V power signal.

[0065] Optionally, the third, fourth, fifth, and eighth power output ports of the first PMIC module output a 1.8V power signal.

[0066] Optional, wherein the sixth power output port of the first PMIC module outputs a 0.8V power signal.

[0067] Optional, wherein the first power output port of the second PMIC module outputs a 0.8V power signal.

[0068] Optional, wherein the second power output port of the second PMIC module outputs a 0.85V power signal.

[0069] Optional, the third power output port of the second PMIC module outputs a 3.3V power signal.

[0070] Optionally, the fourth and fifth power output ports of the second PMIC module output a 1.8V power signal.

[0071] Optionally, the electrical signals output from each power output port of the first PMIC module and the second PMIC module can be configured via an external platform or in the NVM of the PMIC module.

[0072] Furthermore, it should be understood that although the terms "first," "second," etc., may be used herein to describe different elements, parameters, components, regions, layers, and / or parts, these elements, parameters, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, parameter, component, region, layer, or part from another. Therefore, without departing from the teachings of exemplary embodiments according to the present invention, the first element, parameter, component, region, layer, or part discussed below may also be referred to as the second element, parameter, component, region, layer, or part. Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that, unless expressly defined herein, terms such as those defined in a general dictionary should be interpreted as having a meaning consistent with their meaning in the relevant field context, and not as having an ideal or overly formal meaning.

[0073] The present invention has been described in detail above through specific embodiments and examples, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A power module, characterized in that, include: The first PMIC module has a power input terminal connected to a first power signal, an enable input terminal connected to an external enable signal, a first communication port connected to a power configuration register and a power fault register, a second communication port connected to a watchdog configuration register and a watchdog fault register, a third communication port connected to the communication port of the second PMIC module, a first power output port connected to the external platform CPU power supply, a second power output port connected to the first external platform MCU domain power supply, a third power output port connected to the external PHY chip power supply, a fourth power output port connected to the external platform LPDDR4 power supply, and a fifth power output port. The source output port is connected to the input / output power supply terminal of the external platform MCU domain. It forms a sixth power output port connected to the power supply terminal of the external delay phase-locked loop (DDL) circuit. It forms a seventh power output port connected to the power supply terminal of the second external platform MCU domain. It forms a first signal output port connected to the external platform SOC reset signal receiving port. It forms a second signal output port connected to the external platform MCU reset signal receiving port. It forms a third signal output port for outputting fault signals of the first PMIC module and the second PMIC module. It forms a first signal input terminal connected to the external SOC domain reset feedback signal. It forms a second signal input terminal connected to the external MCU domain reset feedback signal. The second PMIC module has a power input terminal connected to a first power signal, an enable input terminal connected to an external enable signal, a first power output port connected to the power supply terminal of an external platform chip, a second power output port connected to the power supply terminal of an external platform RAM module, a third power output port connected to the power supply terminal of an external platform USB, a fourth power output port connected to the power supply terminal of an external platform input / output port, and a fifth power output port connected to the power supply terminal of an external platform phase-locked loop (PLL) circuit.

2. The power module as described in claim 1, characterized in that: The first power signal is the 3.3V external hardware power supply signal.

3. The power module as described in claim 1, characterized in that: The first power output port and the second power output port of the first PMIC module output a 0.85V power signal.

4. The power module as described in claim 1, characterized in that: The third, fourth, fifth, and eighth power output ports of the first PMIC module output a 1.8V power signal.

5. The power module as described in claim 1, characterized in that: The sixth power output port of the first PMIC module outputs a 0.8V power signal.

6. The power module as described in claim 1, characterized in that: The first power output port of the second PMIC module outputs a 0.8V power signal.

7. The power module as described in claim 1, characterized in that: The second power output port of the second PMIC module outputs a 0.85V power signal.

8. The power module as described in claim 1, characterized in that: The third power output port of the second PMIC module outputs a 3.3V power signal.

9. The power module as described in claim 1, characterized in that: The fourth and fifth power output ports of the second PMIC module output a 1.8V power signal.

10. The power module as described in any one of claims 1-9, characterized in that: The electrical signals output from each power output port of the first and second PMIC modules can be configured via an external platform or in the NVM of the PMIC module.

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