Temperature analog-to-digital converter, temperature sensor and vehicle equipment

Abstract

The invention relates to a temperature analog-to-digital converter, a temperature sensor and vehicle equipment. The temperature analog-to-digital converter comprises: a counter module configured to provide a count value based on a clock signal every time a reset signal is converted into an invalid level, the count value being a remainder obtained by dividing the number of passed clock cycles by n + 2; the register module is used for receiving the comparison result signal and is configured to sequentially read logic values provided by the comparison result signal along with the increase of the count value, output a digital temperature signal consisting of n-bit logic values when the count value is equal to n, and empty the registered n-bit logic values when the count value is equal to n + 1; and the signal generation module is configured to generate at least one control signal according to the count value, the period of each control signal is an integral multiple of the period of the clock signal, and each control signal corresponds to the value of one count value. The analog-to-digital converter can meet the performance requirements and the function requirements of the vehicle-mounted temperature sensor at the same time.

Description

Technical Field

[0001] This application relates to the field of electronic and electrical technology, and in particular to a temperature analog-to-digital converter, a temperature sensor, and vehicle equipment. Background Technology

[0002] With the continuous development and application of new energy vehicle technologies, more and more vehicles equipped with intelligent driving systems are appearing in people's daily lives. As the foundation for higher-level applications such as intelligent driving systems, onboard sensors provide environmental sensing data for the core controller to make judgments and decisions, greatly affecting the response speed, reliability, and safety of the entire intelligent driving system.

[0003] In automotive sensors, the analog-to-digital converter (ADC) is a crucial component, typically requiring performance specifications that meet requirements regarding resolution, conversion speed, accuracy, input range, power consumption, and interference immunity. Resolution refers to the smallest input signal variation that the ADC can distinguish; a high-resolution ADC can represent analog signals with greater precision. Conversion speed refers to the speed at which the ADC converts an analog signal into a digital signal. Accuracy refers to the degree of matching between the ADC's output digital signal and the input analog signal; error sources generally include quantization error, nonlinearity error, offset error, and gain error. Input range refers to the voltage range of analog signals that the ADC can process.

[0004] In practical applications, the analog-to-digital converters used by automotive temperature sensors are selected from a wide range of ADC products with various specifications and models, but these ADC products are difficult to fully match the actual application requirements of automotive temperature sensors. Summary of the Invention

[0005] This application provides a temperature analog-to-digital converter, a temperature sensor, and a vehicle device, which can realize an analog-to-digital converter that simultaneously meets the performance requirements and functional needs of an on-board temperature sensor.

[0006] This application provides a temperature analog-to-digital converter (ADC) for outputting an n-bit binary digital temperature signal, where n is an integer greater than 1. The temperature ADC includes:

[0007] A counter module is configured to receive a reset signal and a clock signal, and to provide a count value based on the clock signal each time the reset signal turns to an invalid level, the count value being the remainder of the number of clock cycles elapsed divided by n+2.

[0008] A register module, connected to the counter module, is configured to receive a comparison result signal, which provides a logical value representing the comparison result between a reference voltage signal and an analog temperature signal in each clock cycle. The register module is configured to: sequentially read the logical value provided by the comparison result signal as the count value increments; output the digital temperature signal consisting of n logical bits when the count value equals n; and clear the stored n logical bits when the count value equals n+1.

[0009] A signal generation module is connected to the counter module. The signal generation module is configured to generate at least one control signal based on the count value. The period of each control signal is an integer multiple of the period of the clock signal, and each control signal corresponds to a value of the count value.

[0010] In some possible implementations, the at least one control signal includes a sensitivity temperature compensation enable signal, which is active in the next clock cycle after each clock cycle in which the count value is equal to n-2, and is used to instruct the digital processing circuit receiving the digital temperature signal to perform a sensitivity temperature compensation operation.

[0011] In some possible implementations, the at least one control signal includes a temperature offset compensation enable signal, which is active in the next clock cycle after each clock cycle in which the count value is equal to n-1, and is used to instruct the digital processing circuit receiving the digital temperature signal to perform a temperature offset compensation operation.

[0012] In some possible implementations, the at least one control signal includes a reference voltage calculation enable signal, which is active in the next clock cycle after each clock cycle in which the count value is equal to n. The reference voltage calculation enable signal is used to instruct the digital processing circuit receiving the digital temperature signal to perform an operation of recalculating the reference voltage and applying it to the analog processing circuit that provides the comparison result signal.

[0013] In some possible implementations, the at least one control signal includes a start signal that transitions from an invalid level to an active level in the next clock cycle after the count value first equals 1 following each time the reset signal transitions to an invalid level, and transitions to an invalid level each time the reset signal transitions to an active level.

[0014] In some possible implementations, the register module is further configured to output the stored n-bit binary number to the analog signal processing circuit that provides the comparison result signal, so that the analog signal processing circuit determines, based on the n-bit binary number, the reference voltage signal to be compared with the analog temperature signal in the current period from among n candidate reference voltage signals.

[0015] In some possible implementations, the register module is configured to: reset all n-bit binary numbers to 0 when the count value is equal to n+1; register an identifier value to the m-th least significant bit of the n-bit binary number when the count value is equal to any one of 0 to n-1; and register the logic value currently provided by the comparison result signal to the (m+1)-th least significant bit of the n-bit binary number when the count value is equal to any one of 1 to n, where m is a positive integer and m = n - cq, and cq is the value of the count value.

[0016] This application also provides a temperature sensor, which includes at least one of the above-mentioned temperature analog-to-digital converters.

[0017] In some possible implementations, the temperature sensor further includes a clock generator, an analog signal processing circuit, and a digital signal processing circuit, each connected to the temperature analog-to-digital converter. The clock generator is used to provide the temperature analog-to-digital converter with the reset signal and the clock signal. The analog signal processing circuit is used to provide the temperature analog-to-digital converter with the comparison result signal. The digital signal processing circuit is used to receive the at least one control signal from the temperature analog-to-digital converter.

[0018] This application also provides a vehicle device, which includes at least one of the above-mentioned temperature sensors.

[0019] In the analog-to-digital converter (ADC) of this embodiment, the counter module counts the clock cycles of the clock signal, and the comparison result signal provides the logical value of the comparison result between the reference voltage signal and the analog temperature signal in each clock cycle. The register module reads the logical value provided by the comparison result signal sequentially as the count value increases and outputs it as a digital signal after extraction. At the same time, the signal generation module generates at least one control signal based on the count value. In this way, the ADC can not only achieve analog-to-digital conversion that meets the requirements of resolution, conversion speed and accuracy, but also easily generate the required control signal using the count value. Therefore, it can realize a high-performance ADC for automotive temperature sensors with a simpler architecture, which helps to improve the performance, reliability and stability of related products.

[0020] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0022] Figure 1 This is a structural block diagram of an analog-to-digital converter provided in an embodiment of this application;

[0023] Figure 2 This is a structural block diagram of a temperature sensor provided in an embodiment of this application;

[0024] Figure 3 This is a timing diagram of the control signals of an analog-to-digital converter provided in an embodiment of this application;

[0025] Figure 4 This is a schematic diagram of the state transition of an analog-to-digital converter provided in an embodiment of this application;

[0026] Figure 5 This is a structural block diagram of a vehicle device provided in an embodiment of this application. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0028] The terminology used in the embodiments section of this disclosure is for illustrative purposes only and is not intended to limit the disclosure. Unless otherwise defined, the technical or scientific terms used herein should be understood in their ordinary sense by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar words used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “a” or “one,” and similar words do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising,” “including,” or “containing,” and similar words mean that the elements or objects preceding “comprising,” encompass the elements or objects listed following “comprising,” and their equivalents, and do not exclude other elements or objects. The terms “connected,” “linked,” or “connected,” and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0029] Figure 1 This is a structural block diagram of an analog-to-digital converter provided in an embodiment of this application. See also... Figure 1The temperature analog-to-digital converter includes a counter module 11, a register module 12, and a signal generation module 13. Assuming the binary digital temperature signal output by the temperature analog-to-digital converter has n bits (n is an integer greater than 1), the main functions of each module are as follows.

[0030] Counter module 11 is used to receive reset signal rs and clock signal clk, and is configured to provide a count value cq based on clock signal clk starting each time reset signal rs turns to an invalid level. The count value cq is the remainder when the number of clock cycles elapsed is divided by n+2.

[0031] Register module 12 is connected to counter module 11 and is used to receive the comparison result signal din. The comparison result signal din provides the logical value of the comparison result between the reference voltage signal and the analog temperature signal in each clock cycle. Register module 12 is configured to: sequentially read the logical values ​​provided by the comparison result signal din as the count value cq increases; output a digital temperature signal consisting of n logical values ​​when the count value cq equals n; and clear the stored n logical values ​​when the count value cq equals n+1.

[0032] The signal generation module 13 is connected to the counter module 11. The signal generation module 13 is configured to generate at least one control signal based on the count value cq. The period of each control signal is an integer multiple of the period of the clock signal clk, and each control signal corresponds to a count value cq.

[0033] It should be noted that the temperature analog-to-digital converter and any of its components can be implemented as a pure hardware circuit structure, a pure software program, or a combination of both; the counter module 11 can be implemented, for example, based on a counter chip, a microcontroller storing a counting program, or other digital circuit structures with counting functions; the register module 12 and the signal generation module 13 can be implemented in a corresponding manner.

[0034] In one example, the reset signal rs is an externally provided control signal used to control the operation and reset of the temperature analog-to-digital converter. When the reset signal rs is active, the temperature analog-to-digital converter is in an idle or reset state and does not perform analog-to-digital conversion. When the reset signal rs changes from active to inactive, the counter module 11 begins to provide a count value cq in accordance with the periodic fluctuations of the clock signal clk. Taking a square wave clock signal with a frequency of 250MHz as an example, since the count value cq is the remainder of the number of clock cycles divided by n+2, the count value provided by the counter module 11 will start from 0 and increment by 1 every clock cycle at 4000 nanosecond intervals, that is, it will change sequentially to 1, 2, 3, ..., n, n+1, and then change back to 0 from n+1 in the next clock cycle. This cycle is repeated continuously during the period when the reset signal rs remains inactive.

[0035] In one example, as the count value cq changes continuously, register module 12 receives the logic value of the comparison result between the reference voltage signal and the analog temperature signal from the comparison result signal din in each clock cycle (for example, the logic value is 0 when the reference voltage signal is greater than or equal to the analog temperature signal in the current clock cycle, and the logic value is 1 when the reference voltage signal is greater than or equal to the analog temperature signal in the current clock cycle). It then sequentially receives n bits of logic value during the period when cq changes from 1 to n using a shift register method. When cq equals n, it outputs a digital temperature signal composed of these n bits of logic value dout (i.e., an n-bit binary digital temperature signal). When cq equals n+1, register module 12 clears the stored n bits of logic value.

[0036] In one example, signal generation module 13 generates one, two, three, four, five, or more control signals based on a count value cq for use by other components. Each of these control signals is generated based on a clock signal, and therefore its period is an integer multiple of the clock signal's period. "Generated based on a count value" means that a value of the corresponding count value cq is used as a parameter when generating the control signal, so that there is a correspondence between the phase of the control signal in each cycle and the relative position of the corresponding count value cq in the range of 0 to n+1. For example, the count value cq of 3 occupies 1 / (n+2) of the time period from 0 to n+1. The control signal corresponding to the count value cq of 3 can be low in one clock cycle corresponding to cq=3 every n+2 clock cycles, and high in other clock cycles. Thus, the period of this control signal is n+2 times the clock cycle, and there is a correspondence between the phase of this control signal and the relative position of the count value cq of 3 in the range of 0 to n+1.

[0037] As can be seen, in the analog-to-digital converter of this application embodiment, the counter module counts the clock cycles of the clock signal, and the comparison result signal provides the logical value of the comparison result between the reference voltage signal and the analog temperature signal in each clock cycle. The register module reads the logical value provided by the comparison result signal in sequence as the count value increases and outputs it as a digital signal after extraction. At the same time, the signal generation module generates at least one control signal based on the count value. In this way, the analog-to-digital converter can not only achieve analog-to-digital conversion that meets the requirements of resolution, conversion speed and accuracy, but also can easily generate the required control signal using the count value. Therefore, it can realize a high-performance analog-to-digital converter for automotive temperature sensors with a simpler architecture, which helps to improve the performance, reliability and stability of related products.

[0038] Figure 2 This is a structural block diagram of a temperature sensor provided in an embodiment of this application. See also... Figure 2 The temperature sensor includes a temperature analog-to-digital converter 10, and also includes a clock generator 20, an analog signal processing circuit 30, and a digital signal processing circuit 40, all connected to the temperature analog-to-digital converter 10. The clock generator 20 provides a reset signal rs and a clock signal clk to the temperature analog-to-digital converter, the analog signal processing circuit 30 provides a comparison result signal din to the temperature analog-to-digital converter, and the digital signal processing circuit 40 receives at least one control signal from the temperature analog-to-digital converter. Figure 2 The temperature analog-to-digital converter 10 shown includes a counter module and a register module as described above, and also includes an inverter connected to the counter module and the register module respectively (used to invert the digital temperature signal output by the register module to obtain the temperature detection signal temp); the temperature analog-to-digital converter 10 also includes the signal generation module described above, but for clarity, it is... Figure 2 It is not shown in the text.

[0039] like Figure 2 As shown, in one example, the control signals include a sensitivity temperature compensation enable signal ens, a temperature offset compensation enable signal enf, a reference voltage calculation enable signal env, and a start signal st. Figure 3 This is a timing diagram of the control signals of an analog-to-digital converter provided in an embodiment of this application. Figure 3 In the example above, n = 7. See also... Figure 2 and Figure 3The aforementioned sensitivity temperature compensation enable signal ens is active in the next clock cycle following each clock cycle in which the count value cq equals 5 (i.e., n-2) (i.e., the clock cycle corresponding to cq = 6). This sensitivity temperature compensation enable signal ens is used to instruct the digital processing circuit 40 that receives the temperature detection signal temp (i.e., the processed digital temperature signal) to perform a sensitivity temperature compensation operation. See also [example example]. Figure 2 The Sensitivity Temperature Compensation (STC) unit in the digital processing circuit 40 performs a sensitivity temperature compensation operation every 8 (n-1) clock cycles when triggered by the sensitivity temperature compensation enable signal ens. Based on the previously obtained temperature sensing signal (composed of n-2 binary numbers, i.e., 7 bits), it generates a temperature sensing signal sens composed of 8 (n-1) binary numbers (i.e., 8 bits) as the output signal of the temperature sensor.

[0040] See Figure 2 and Figure 3 The aforementioned temperature offset compensation enable signal enf is active in the next clock cycle (i.e., the clock cycle corresponding to cq = 7) after each clock cycle in which the count value cq equals 6 (i.e., n-1). This temperature offset compensation enable signal enf instructs the digital processing circuit 40, which receives the temperature detection signal temp (i.e., the processed digital temperature signal), to perform a temperature offset compensation operation. See also: Figure 2 The temperature offset compensation (OTC) unit in the digital processing circuit 40 performs a temperature offset compensation operation every 8 (i.e. n-1) clock cycles when triggered by the temperature offset compensation enable signal enf. It generates a temperature offset compensated temperature sensing signal offs composed of 9 (i.e. n) binary numbers (i.e. 9 bits) based on the previously obtained temperature sensing signal (composed of n-2 binary numbers, i.e. 7 bits) as the output signal of the temperature sensor.

[0041] See Figure 2 and Figure 3 The aforementioned start signal st transitions from an invalid level to an active level in the next clock cycle after the count value cq first equals 1 (i.e., the clock cycle corresponding to the first time cq equals 2), following each time the reset signal rs transitions to an invalid level. It then transitions to an invalid level each time the reset signal rs transitions to an active level (not in the clock cycle). Figure 3 (As shown in the image). In one example, see [image / reference]. Figure 2The processor in the digital processing circuit 40 receives the start signal st to determine the operating state of the temperature analog-to-digital converter 10 based on the start signal st, and can execute the required control strategy in combination with other parameters.

[0042] In some possible implementations, register module 12 is also configured to output the stored n-bit binary number to analog signal processing circuit 30 that provides the comparison result signal din, so that analog signal processing circuit 30 determines the reference voltage signal to be compared with the analog temperature signal in the current cycle from n candidate reference voltage signals based on the n-bit logic value (n-bit binary number) dout.

[0043] In some possible implementations, register module 12 is configured to: reset all n-bit binary numbers to 0 when the count value cq equals n+1; register the flag value to the m-th least significant bit of the n-bit binary number when the count value cq equals any one of 0 to n-1; and register the logic value currently provided by the comparison result signal to the (m+1)-th least significant bit of the n-bit binary number when the count value cq equals any one of 1 to n, where m is a positive integer and m = n - cq.

[0044] Figure 4 This is a schematic diagram of the state transition of an analog-to-digital converter provided in an embodiment of this application. Figure 4 Each circle in the equation represents an operation performed by the register module within one clock cycle. The equations within the circles represent the values ​​on the right side of the equation being assigned to the parameters on the left side. dou[6], dou[5], dou[4], dou[3], dou[2], dou[1], and dou[0] are the seven binary numbers (arranged from the most significant bit to the least significant bit) stored in the register module. In ascending order, dou[0] is the first least significant bit, dou[1] is the second least significant bit, dou[2] is the third least significant bit, dou[3] is the fourth least significant bit, dou[4] is the fifth least significant bit, dou[5] is the sixth least significant bit, and dou[6] is the seventh least significant bit (i.e., the most significant bit). The relationship between these seven binary numbers and the count value cq is shown in Table 1 below.

[0045]

[0046] Table 1 shows the relationship between the binary numbers and count values ​​stored in the register module.

[0047] like Figure 4As shown in Table 1, in the idle state, all 7 binary numbers registered by the register module are 0, represented by dou = 0; in the first clock cycle at the beginning of each working cycle, the count value cq is equal to 0, and in this clock cycle, dou[6] is assigned the flag value True, and the other bits are kept at 0. The flag value True represents the digital level of valid or logically true, and is used by the analog signal processing circuit 30 to determine which candidate reference voltage signal to use; in the second clock cycle, the count value cq is equal to 1, and the register module begins to receive the logic value provided by the comparison result signal din (that is, the logic level value of the comparison result signal din in this clock cycle), and registers the logic value to the register module. The 7th least significant bit dou[6] of the 7-bit binary number is registered (at this time cq=1, n=7, m+1=n+1-cq=7, i.e., the 7th least significant bit dou[6]), and the flag value True is registered to the 6th least significant bit dou[5] of the 7-bit binary number registered by the register module (at this time m=n-cq=6, i.e., the 6th least significant bit dou[5]); in the third clock cycle, the count value cq equals 2, and the register module registers the logic value provided by the comparison result signal din (i.e., the level logic value of the comparison result signal din in this clock cycle) to the 6th least significant bit dou[5] of the 7-bit binary number registered by the register module (at this time cq=2, n=7, m+1=n+1-cq=7, i.e., the 7th least significant bit dou[6]). q = 6, i.e., the 6th least significant bit dou[5]), and register the flag value True to the 5th least significant bit dou[4] of the 7-bit binary number stored in the register module (at this time m = n - cq = 5, i.e., the 5th least significant bit dou[5]); in the fourth clock cycle, the count value cq equals 3, the register module registers the logic value provided by the comparison result signal din (i.e., the level logic value of the comparison result signal din in this clock cycle) to the 5th least significant bit dou[4] of the 7-bit binary number stored in the register module (at this time cq = 3, n = 7, m + 1 = n + 1 - cq = 5, i.e., the 5th least significant bit dou[4]), and registers the flag value True to the 7-bit binary number stored in the register module. The fourth least significant bit of the binary number is dou[4] (at this time m = n - cq = 4, that is, the fourth least significant bit dou[3]); in the fifth clock cycle, the count value cq equals 4, the register module registers the logic value provided by the comparison result signal din (that is, the level logic value of the comparison result signal din in this clock cycle) to the fourth least significant bit dou[3] of the 7-bit binary number registered by the register module (at this time cq = 4, n = 7, m + 1 = n + 1 - cq = 4, that is, the fourth least significant bit dou[3]), and registers the flag value True to the third least significant bit dou[2] of the 7-bit binary number registered by the register module (at this time m = n - cq = 3, that is, the third least significant bit dou[2]);During the sixth clock cycle, the count value cq equals 5. The register module stores the logic value provided by the comparison result signal din (i.e., the level logic value of the comparison result signal din during this clock cycle) into the third least significant bit dout[2] of the 7-bit binary number stored in the register module (at this time, cq = 5, n = 7, m + 1 = n + 1 - cq = 3, i.e., the third least significant bit dout[2]), and stores the flag value True into the second least significant bit dout[1] of the 7-bit binary number stored in the register module (at this time, m = n - cq = 2, i.e., the second least significant bit dout[1]); During the seventh clock cycle, the count value cq equals 6. The register module stores the logic value provided by the comparison result signal din (i.e., the level logic value of the comparison result signal din during this clock cycle) into the second least significant bit dout[1] of the 7-bit binary number stored in the register module (at this time, cq = 6, n = 7, m + 1 = 5 ... n+1-cq=2, i.e. the second least significant bit dou[1]), and register the flag value True to the first least significant bit dou[0] of the 7-bit binary number registered by the register module (at this time m=n-cq=1, i.e. the first least significant bit dou[0]); in the eighth clock cycle, the count value cq equals 7, the register module registers the logic value provided by the comparison result signal din (i.e. the level logic value of the comparison result signal din in this clock cycle) to the first least significant bit dou[0] of the 7-bit binary number registered by the register module (at this time cq=7, n=7, m+1=n+1-cq=1, i.e. the first least significant bit dou[0]), and outputs a digital temperature signal composed of n-bit logic value dou; in the ninth clock cycle, the count value cq equals 8 (i.e. equals n+1), the register module resets all the registered n-bit binary numbers to 0 in preparation for entering the next working cycle. Thus, as the counter value cq provided by the counter module continuously cycles, the working cycle described above also continuously repeats, and the temperature analog-to-digital converter 10 outputs each set of digital temperature signals composed of n-bit logic values ​​dou sequentially over time.

[0048] In the above process, the position of the True flag determines which candidate reference voltage signal the analog temperature signal should be compared with in the next clock cycle. Therefore, the analog signal processing circuit 30 can determine the reference voltage signal to be compared with the analog temperature signal in the current cycle based on the position of the True flag in the n-bit logic value (n-bit binary number) dou (for example, True in the highest bit indicates that the analog temperature signal should be compared with the candidate reference voltage signal corresponding to the highest bit in the next clock cycle; True not in any bit indicates that no comparison result signal din needs to be provided in the next clock cycle). Thus, no additional feedback signal needs to be added to the analog signal processing circuit 30, which simplifies the system architecture.

[0049] See Figure 2 , Figure 3 and Figure 4 The aforementioned reference voltage calculation enable signal env is active in the next clock cycle following each clock cycle in which the count value cq equals 7 (i.e., equal to n) (i.e., the clock cycle corresponding to cq = 8). This reference voltage calculation enable signal env instructs the digital processing circuit 40, which receives the temperature detection signal temp (i.e., the processed digital temperature signal), to recalculate the reference voltage and apply it to the analog processing circuit 30, which provides the comparison result signal din. See also: Figure 2 The digital processing circuit 40, triggered by the reference voltage calculation enable signal env, performs a reference voltage update operation every 8 (n-1) clock cycles. This re-determines the voltage values ​​of 7 (n) candidate reference voltage signals according to a pre-set method and updates them in the analog processing circuit 30. The updated candidate reference voltage signals are then used to generate the comparison result signal din in the next operating cycle (9 clock cycles). This method helps improve the accuracy of analog-to-digital conversion.

[0050] Figure 5 This is a structural block diagram of a vehicle device provided in an embodiment of this application. See also... Figure 5 The vehicle equipment includes at least one of the above-mentioned temperature sensors 100. Figure 2 The temperature sensor shown (which can be considered as an example) also includes a controller 200 connected to each of the temperature sensors 100. In one example, the controller 200 is connected to at least one output of the temperature sensor 100 to obtain at least one of the aforementioned digital temperature signal, temperature sensing signal sens, and compensated temperature sensing signal offs, thereby obtaining temperature sensing data at the corresponding location.

[0051] In one example, the controller 200 described above may include one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components.

[0052] As can be seen, in the temperature analog-to-digital converter used by the temperature sensor of the vehicle equipment in this application embodiment, the counter module counts the clock cycles of the clock signal, and the comparison result signal provides the logical value of the comparison result between the reference voltage signal and the analog temperature signal in each clock cycle. The register module reads the logical value provided by the comparison result signal in sequence as the count value increases and outputs it as a digital signal after extraction. At the same time, the signal generation module generates at least one control signal based on the count value. In this way, the temperature analog-to-digital converter can not only achieve analog-to-digital conversion that meets the requirements of resolution, conversion speed and accuracy, but also can easily generate the required control signal using the count value. Therefore, a high-performance temperature analog-to-digital converter for vehicle temperature sensors can be realized with a simpler architecture, which helps to improve the performance, reliability and stability of related products.

[0053] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A temperature analog-to-digital converter, characterized in that: The temperature analog-to-digital converter is used to output an n-bit binary digital temperature signal, where n is an integer greater than 1, and the temperature analog-to-digital converter includes: A counter module, the counter module is used to receive a reset signal and a clock signal, and is configured to provide a count value based on the clock signal starting from each time the reset signal turns to an invalid level, the count value being a remainder of the number of clock cycles passed divided by n+2; a register module, the register module being connected to the counter module, the register module being used to receive a comparison result signal, the comparison result signal providing a logic value of a comparison result between a reference voltage signal and an analog temperature signal in each clock cycle, the register module being configured to: sequentially read the logic values ​​provided by the comparison result signal as the count value increases, output the digital temperature signal consisting of an n-bit logic value when the count value is equal to n, and clear the stored n-bit logic value when the count value is equal to n+1; and A signal generating module, wherein the signal generating module is connected to the counter module, and the signal generating module is configured to generate at least one control signal according to the count value, wherein the period of each of the control signals is an integer multiple of n+2, and each of the control signals corresponds to a numerical value of the count value.

2. The temperature analog-to-digital converter according to claim 1, characterized in that: The at least one control signal includes a sensitivity temperature compensation enable signal, which is at a valid level in the next clock cycle of each clock cycle in which the count value is equal to n-2, and the sensitivity temperature compensation enable signal is used to instruct the digital processing circuit that receives the digital temperature signal to perform a sensitivity temperature compensation operation.

3. The temperature analog-to-digital converter according to claim 1, characterized in that: The at least one control signal includes a temperature offset compensation enable signal, which is at a valid level in the next clock cycle of each clock cycle in which the count value is equal to n-1, and the temperature offset compensation enable signal is used to instruct the digital processing circuit receiving the digital temperature signal to perform a temperature offset compensation operation.

4. The temperature analog-to-digital converter according to claim 1, characterized in that: The at least one control signal includes a reference voltage calculation enable signal, which is at a valid level in the next clock cycle of each clock cycle in which the count value is equal to n, and the reference voltage calculation enable signal is used to instruct the digital processing circuit that receives the digital temperature signal to perform the operation of recalculating the reference voltage and applying it to the analog processing circuit that provides the comparison result signal.

5. The temperature analog-to-digital converter according to claim 1, characterized in that: The at least one control signal includes a start signal, which changes from an invalid level to a valid level in a clock cycle next to a clock cycle in which the count value first equals 1 after the reset signal changes to an invalid level each time, and changes to an invalid level each time the reset signal changes to a valid level.

6. The temperature analog-to-digital converter according to any one of claims 1 to 5, characterized in that: The register module is also configured to output the stored n-bit binary number to the analog signal processing circuit that provides the comparison result signal, so that the analog signal processing circuit determines the reference voltage signal to be compared with the analog temperature signal in the current cycle from among n candidate reference voltage signals based on the n-bit binary number.

7. The temperature analog-to-digital converter according to claim 6, characterized in that: The register module is configured to: reset all the stored n-bit binary numbers to 0 when the count value is equal to n+1, store the identification value in the mth lowest bit of the stored n-bit binary number when the count value is equal to any one from 0 to n-1, and store the logic value currently provided by the comparison result signal in the m+1th lowest bit of the stored n-bit binary number when the count value is equal to any one from 1 to n, where m is a positive integer and m=n-cq, and cq is the numerical value of the count value.

8. A temperature sensor, characterized in that: The temperature sensor comprises a temperature analog-to-digital converter according to any one of claims 1 to 7.

9. The temperature analog-to-digital converter according to claim 8, characterized in that: The temperature sensor also includes a clock generator, an analog signal processing circuit and a digital signal processing circuit respectively connected to the temperature analog-to-digital converter, the clock generator is used to provide the reset signal and the clock signal to the temperature analog-to-digital converter, the analog signal processing circuit is used to provide the comparison result signal to the temperature analog-to-digital converter, and the digital signal processing circuit is used to receive the at least one control signal from the temperature analog-to-digital converter.

10. A vehicle device, characterized in that: The vehicle device comprises at least one temperature sensor as claimed in claim 8 or 9.

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