Capacitance sensor reading circuit based on negative capacitance and parasitic capacitance calibration and parasitic capacitance calibration method
By adopting negative capacitance-based parasitic capacitance calibration technology in the capacitance sensor readout circuit, the problem of low-frequency flicker noise and parasitic capacitance affecting sensing accuracy is solved, high-precision large-bandwidth capacitance sensing is achieved, and the calibration process is simplified.
Patent Information
- Application Number
- CN202510040454.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-10
- Publication Date
- 2025-05-16
AI Technical Summary
The existing capacitance sensor readout circuit is affected by flicker noise at low frequencies, and parasitic capacitance affects the sensing accuracy. It is difficult for the prior art to effectively solve these problems.
The parasitic capacitance calibration technology based on negative capacitors is adopted, and the combination of negative capacitors, transimpedance amplifiers and DC servo loops is used to automatically calibrate the parasitic capacitance, eliminating the impact of parasitic capacitance at the input on the performance of transimpedance amplifiers.
High-precision large bandwidth capacitive sensing is achieved, reducing the impact of flicker noise, and avoiding the complexity of manual calibration through automatic calibration and improving detection accuracy.
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Figure CN120017056A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of integrated circuits, and in particular, relates to a capacitance sensor readout circuit based on negative capacitance parasitic capacitance calibration and a parasitic capacitance calibration method. Background Art
[0002] With the continuous advancement of sensing technology, capacitive sensors with various capacitors as sensitive elements have been widely used. With the development of micro-electro-mechanical system (MEMS) technology, capacitive sensitive elements have the advantages of low power consumption, small size, excellent dynamic characteristics and support for non-contact measurement. The sensitive element of a capacitive sensor is usually formed by a parallel plate capacitor structure. Since the dielectric loss between the two plates is usually very small, it can achieve extremely high detection accuracy and is very suitable for detecting weak signals.
[0003] Capacitive sensors usually work in a lower frequency band. At low frequencies, flicker noise is one of the main factors affecting circuit accuracy. In order to reduce the impact of flicker noise, existing circuits generally use Figure 1 The lock-in amplifier shown in the figure is used for circuit readout. In this architecture, the external excitation signal makes the capacitive sensor C s There is a signal current i s The signal current i s A changing signal voltage is generated through a transimpedance amplifier (TIA), which contains the detection information of the capacitive sensor. After that, this voltage passes through a dual-channel demodulation circuit to generate two low-frequency changing signals. Among them, the signal of the I channel represents the information of the capacitance change.
[0004] According to the different transimpedance elements, transimpedance amplifiers can be divided into resistive transimpedance amplifiers and capacitive transimpedance amplifiers. Figure 2 As shown. For the resistor feedback transimpedance amplifier, there is a design compromise between its accuracy, speed and gain, which is not suitable for application in design scenarios that require both large bandwidth and high accuracy. Therefore, the capacitive sensor readout circuit based on the phase-locked amplifier architecture usually adopts Figure 2 The circuit architecture is shown on the right.
[0005] In the case of input DC current, the capacitor feedback transimpedance amplifier is prone to saturation, so a DC bias circuit is required to ensure that the TIA has a correct static operating point. In the existing technical solutions, a more suitable solution is to use a DC servo loop (DSL). The specific structure of DSL is as follows Figure 3 As shown, the integrator only amplifies the low-frequency signal, so that the DC current in the circuit can pass through the resistor R dc It is drawn away by the DSL, thus stabilizing the output DC point of the TIA.
[0006] For capacitive feedback transimpedance amplifiers, considering their application requirements in the field of high-precision capacitive sensing, their sensing accuracy is affected and restricted by parasitic capacitance. Figure 4 As shown in Figure 1, the parasitic capacitance introduced by the electronic circuit and the sensor circuit has multiple sources, including: the sensor itself, PCB circuit, chip pins, ESD protection circuit, main op amp, etc. This value is usually in the order of picofarads (~pF).
[0007] The pF level parasitics of the input node will significantly affect the detection accuracy of the capacitive sensing circuit. This is because the capacitive feedback transimpedance amplifier is very sensitive to the parasitics of the input node. The theoretical analysis is as follows, considering only the equivalent input noise of the main op amp Then the equivalent capacitor noise can be characterized as follows:
[0008]
[0009] Among them, c s is the capacitance value of the capacitive sensor, c f is the feedback capacitor, c p is the parasitic capacitance of the circuit input node. The equivalent capacitance noise shown in this formula represents the detection accuracy finally achieved by the circuit. Summary of the invention
[0010] In view of the above-mentioned deficiencies of the prior art, the present invention provides a capacitance sensor readout circuit and a parasitic capacitance calibration method based on negative capacitance parasitic capacitance calibration. The capacitance sensor readout circuit implemented based on negative capacitance of the present invention can achieve very high accuracy. In addition, the present invention realizes automatic calibration of parasitic capacitance, avoiding the complexity of manual calibration.
[0011] The technical solution of the present invention is specifically as follows.
[0012] The present invention provides a capacitance sensor readout circuit based on negative capacitance parasitic capacitance calibration, which has high precision, large bandwidth and input DC current processing capability; the circuit comprises a negative capacitance, a transimpedance amplifier TIA and a DC servo loop DSL; wherein the negative capacitance circuit is connected to the input end of the transimpedance amplifier, connected to a parasitic capacitance C_p and a resistor R_dc providing a DC bias, and functions to eliminate the influence of the input end parasitic capacitance on the performance of the transimpedance amplifier; the DC servo loop DSL is connected to both ends of the feedback capacitor of the transimpedance amplifier, and functions to provide a DC bias for the transimpedance amplifier in a capacitive coupling form; wherein: the negative capacitance is composed of a forward amplifier and a positive feedback capacitor; the forward amplifier is fed back by a capacitor, and its gain is
[0013] A=1+C_(p,cal) / C_1
[0014] In the formula, C_(p,cal) is the capacitor connected between the common mode level V_CM and the negative input terminal of the op amp, and C_1 is the feedback capacitor connected between the negative input terminal and the output terminal of the op amp; C_(p,cal) is implemented by an adjustable capacitor array CDAC, and the final equivalent negative capacitance value is
[0015]
[0016] In the formula, C c is the size of the positive feedback capacitor, which is connected between the output of the forward amplifier and the input of the transimpedance amplifier. From the expression of the equivalent negative capacitance, it can be seen that when the equivalent capacitance value C eq and parasitic capacitance C p When they are equal, the parasitic capacitance is calibrated;
[0017] The capacitance sensor readout circuit has two operating modes: calibration mode and sensing mode;
[0018] In calibration mode, the external excitation and the transimpedance amplifier TIA are disconnected from the negative capacitor, and the resistor R dc Connect to V CM Used to provide DC bias for this circuit; the negative capacitor is directly connected to the input of the circuit to affect its parasitic capacitance C p Perform calibration;
[0019] In the sensing mode, the negative capacitor is connected to the transimpedance amplifier TIA for capacitive signal sensing; C s By the external excitation signal V AC Driven by the transistor, a signal current is generated, which is converted into a signal voltage by the transimpedance amplifier TIA; the transimpedance amplifier TIA is connected to the demodulator module demodulator to generate the final output signal.
[0020] In the present invention, the adjustable capacitor array CDAC is a MIM capacitor.
[0021] The present invention also provides a parasitic capacitance calibration method based on the above-mentioned capacitance sensor readout circuit. During the calibration process, the circuit stability is judged by the change of the pole frequency, and the negative capacitance value is adjusted until it is compensated to the ideal state; automatic calibration of the negative capacitance is achieved through oscillation detection and successive approximation register SAR logic; the oscillation detection circuit judges the negative capacitance compensation state, and adjusts the compensation value through feedback, and the successive approximation SAR logic adjusts the adjustable capacitance array CDAC.
[0022] In the present invention, the oscillation detection circuit is generated by two comparators and an OR gate; the positive input terminal of one comparator is connected to the input signal, and the negative input terminal is connected to the reference voltage V CM -V TH , V TH is a reconstructible voltage value; the negative input terminal of the other comparator is connected to the input signal, and the positive input terminal is connected to another reference voltage V CM +V TH , V TH is a reconfigurable voltage value; the outputs of the two comparators are operated through an OR gate to obtain the final detection result; the oscillation detection circuit is used to detect whether the input signal is within V CM -V TH With V CM +V TH A jump occurs between the detection circuits, that is, whether oscillation occurs.
[0023] In the present invention, the output terminal v of the op amp in the negative capacitor p,cal will oscillate during overcompensation, and the capacitance of CDAC will decrease; when v p,cal When the capacitance of CDAC increases, the circuit is stable. After several clock cycles, the circuit completes the adjustment of CDAC, and the overall capacitance of CDAC is c p,cal Converges to the parasitic capacitance c p nearby.
[0024] Compared with the prior art, the present invention has the following beneficial effects:
[0025] (1) Compared with the traditional capacitive sensor readout circuit, the capacitive sensing readout circuit based on negative capacitance can achieve very high accuracy.
[0026] (2) The present invention realizes automatic calibration of parasitic capacitance and avoids the complexity of manual calibration. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 A lock-in amplifier is used in the readout circuit of a capacitive sensor.
[0028] Figure 2 It is a resistive feedback transimpedance amplifier and a capacitive feedback transimpedance amplifier.
[0029] Figure 3 It is a capacitive feedback transimpedance amplifier that uses a DC servo loop for biasing.
[0030] Figure 4 Schematic diagram of input node parasitic capacitance.
[0031] Figure 5 Schematic diagram of the circuit architecture of the calibration mode and the detection mode.
[0032] Figure 6 The present invention is a capacitive sensor readout circuit based on negative capacitance parasitic capacitance calibration.
[0033] Figure 7 This is a schematic diagram of a negative capacitor circuit.
[0034] Figure 8 This is a schematic diagram of the automatic calibration logic circuit.
[0035] Fig. 9 Schematic diagram of the automatic calibration process of negative capacitance.
[0036] Fig.10 This is a test chart of capacitance detection accuracy.
[0037] Fig.11 This is an electron microscope photo of a lock-in amplifier chip based on automatic calibration of parasitic capacitance. DETAILED DESCRIPTION
[0038] The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings and embodiments.
[0039] The present invention proposes a parasitic capacitance cancellation technology based on negative capacitor (NC) to improve the overall accuracy of the capacitance detection front end. Since the size of the parasitic capacitance is affected by various factors such as the ambient temperature of the circuit and the structural size, it has a large uncertainty. Conventional sensor readout circuits usually use manual calibration to make the circuit have more appropriate parameter values, which increases the complexity of use. Therefore, the present invention also realizes automatic calibration of negative capacitance, replacing complex manual calibration.
[0040] like Figure 5 As shown, the capacitance sensor readout circuit based on negative capacitance parasitic capacitance calibration proposed by the present invention has two working modes: calibration mode and sensing mode. In use, the circuit is first switched to the calibration mode, and after the calibration is completed, it is switched to the sensing mode to output a high-precision capacitance sensing signal.
[0041] In calibration mode, the external excitation and the transimpedance amplifier TIA are disconnected from the negative capacitor, and the resistor R dc Connect to V CM It is used to provide DC bias for this circuit. The negative capacitor NC is directly connected to the input of the circuit to affect its parasitic capacitance C p Perform calibration.
[0042] In the sensing mode, the negative capacitor is connected to the transimpedance amplifier TIA for capacitive signal sensing. s By the external excitation signal V AC The TIA is connected to the demodulator module to generate the final output signal.
[0043] like Figure 6 As shown, the negative capacitor consists of a forward amplifier and a positive feedback capacitor. Figure 6 The circuit shown by the box line is the negative capacitor. This forward amplifier is fed back by the capacitor, and its gain is
[0044]
[0045] In the formula, C p,cal For connection at common-mode level V CM and the op amp’s negative input capacitor, C 1 is the feedback capacitor connected between the negative input and output of the op amp. p,cal It is implemented by a 9-bit adjustable capacitor array (CDAC), and the specific capacitor type is MIM capacitor. The final equivalent negative capacitance value is
[0046]
[0047] In the formula, C c is the size of the positive feedback capacitor, such as Figure 6 As shown, it is connected between the output of the forward amplifier and the input of the transimpedance amplifier. From the expression of the equivalent negative capacitance, it can be seen that when the above capacitance value is equal to the parasitic capacitance, the parasitic capacitance can be calibrated, thereby improving the overall detection accuracy.
[0048] Next, the principle of automatic calibration is explained. In the calibration mode, the circuit diagram is as follows Figure 7 In the circuit, the negative capacitor is connected to the input end of the circuit and the parasitic capacitor C p And the resistor R provides DC bias dc In this circuit, consider that there is random noise v n , the signal at the output of the op amp in the negative capacitor is v p,cal , v n to vp,cal The transfer function is as follows:
[0049]
[0050] From this transfer function, it can be analyzed that the circuit has a pole with the following frequency:
[0051]
[0052] It can be clearly seen from the pole expression that the pole frequency is related to the compensation state. When the negative capacitance does not fully compensate the parasitic capacitance of the circuit input node, the pole is located in the left half plane of the complex plane, and the circuit is stable. When the negative capacitance is overcompensated (that is, the compensation value is greater than the parasitic capacitance value in the actual circuit), this pole will move to the right half plane of the complex plane, and the circuit will oscillate. By detecting whether the circuit is stable, the current compensation state can be determined, and it can be determined whether the compensation capacitance needs to be further increased.
[0053] The specific compensation circuit formed based on this idea is as follows Figure 8 The oscillation detector is connected to the output of the forward amplifier, and the output digital code is directly used as the control word of CDAC to determine C p,cal In terms of circuit structure, the oscillation detector is generated by two comparators and an OR gate. This circuit can detect whether there is oscillation in the circuit. After the oscillation is detected, the subsequent logic will generate the corresponding control word and adjust the CDAC through the successive approximation register (SAR) logic. Fig. 9 Shows the voltage V during parasitic capacitance calibration p,cal And the capacitor C p,cal As shown in the figure, when calibrating the parasitic capacitance, the output terminal v of the op amp in the negative capacitance p,cal will oscillate during overcompensation, and the capacitance of CDAC will decrease; when v p,cal When the capacitance of CDAC increases, the circuit is stable. After 9 clock cycles, the circuit completes the adjustment of CDAC, and the overall capacitance of CDAC is c p,cal will converge to the parasitic capacitance c p Based on the above working process, it can be concluded that this technology not only realizes the automatic calibration of parasitic capacitance, but also greatly improves the calibration accuracy.
[0054] The practical effect of the present invention has been verified by chip tape-out. Fig.10 This is the equivalent capacitance noise test result of the chip, which shows that the capacitance sensing detection front end implemented with negative capacitance achieves capacitance detection accuracy of zF (10^-21) level.
[0055] The negative capacitance automatic calibration technology proposed in this invention has multiple advantages. The scheme has been successfully verified in a sensor readout circuit, showing excellent performance and strong versatility. The electron microscope photo of the chip is shown in FIG. Fig.11 shown.
Claims
1. A capacitance sensor readout circuit based on negative capacitance parasitic capacitance calibration, characterized in that: It includes a negative capacitor, a transimpedance amplifier TIA and a DC servo loop DSL; wherein the negative capacitor circuit is connected to the input end of the transimpedance amplifier and the parasitic capacitor C p And the resistor R provides DC bias dc The DC servo loop DSL is connected to both ends of the transimpedance amplifier feedback capacitor, and its function is to provide a DC bias for the transimpedance amplifier in the form of capacitive coupling; wherein: the negative capacitor is composed of a forward amplifier and a positive feedback capacitor; the forward amplifier is fed back by a capacitor, and its gain is In the formula, C p,cal For connection at common-mode level V CM and the capacitor at the negative input of the op amp, C1 is the feedback capacitor connected between the negative input and output of the op amp; p,cal It is implemented by an adjustable capacitor array CDAC, and the final equivalent negative capacitance is In the formula, C c is the size of the positive feedback capacitor, which is connected between the output of the forward amplifier and the input of the transimpedance amplifier. From the expression of the equivalent negative capacitance, it can be seen that when the equivalent capacitance value C eq and parasitic capacitance C p When they are equal, the parasitic capacitance is calibrated; The capacitance sensor readout circuit has two operating modes: calibration mode and sensing mode; In calibration mode, the external excitation and the transimpedance amplifier TIA are disconnected from the negative capacitor, and the resistor R dc Connect to V CM , used to provide DC bias for this circuit; the negative capacitor is directly connected to the input of the circuit to affect its parasitic capacitance C p Perform calibration; In the sensing mode, the negative capacitor is connected to the transimpedance amplifier TIA for capacitive signal sensing; C s By the external excitation signal V AC Driven by the transistor, a signal current is generated, which is converted into a signal voltage by the transimpedance amplifier TIA; the transimpedance amplifier TIA is connected to the demodulator module demodulator to generate the final output signal.
2. The capacitance sensor readout circuit according to claim 1, characterized in that: The adjustable capacitor array CDAC is a MIM capacitor.
3. The capacitance sensor readout circuit according to claim 1, characterized in that: The negative capacitor uses a multi-stage positive feedback amplifier.
4. A parasitic capacitance calibration method based on the capacitance sensor readout circuit according to claim 1, characterized in that: During the calibration process, the circuit stability is judged by the change of the pole frequency, and the negative capacitance value is adjusted until it is compensated to the ideal state; the automatic calibration of the negative capacitance is achieved through oscillation detection and successive approximation register SAR logic; the oscillation detection circuit judges the compensation state of the negative capacitance, and adjusts the compensation value through feedback, and the successive approximation SAR logic adjusts the adjustable capacitor array CDAC.
5. The parasitic capacitance calibration method according to claim 4, characterized in that: The oscillation detection circuit is generated by two comparators and an OR gate; the positive input of one comparator is connected to the input signal, and the negative input is connected to the reference voltage V CM -V TH , V TH is a reconstructible voltage value; the negative input terminal of the other comparator is connected to the input signal, and the positive input terminal is connected to another reference voltage V CM +V TH , V TH is a reconfigurable voltage value; the outputs of the two comparators are operated through an OR gate to obtain the final detection result; The oscillation detection circuit is used to detect whether the input signal is within V CM -V TH With V CM +V TH A jump occurs between the detection circuits, that is, whether oscillation occurs.
6. The parasitic capacitance calibration method according to claim 4, characterized in that: The output terminal of the op amp in the negative capacitor v p,cal will oscillate during overcompensation, and the capacitance of CDAC will decrease; when v p,cal When the capacitance of CDAC increases, the circuit is stable. After several clock cycles, the circuit completes the adjustment of CDAC, and the overall capacitance of CDAC is c p,cal Converges to the parasitic capacitance c p nearby.