Static capacitance automatic calibration system and method based on SAR (Synthetic Aperture Radar) logic

Abstract

The invention discloses a static capacitance automatic calibration system and method based on SAR (Synthetic Aperture Radar) logic. The system comprises a static capacitance detection module which collects signals output by a sensor in real time and obtains an I channel output amplitude through demodulation for reflecting the influence of static capacitance on the output signals; the capacitor digital-to-analog converter CDAC is characterized in that a logic circuit adjusts a combined value of the capacitor array to generate equivalent negative capacitance for compensating static baseline capacitance; and the calibration logic control module is used for logically controlling the on-off state of the CDAC through a successive approximation register (SAR), adjusting a compensation value in real time according to an I channel amplitude signal until an output signal is stabilized in a set threshold range, and ensuring that a baseline capacitor is completely compensated. According to the invention, an automatic static capacitance calibration technology based on CDAC is combined with successive approximation register (SAR) logic, so that the signal quality and the dynamic range of the capacitive sensor reading circuit can be obviously improved, and automatic high-precision calibration is realized.

Description

Technical Field

[0001] The invention belongs to the technical field of capacitance sensors, and in particular, relates to a static capacitance automatic calibration system and method based on SAR logic. Background Art

[0002] With the continuous advancement of sensing technology, capacitive sensors have been widely used in humidity detection, particle detection, proximity sensing, material analysis, and liquid level monitoring due to their advantages such as high sensitivity, low power consumption, and non-contact detection. These applications have put forward higher requirements for high-precision capacitive sensing interfaces, such as being able to achieve zF-level resolution in a high noise environment. However, this high-precision requirement poses many design challenges to the capacitive sensor readout circuit.

[0003] In a capacitive sensor, static capacitance is a fixed capacitance determined by the geometry and material properties of the sensor body, and its value is usually much larger than the dynamic capacitance signal detected by the sensor. A typical capacitive sensor may have a baseline capacitance of several pico-farads (pF) or even higher, while the change in dynamic capacitance is only a few femto-farads (fF). This problem can be solved by Figure 1 The circuit architecture shown is explained. Figure 1 A lock-in amplifier circuit for capacitive sensor readout is shown. The capacitive sensor is excited by external voltage v ac The signal current generated by the drive is converted into a signal voltage through a transimpedance amplifier with capacitor feedback. The DC path of the transimpedance amplifier is provided by a DC servo loop. The output voltage of the transimpedance amplifier is processed by a dual-channel demodulation circuit and generates I and Q channel outputs, where the I channel corresponds to the capacitance information. In this architecture, the model of the capacitive sensor consists of two parts, one of which is the static capacitance C base The other part is the dynamic capacitance C that represents the effective information. d Designers are only interested in dynamic capacitance because it represents the change in the actual physical quantity sensed by the sensor.

[0004] The signal-to-noise ratio of this circuit can be expressed as follows:

[0005]

[0006] In the formula, is the equivalent input noise voltage of the main op amp, and ENBW is the equivalent noise bandwidth of the circuit. From the SNR expression, it can be seen that a large static capacitance limits the amplitude of the excitation signal that can be applied to the sensor, resulting in a significant decrease in signal power and SNR.

[0007] Traditional compensation methods for static capacitance are often based on traditional manual calibration methods. This method is not only time-consuming and labor-intensive, but also requires repeated calibration when the application scenario changes, making it difficult to adapt to the real-time and high-efficiency requirements of modern industry. At the same time, the accuracy of manual calibration is also limited by the skill level of the operator, and consistency cannot be guaranteed.

[0008] In view of the above problems, there is an urgent need for a solution that can automatically, efficiently and accurately calibrate static capacitance to adapt to changing application scenarios and improve the performance of the sensor under the premise of low power consumption and low cost. Summary of the invention

[0009] The present invention proposes a static capacitance automatic calibration system and method based on SAR logic. The automatic static capacitance calibration technology based on CDAC is combined with successive approximation register (SAR) logic to achieve accurate compensation of baseline capacitance. The present invention can significantly improve the signal quality and dynamic range of the capacitance sensor readout circuit and achieve automatic high-precision calibration.

[0010] The technical solution of the present invention is specifically described as follows.

[0011] The present invention provides a static capacitance automatic calibration system based on SAR logic, comprising:

[0012] Static capacitance detection module: collects the signal output by the sensor in real time, and obtains the I channel output amplitude through demodulation to reflect the influence of static capacitance on the output signal;

[0013] Calibration logic control module: The switching state of the capacitance digital-to-analog converter CDAC is controlled by the successive approximation register SAR logic, and the capacitance array combination value of the capacitance digital-to-analog converter CDAC is adjusted in real time according to the I channel amplitude signal to generate an equivalent negative capacitance to compensate the static baseline capacitance until the output signal is stable within the set threshold range, ensuring that the baseline capacitance is fully compensated.

[0014] In the present invention, the static capacitance detection module includes a sensor, a transimpedance amplifier TIA and a demodulation module; the sensor is used to sense capacitance changes and generate corresponding electrical signals; the TIA converts the current signal output by the sensor into a voltage signal and amplifies it; the demodulation module demodulates the signal output by the TIA to extract useful signal information; the three are closely connected through signal transmission to ensure that capacitance changes can be accurately detected and processed; in the work process, the sensor generates a signal, the TIA amplifies and converts it, and the demodulation module extracts and analyzes the signal.

[0015] In the present invention, the calibration logic control module is composed of a comparator, a D flip-flop and a SAR logic; the comparator is used to compare an input signal with a reference signal, generate a comparison result, and transmit the signal to the D flip-flop; the D flip-flop receives the output of the comparator, stores a control state and synchronizes the signal; the SAR logic gradually adjusts the output according to the control signal of the D flip-flop through a successive approximation algorithm, and finally completes the precise calibration; the three work closely together through signal transmission, the comparator provides comparison information, the D flip-flop stores synchronously, and the SAR logic performs calibration adjustment to achieve precise control of the system.

[0016] In the present invention, the design of the capacitor digital-to-analog converter CDAC adopts a hand-drawn capacitor structure, refers to the interdigital MOM structure, and uses the fourth layer of metal in the layout for implementation; in addition, the first layer of metal is used as a shielding layer to effectively reduce parasitic effects, thereby improving the accuracy of capacitance realization.

[0017] In the present invention, the capacitance digital-to-analog converter CDAC is a metal oxide metal MOM capacitor array; the unit capacitance is only a small capacitance of 5fF.

[0018] The present invention also provides a static capacitance automatic calibration method based on SAR logic, which is implemented based on the above-mentioned static capacitance automatic calibration system, and the specific steps are as follows:

[0019] The system applies an excitation signal of a certain amplitude to the sensor, and the capacitance signal generated by the sensor is conditioned by the transimpedance amplifier TIA and the demodulation module and then sent to the calibration logic control module;

[0020] The calibration logic control module monitors the output changes of the I channel and drives the control word of the capacitance digital-to-analog converter CDAC to be gradually adjusted according to the SAR algorithm, gradually approaching the optimal compensation value to complete the static capacitance calibration.

[0021] As mentioned above, the calibration control method based on SAR logic of the present invention ensures fast and accurate baseline capacitance compensation; the design of high-resolution capacitance digital-to-analog converter CDAC and its application in dynamic signal calibration improve the amplitude of the excitation signal that the circuit can withstand and improve the signal-to-noise ratio of the overall readout circuit; the calibration logic module realizes automatic detection of I channel output. The present invention can significantly improve the performance of capacitance sensors and provide reliable and efficient solutions for multi-scenario applications; compared with the prior art, the present invention has the following beneficial effects:

[0022] ① High precision: Accurate compensation of baseline capacitance is achieved through the 5fF resolution of the capacitance digital-to-analog converter CDAC, which is particularly suitable for scenarios with extremely small dynamic capacitance signals.

[0023] ②Fast convergence: SAR logic control ensures that the calibration process is completed within a limited number of steps, greatly reducing the calibration time.

[0024] ③ Dynamic adaptability: The calibration module can adapt to the sensor characteristics in different scenarios without manual intervention, truly realizing fully automatic calibration. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A lock-in amplifier for a capacitive sensor readout circuit.

[0026] Figure 2 It is a lock-in amplifier with automatic calibration based on static capacitance.

[0027] Figure 3 This is the specific circuit diagram of the static capacitance automatic calibration module.

[0028] Figure 4 This is the static capacitance calibration process obtained from actual testing.

[0029] Figure 5 This is a test chart of capacitance detection accuracy. DETAILED DESCRIPTION

[0030] The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings and embodiments.

[0031] Aiming at the influence of static capacitance on dynamic signal acquisition in a capacitance sensor readout circuit, the present invention proposes an automatic calibration technology based on CDAC, which includes:

[0032] (1) Automated calibration method based on successive approximation logic (SAR)

[0033] Traditional static capacitance compensation usually relies on manual adjustment or fixed circuit design, which is difficult to adapt to complex scenarios. The present invention adopts successive approximation register (SAR) logic to achieve efficient and accurate automatic calibration by optimizing the calibration control word. This method has the following characteristics:

[0034] Dynamic adjustment: According to the amplitude change of the sensor output signal, the compensation value of the capacitance digital-to-analog converter CDAC is dynamically adjusted to ensure that the compensation effect of the baseline capacitance is always optimal.

[0035] Fast convergence: SAR logic significantly reduces calibration time by gradually approaching the optimal solution for compensation values ​​and can adapt to application scenarios with different baseline capacitance ranges.

[0036] (2) Design of Capacitor Digital-to-Analog Converter (CDAC)

[0037] The present invention designs a high-precision CDAC based on a MOM capacitor array for generating an equivalent negative capacitance to compensate for the baseline capacitance. The core protection points of the CDAC design include:

[0038] High-resolution feature: Fully customized MOM implementation, the minimum resolution of CDAC reaches 5fF, which can achieve accurate compensation of static capacitance.

[0039] High linearity and wide dynamic range: The use of MOM capacitors ensures linearity, while the overall CDAC supports a baseline capacitance compensation range of up to several pico-farads, suitable for a variety of complex sensor interface applications.

[0040] (3) Improvement of dynamic signal readout performance

[0041] The core goal of static capacitance calibration technology is to improve the readout performance of dynamic signals. The present invention achieves significant optimization of dynamic performance by the following means:

[0042] Improve signal excitation amplitude: The calibrated readout circuit allows the application of excitation signals up to 20Vpk, significantly improving the sensor's signal power and signal-to-noise ratio (SNR). After baseline capacitance compensation, the amplitude limitation of the dynamic signal is released, avoiding the saturation problem of the amplifier under large signal excitation, thereby ensuring the integrity and accuracy of the signal readout.

[0043] (5) Full automation and wide applicability

[0044] The calibration technology of the present invention does not require manual intervention and is truly fully automated. This feature not only improves the calibration efficiency, but also enhances the versatility of the system, and can be adapted to different types and sizes of capacitive sensors, including:

[0045] Low-frequency and high-sensitivity applications: such as environmental monitoring and acquisition of tiny signals in medical testing;

[0046] High dynamic range requirements: such as high-precision liquid level detection in industrial automation;

[0047] Noise-sensitive environments: such as communication equipment and consumer electronics with significant electromagnetic interference.

[0048] The following are specific embodiments.

[0049] 1. Architecture design of static capacitance calibration module

[0050] like Figure 2 As shown, the static capacitance calibration module of the present invention is composed of the following main functional units:

[0051] Static capacitance detection module: collects the signal output by the sensor in real time, and obtains the I channel output amplitude through demodulation to reflect the influence of static capacitance on the output signal.

[0052] Capacitor array (CDAC): Logic circuits adjust the combined value of the metal oxide metal (MOM) capacitor array to generate an equivalent negative capacitance to compensate for the static baseline capacitance. The minimum resolution of CDAC is 5fF, which can accurately compensate for the static capacitance value in a variety of scenarios.

[0053] Calibration logic control module:

[0054] Figure 3 The specific composition of the logic control circuit is shown. The module consists of a comparator and a D-type flip-flop SAR logic. In the workflow, the comparator first compares the input signal with the set reference signal, outputs the comparison result, and passes it to the D-type flip-flop. The D-type flip-flop receives the comparison result and stores the state synchronously to ensure the stability of the signal timing. Subsequently, the SAR logic controls the successive approximation process according to the output of the D-type flip-flop, and adjusts the compensation voltage or current by controlling the switch state of the CDAC (capacitance digital-to-analog converter) to achieve accurate capacitance compensation. The SAR logic continuously adjusts the compensation value, monitors the I channel amplitude signal in real time, and gradually makes the output signal tend to be within the set threshold range until the system reaches a stable state. This process ensures the complete compensation of the baseline capacitance, improves the accuracy and stability of the system, and thus achieves high-precision signal measurement and processing. Through this closed-loop adjustment mechanism, the logic control module can effectively respond to changes in the environment or component parameters and maintain the consistency of system performance.

[0055] 2. Working Process

[0056] The working process of the overall circuit is divided into two stages: static capacitance and stable output:

[0057] Static capacitance calibration: The system applies a sinusoidal excitation signal of a certain amplitude to the sensor. The capacitance signal generated by the sensor is sent to the calibration module after conditioning by the transimpedance amplifier (TIA) and the demodulation module. The baseline capacitance detection module determines the compensation value according to the output amplitude. The calibration logic module monitors the output changes of the I channel, and the control word driving the capacitance digital-to-analog converter CDAC is gradually adjusted according to the SAR algorithm, gradually approaching the optimal compensation value. The high-resolution design of the capacitance digital-to-analog converter CDAC ensures the accuracy of the compensation value. In the design of the capacitance digital-to-analog converter CDAC, a precisely designed hand-drawn capacitor structure is adopted, and the goal is to achieve a small capacitance of only 5fF for each capacitance unit. These hand-drawn capacitors use an interdigitated MOM structure, and the capacitance unit is realized through the fourth layer of metal in the layout. In order to further improve the accuracy of the capacitance value, the first layer of metal in the layout is also used as a shielding layer in the design, which effectively reduces the influence of parasitic capacitance, thereby ensuring the high accuracy of the capacitance value. Through this high-precision capacitance digital-to-analog converter CDAC design, the system can achieve a smaller range of capacitance adjustment during the static capacitance calibration process, thereby ensuring the stability and accuracy of the signal. The calibration module and the capacitance digital-to-analog converter CDAC work together to ensure that the output signal of the sensor can accurately match the target value, effectively eliminate the error of the baseline capacitance, and improve the performance and reliability of the overall system.

[0058] Stable output: After nine clock cycles, the calibration is complete. At this time, the equivalent baseline capacitance of the system has been fully compensated, the output signal amplitude is stable, and the readout circuit can reliably obtain the dynamic capacitance signal.

[0059] Figure 4 The static capacitance calibration process obtained from the actual test. During the test, a sine wave signal of a certain amplitude is applied to the input end of the capacitance sensor. The capacitance sensor generates a capacitance change according to the input excitation signal. The output signal is amplified by a transimpedance amplifier (TIA) and sent to the demodulation module. The demodulation module processes the signal, extracts the effective signal and compares it with the reference signal. During the test, the CDAC control word changes in Figure 4 Given in.

[0060] Figure 5 This is a test diagram of capacitance detection accuracy. The circuit based on static capacitance compensation can achieve capacitance detection at the zF level.

[0061] The present invention adopts an innovative automatic calibration method and a high-precision capacitance adjustment element, so that the calibration process has the following characteristics: (1) Automatic calibration: no manual intervention is required, suitable for a variety of dynamic environments, and can effectively improve user experience and calibration efficiency. (2) High precision: Through the CDAC with an LSB of 5fF, accurate compensation of the baseline capacitance can be achieved, so that the excitation voltage can reach 20Vpk, thereby significantly improving the signal power and SNR. Figure 5The actual test results of a chip using this technology are shown, and the test results show that this readout circuit achieves zF-level accuracy. (3) Wide applicability: This solution is applicable to a variety of low-frequency and high-sensitivity capacitive sensor interface designs, taking into account both high resolution and high dynamic range.

[0062] Through the static capacitance calibration module of the present invention, the readout circuit can apply a higher amplitude excitation signal (up to 20Vpk), thereby significantly improving the signal-to-noise ratio and dynamic range of the sensor. In addition, the calibration process is insensitive to external environment and noise interference, and can be widely used in a variety of high-precision capacitance sensor interface designs, including liquid level detection, environmental monitoring, and medical equipment.

Claims

1. A static capacitance automatic calibration system based on SAR logic, characterized in that: include: Static capacitance detection module: collects the signal output by the sensor in real time, and obtains the I channel output amplitude through demodulation to reflect the influence of static capacitance on the output signal; Calibration logic control module: The switching state of the capacitance digital-to-analog converter CDAC is controlled by the successive approximation register SAR logic, and the capacitance array combination value of the capacitance digital-to-analog converter CDAC is adjusted in real time according to the I channel amplitude signal to generate an equivalent negative capacitance to compensate the static baseline capacitance until the output signal is stable within the set threshold range, ensuring that the baseline capacitance is fully compensated.

2. The static capacitance automatic calibration system according to claim 1, characterized in that: The static capacitance detection module includes a sensor, a transimpedance amplifier (TIA) and a demodulation module; the sensor is used to sense capacitance changes and generate corresponding electrical signals; the TIA converts the current signal output by the sensor into a voltage signal and amplifies it; the demodulation module demodulates the signal output by the TIA to extract useful signal information.

3. The static capacitance automatic calibration system according to claim 1, characterized in that: The calibration logic control module is composed of a comparator, a D flip-flop, and a SAR logic. The comparator is used to compare the input signal with the reference signal, generate a comparison result, and pass the signal to the D flip-flop; the D flip-flop receives the output of the comparator, stores the control state, and synchronizes the signal; the SAR logic uses a successive approximation algorithm to gradually adjust the output according to the control signal of the D flip-flop, and finally completes the precise calibration.

4. The static capacitance automatic calibration system according to claim 1, characterized in that: A hand-drawn capacitor structure is adopted in the design of the capacitor digital-to-analog converter CDAC. The hand-drawn capacitor refers to the interpolated MOM structure and is implemented using the fourth metal layer in the layout. In addition, the first metal layer in the layout is used as a shielding layer to effectively reduce parasitic effects, thereby improving the accuracy of capacitance realization.

5. The static capacitance automatic calibration system according to claim 1, characterized in that: The capacitance digital-to-analog converter CDAC uses a metal oxide metal MOM capacitor array; the unit capacitance is only a small capacitance of 5fF.

6. A static capacitance automatic calibration method based on SAR logic, which is implemented based on the static capacitance automatic calibration system according to claim 1, characterized in that: The following steps are involved: The system applies an excitation signal of a certain amplitude to the sensor, and the capacitance signal generated by the sensor is conditioned by the transimpedance amplifier TIA and the demodulation module and then sent to the calibration logic control module; The calibration logic control module monitors the output changes of the I channel and drives the control word of the capacitance digital-to-analog converter CDAC to be gradually adjusted according to the SAR algorithm, gradually approaching the optimal compensation value to achieve static capacitance calibration.

Images