Segmented broken line nonlinear calibration device of analog-to-digital converter, driving chip and electronic equipment

Abstract

The invention relates to a segmented broken line nonlinear calibration device of an analog-to-digital converter, a driving chip and electronic equipment, and the device comprises a first adjustment unit which is used for selecting a target slope from a slope storage unit according to the high n bits of an analog-to-digital conversion result, and adjusting the low-bit quantized value corresponding to the N-n bits of the analog-to-digital conversion result by using the target slope, the output range of the analog-to-digital converter is divided into a plurality of continuous interval sections, and each interval section corresponds to one slope; and the second adjusting unit is used for adjusting the high-order quantized value corresponding to the high n bits of the analog-to-digital conversion result according to the slopes of a plurality of interval sections before the interval section corresponding to the target slope so as to obtain the adjusted high-order quantized value, and obtaining the calibrated analog-to-digital conversion result by utilizing the sum of the adjusted high-order quantized value and the adjusted low-order quantized value. According to the embodiment of the invention, the calculation complexity can be greatly reduced, the area overhead is saved, the energy efficiency is improved, and the analog-to-digital conversion efficiency is relatively high.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a piecewise zigzag nonlinear calibration device, a driving chip and an electronic device for an analog-to-digital converter. Background Art

[0002] The analog-to-digital converter is a typical analog and mixed-signal integrated circuit that converts analog signals into digital signals after quantization. It is a bridge between the real world and digital systems. With the advancement of integrated circuit technology, the size of transistors continues to shrink and the power supply voltage gradually decreases. The lower transistor output impedance and more limited voltage swing bring severe nonlinear challenges to the design of analog-to-digital converters.

[0003] During the signal conversion process, non-ideal characteristics in the circuit will introduce nonlinearity, thereby reducing the performance of the analog-to-digital converter.

[0004] At the same time, the advancement of technology has also brought about digital computing capabilities with lower area and higher energy efficiency. Therefore, it has become a very important method to calibrate the nonlinearity introduced by analog circuits in the digital domain. It can use the advantages of digital computing under advanced technology to deal with the irrational characteristics of analog circuits and has broad application prospects.

[0005] The polynomial-based nonlinear calibration algorithm is a commonly used method. The nonlinear effects in the circuit can be modeled through the polynomial function, and the nonlinear error can be extracted and corrected on this basis. The polynomial function can accurately describe the nonlinear characteristics of the actual circuit, and only requires fewer parameters to achieve error extraction. It is the current mainstream nonlinear calibration algorithm. There are many relatively mature background error extraction solutions on the market that can achieve error extraction at a low cost. However, polynomial calculations require power operations on the signal, which introduces large delays, power consumption and area overhead. This poses a great challenge to the practical application of the algorithm.

[0006] Another solution is to model and extract nonlinear errors by means of segmented polyline. By using linear functions to approximate nonlinear functions, nonlinear calibration can be achieved only through linear multiplication and addition operations, thereby avoiding complex power operations and greatly reducing the overall complexity of the system. However, compared with the polynomial-based nonlinear calibration algorithm, the segmented polyline-based calibration method requires a larger number of parameters and is more difficult to extract. For a cubic polynomial y=a1x+a3x 3 For example, only two parameters, a1 and a3, are needed to achieve accurate error extraction. Assuming that the model is built through 4 segmented polylines, each segment of the polyline needs a slope k i and intercept b iTwo parameters are needed to determine the calibration accuracy, so a total of 8 parameters are needed. If higher calibration accuracy is required, more parameters are needed. How to extract these parameters is a very challenging problem.

[0007] Figure 1a , Figure 1b The existing scheme for extracting the segmented broken line coefficient is presented. This scheme extracts the segmented broken line parameters through the foreground test method. The basic idea is to generate a preset test voltage through a digital-to-analog converter and input it into the analog-to-digital converter, and determine its nonlinear characteristics based on the output result of the analog-to-digital converter, thereby realizing the extraction of the segmented broken line coefficient. This scheme requires a large hardware overhead (additional digital-to-analog converter) and can only realize foreground extraction, which requires interrupting the normal conversion of the analog-to-digital converter. These shortcomings greatly limit its scope of use.

[0008] It can be seen that the traditional polynomial nonlinear error calibration algorithm has high computational complexity and will introduce a lot of speed and area costs. In addition, the existing nonlinear calibration method based on piecewise broken lines has large hardware overhead and low calibration efficiency, and there are many limitations in practical applications. Summary of the invention

[0009] According to one aspect of the present disclosure, a piecewise zigzag nonlinear calibration device for an analog-to-digital converter is provided, wherein the analog-to-digital converter is used to perform analog-to-digital conversion on an input analog input signal and output an analog-to-digital conversion result, wherein the device comprises:

[0010] A first adjustment unit is connected to the output end of the analog-to-digital converter, and is used to select a target slope from a slope storage unit according to the high n bits of the analog-to-digital conversion result, and use the target slope to adjust the low-bit quantization value corresponding to the Nn bits of the analog-to-digital conversion result to obtain an adjusted low-bit quantization value, wherein N>n and are all positive integers, N is the conversion accuracy of the analog-to-digital converter, and the output range of the analog-to-digital converter is divided into a plurality of continuous interval segments, each of which corresponds to a slope;

[0011] A second adjustment unit is connected to the output end of the analog-to-digital converter and the output end of the first adjustment unit, and the second adjustment unit is used to: adjust the high-order quantization value corresponding to the high n bits of the analog-to-digital conversion result according to the slopes of multiple interval segments before the interval segment corresponding to the target slope to obtain the adjusted high-order quantization value, and use the sum of the adjusted high-order quantization value and the adjusted low-order quantization value to obtain the calibrated analog-to-digital conversion result.

[0012] In a possible implementation, the slope storage unit includes a plurality of slope registers, each slope register stores a corresponding slope, and the first adjustment unit includes a first multiplexer and a first multiplier, wherein:

[0013] The multiple input terminals of the first multiplexer are respectively connected to the slope registers of the slope storage unit, the control terminal of the first multiplexer is used to receive the upper n bits of the analog-to-digital conversion result, the output terminal of the first multiplexer is connected to the first input terminal of the first multiplier, and the output terminal of the first multiplexer is used to output the target slope.

[0014] The second input end of the first multiplier is used to receive the low-order quantization value corresponding to the Nn bits of the analog-to-digital conversion result, the first multiplier is used to implement the multiplication operation of the low-order quantization value corresponding to the Nn bits of the analog-to-digital conversion result and the target slope, and the output end of the first multiplier is used to output the adjusted low-order quantization value.

[0015] In a possible implementation manner, the second adjustment unit includes a second multiplexer, an accumulator, a second multiplier, and a first adder, wherein:

[0016] The second multiplexer is used to select the slopes of multiple intervals before the interval corresponding to the target slope from the slope storage unit according to the upper n bits of the analog-to-digital conversion result, and input them into the accumulator, and the accumulator is used to output the slope accumulation result;

[0017] The second multiplier is used to implement a multiplication operation of a high-order quantization value corresponding to high n bits of the analog-to-digital conversion result and the slope accumulation result to obtain the adjusted high-order quantization value;

[0018] The first adder is connected to the output end of the accumulator and the output end of the first adjustment unit, and is used to sum the adjusted high-order quantization value and the adjusted low-order quantization value to obtain a calibrated analog-to-digital conversion result.

[0019] In a possible implementation, the target slope is a ratio of an ideal slope of the analog-to-digital converter to an actual slope corresponding to an interval to which a quantized value corresponding to upper n bits of the analog-to-digital conversion result belongs.

[0020] In one possible implementation, 2 n is the total number of divided intervals,

[0021] In the initial case, the endpoints of each interval segment include the origin 0 and i×b0, b0=A / 2 n , 1≤i≤2 n And i is an integer, A=2 Nrepresents the maximum output value of the analog-to-digital converter,

[0022] After the device performs a calibration, the endpoints of each interval segment include 0 and b i ,

[0023] in, k i Represents the slope corresponding to the i-th interval, j is a positive integer.

[0024] In a possible implementation manner, the device further includes a parameter updating module, configured to update the slope in the slope register and endpoints of each interval segment using the calibrated analog-to-digital conversion result.

[0025] In a possible implementation, the parameter updating module includes an endpoint updating unit and a plurality of slope updating units, wherein the slope updating unit is used to perform a slope updating operation, and the endpoint updating unit is used to perform an endpoint updating operation according to the updated slope.

[0026] Each slope updating unit includes an absolute value judger, a third multiplier and a minimum mean square filter. For any slope updating unit:

[0027] The absolute value judger is used to judge the size of the absolute value of the input sample and the value of the corresponding endpoint, and output the judgment result to the third multiplier, wherein the input sample is the difference between the calibrated analog-to-digital conversion result and the digital code of the random signal added to the analog input signal, and the input sample is used as the final analog-to-digital conversion result, wherein when the absolute value of the input sample is greater than the value of the corresponding endpoint, the judgment result is 1; when the absolute value of the input sample is less than or equal to the value of the corresponding endpoint, the judgment result is 0.

[0028] The third multiplier is used to perform a multiplication operation of the judgment result and the sample, and input the operation result into the minimum mean square filter.

[0029] The least mean square filter is used to receive the preset update parameter and the operation result, and output the updated slope,

[0030] Wherein, the preset update parameter is related to the digital code.

[0031] In a possible implementation manner, the minimum mean square filter includes a fourth multiplier, a second adder, and a delay device, wherein:

[0032] The fourth multiplier is used to receive the operation result output by the third multiplier and the preset update parameter, the output end of the fourth multiplier is connected to the first input end of the second adder, and the output end of the fourth multiplier is used to output the product of the operation result output by the third multiplier and the preset update parameter,

[0033] The second input terminal of the second adder is connected to the output terminal of the delay device.

[0034] The input end of the delayer is connected to the output end of the second adder as the output end of the minimum mean square filter.

[0035] The preset update parameter is μ·sign(D d ), μ represents the preset value, sign() represents the sign function, D d Represents the digital code.

[0036] According to one aspect of the present disclosure, a driver chip is provided, the driver chip comprising the piecewise broken line nonlinear calibration device of the analog-to-digital converter.

[0037] According to one aspect of the present disclosure, an electronic device is provided, and the electronic device includes the driving chip.

[0038] The disclosed embodiment sets a first adjustment unit to select a target slope from a slope storage unit according to the high n bits of the analog-to-digital conversion result, and uses the target slope to adjust the low-order quantization value corresponding to the Nn bits of the analog-to-digital conversion result to obtain the adjusted low-order quantization value, sets a second adjustment unit to adjust the high-order quantization value corresponding to the high n bits of the analog-to-digital conversion result according to the slopes of multiple interval segments before the interval segment corresponding to the target slope to obtain the adjusted high-order quantization value, and uses the sum of the adjusted high-order quantization value and the adjusted low-order quantization value to obtain the calibrated analog-to-digital conversion result. Compared with traditional polynomial calibration, the disclosed embodiment can greatly reduce computational complexity, save area overhead, and improve energy efficiency. Compared with the existing segmented calibration method, the disclosed embodiment does not need to set an additional digital-to-analog converter, can reduce hardware overhead, reduce cost, and does not need to interrupt the conversion process during the conversion process, and has a higher analog-to-digital conversion efficiency.

[0039] It should be understood that the above general description and the following detailed description are exemplary and explanatory only and do not limit the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.

[0041] Figure 1a FIG. 4 shows a schematic diagram of an error curve of an existing segmented calibration. Figure 1b A block diagram of existing segmented calibration is shown.

[0042] Figure 2 A schematic diagram of a piecewise broken line nonlinear calibration device for an analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0043] Figure 3a A schematic diagram of a piecewise broken line nonlinear calibration device for an analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0044] Figure 3b shows a schematic diagram of the initial segmentation. Figure 3c A schematic diagram of the segmentation after calibration is shown.

[0045] Figure 4 A schematic diagram of a piecewise broken line nonlinear calibration device for an analog-to-digital converter according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0046] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0047] In the description of the present disclosure, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0048] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0049] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0050] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0051] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

[0052] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0053] See also Figure 2 , Figure 2 A schematic diagram of a piecewise broken line nonlinear calibration device for an analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0054] The analog-to-digital converter 10 is used to perform analog-to-digital conversion on the input analog input signal (Vi) and output the analog-to-digital conversion result, wherein Figure 2 As shown, the device comprises:

[0055] A first adjustment unit 20 is connected to the output end of the analog-to-digital converter 10, and is used to: select a target slope from the slope storage unit 40 according to the high n bits of the analog-to-digital conversion result, and use the target slope to adjust the low-bit quantization value corresponding to the Nn bits of the analog-to-digital conversion result to obtain an adjusted low-bit quantization value, wherein N>n and are positive integers, N is the conversion accuracy of the analog-to-digital converter 10, and the output range of the analog-to-digital converter 10 is divided into a plurality of continuous interval segments, each of which corresponds to a slope;

[0056] The second adjustment unit 30 is connected to the output end of the analog-to-digital converter 10 and the output end of the first adjustment unit 20. The second adjustment unit 30 is used to: adjust the high-order quantization value corresponding to the high n bits of the analog-to-digital conversion result according to the slopes of multiple interval segments before the interval segment corresponding to the target slope to obtain the adjusted high-order quantization value, and use the sum of the adjusted high-order quantization value and the adjusted low-order quantization value to obtain the calibrated analog-to-digital conversion result (Dout).

[0057] The embodiment of the present disclosure sets a first adjustment unit 20 to select a target slope from a slope storage unit 40 according to the high n bits of the analog-to-digital conversion result, and uses the target slope to adjust the low-order quantization value corresponding to the Nn bits of the analog-to-digital conversion result to obtain an adjusted low-order quantization value, sets a second adjustment unit 30 to adjust the high-order quantization value corresponding to the high n bits of the analog-to-digital conversion result according to the slopes of multiple intervals before the interval corresponding to the target slope to obtain an adjusted high-order quantization value, and uses the sum of the adjusted high-order quantization value and the adjusted low-order quantization value to obtain a calibrated analog-to-digital conversion result. Compared with traditional polynomial calibration, the present disclosure can greatly reduce computational complexity, save area overhead, and improve energy efficiency. Compared with the existing segmented calibration method, the embodiment of the present disclosure does not need to set up an additional digital-to-analog converter, can reduce hardware overhead, reduce cost, and does not need to interrupt the conversion process during the conversion process, and has a higher analog-to-digital conversion efficiency.

[0058] The embodiments of the present disclosure do not limit the specific implementation of the first adjustment unit 20 and the second adjustment unit 30. Those skilled in the art may adopt appropriate technical solutions according to actual conditions and needs, as long as the corresponding functions can be achieved.

[0059] In a possible implementation, the slope storage unit 40 may include a plurality of slope registers, each of which stores a corresponding slope. The disclosed embodiment does not limit the number and type of slope registers, and those skilled in the art may set them according to actual conditions and needs. For example, corresponding slope registers may be set according to the number of segments, and the number of slope registers may be greater than or equal to the specific number of segments. In a possible implementation, 2 n is the total number of divided interval segments, then the number of slope registers can be greater than or equal to 2 n, that is, each interval segment corresponds to a slope. For example, if n=2, it can be divided into 4 interval segments. The slope storage unit 40 can include at least 4 slope registers, which are respectively used to store the corresponding slopes of the 4 interval segments. For example, the interval segments can be arranged in order from small to large, and the slopes corresponding to the interval segments can be numbered in sequence. In this example, the slopes of the first interval segment to the fourth interval segment correspond to k1~k4 respectively.

[0060] The embodiment of the present disclosure does not limit the specific size of the slope of each interval segment, and those skilled in the art can set it according to actual conditions and needs. For example, multiple tests can be performed in advance to obtain the simulation curve of the input and output of the analog-to-digital converter 10, and the slope of each interval segment is set according to the number of segments and the simulation curve, and stored in the corresponding slope register. Of course, the embodiment of the present disclosure does not limit the specific implementation method of obtaining the initial slope, and those skilled in the art can refer to the relevant technology implementation according to actual conditions and needs.

[0061] The following is an exemplary introduction to possible implementations of the first adjustment unit 20 and the second adjustment unit 30.

[0062] See also Figure 3a , Figure 3a A schematic diagram of a piecewise broken line nonlinear calibration device for an analog-to-digital converter 10 according to an embodiment of the present disclosure is shown.

[0063] In a possible implementation, Figure 3a As shown, the first adjustment unit 20 may include a first multiplexer MUX1 and a first multiplier MUL1, wherein:

[0064] The multiple input terminals of the first multiplexer MUX1 are respectively connected to the slope registers of the slope storage unit 40, the control terminal of the first multiplexer is used to receive the upper n bits (MSB) of the analog-to-digital conversion result, the output terminal of the first multiplexer MUX1 is connected to the first input terminal of the first multiplier MUL1, and the output terminal of the first multiplexer MUX1 is used to output the target slope.

[0065] The second input end of the first multiplier MUL1 is used to receive the low-order quantization value (LSB) corresponding to the Nn-bit of the analog-to-digital conversion result, the first multiplier MUL1 is used to implement the multiplication operation of the low-order quantization value corresponding to the Nn-bit of the analog-to-digital conversion result and the target slope, and the output end of the first multiplier MUL1 is used to output the adjusted low-order quantization value (LSB cal ).

[0066] In a possible implementation, Figure 3aAs shown, the second adjustment unit 30 may include a second multiplexer MUX2, an accumulator AND0, a second multiplier MUL2 and a first adder AND1, wherein:

[0067] The second multiplexer MUX2 is used to select the slopes of multiple intervals before the interval corresponding to the target slope from the slope storage unit 40 according to the high n bits of the analog-to-digital conversion result, and input them into the accumulator AND0, and the accumulator AND0 is used to output the slope accumulation result;

[0068] The second multiplier MUL2 is used to implement a multiplication operation of the high-order quantization value corresponding to the high n bits of the analog-to-digital conversion result and the slope accumulation result to obtain the adjusted high-order quantization value;

[0069] The first adder AND1 is connected to the output end of the accumulator AND0 and the output end of the first adjustment unit 20, and is used to sum the adjusted high-order quantization value and the adjusted low-order quantization value to obtain a calibrated analog-to-digital conversion result.

[0070] Exemplarily, if the high n MSB bits of the analog-to-digital conversion result are located in the third interval segment, the target slope is k3, and the slopes of multiple interval segments before the target slope corresponds to the interval segment, including the slope k1 of the first interval segment and the slope k2 of the second interval segment. The accumulator AND0 outputs the slope accumulation result (k1+k2), and the adjusted high-order quantization value MSB_cal=(k1+k2)×MSB.

[0071] Of course, the above introduction to the first adjustment unit 20 and the second adjustment unit 30 is exemplary and should not be regarded as a limitation on the embodiments of the present disclosure. Those skilled in the art may implement it in other ways according to actual conditions and needs. For example, a mapping relationship between each interval segment and the slope may be established in advance, and a controller may be used to query the target interval segment where the high n bits of the analog-to-digital conversion result are located, and then the target slope may be obtained through the target interval segment and the mapping relationship established in advance.

[0072] In a possible implementation, the target slope is the ratio of the ideal slope of the analog-to-digital converter to the actual slope corresponding to the interval segment to which the quantized value corresponding to the upper n bits of the analog-to-digital conversion result belongs. In this way, the disclosed embodiment can ensure that the slope of each segment of the output result after multiplication is equal to the ideal slope, thereby achieving nonlinear calibration. The ideal slope of the analog-to-digital converter can be obtained by looking up the technical manual.

[0073] See also Figure 3b and Figure 3c , Figure 3b shows a schematic diagram of the initial segmentation. Figure 3c A schematic diagram of the segmentation after calibration is shown.

[0074] For simplicity, Figure 3b and Figure 3c Only the case where the input signal is greater than 0 is shown. For inputs less than 0, the same correction operation can be performed after taking the absolute value. Of course, the reference value "0" here can also be other values ​​of the minimum input of the ADC. For example, for a differential circuit, the reference value can be a negative value. In addition, the selection of the upper 2 bits (n=2) shown in the figure (corresponding to the 4-segment segmented broken line approximation) is also a special case. The number of segments can be increased or decreased according to the requirements of calibration accuracy.

[0075] In one possible implementation, as described above, 2 n is the total number of intervals to be divided. In this example, n=2, which means it can be divided into 4 intervals. Figure 3b As shown, in the initial case, the endpoints of each interval segment include the origin 0 and i×b0, b0=A / 2 n , 1≤i≤2 n And i is an integer, A=2 N It represents the maximum output value of the analog-to-digital converter 10, that is, the endpoints include 0, b0, 2b0, 3b0, and 4b0 (not shown), that is, it includes four intervals of 0-b0, b0-2b0, 2b0-3b0, and 3b0-4b0. The slopes corresponding to the four intervals of 0-b0, b0-2b0, 2b0-3b0, and 3b0-4b0 are k1, k2, k3, and k4 respectively.

[0076] Exemplarily, after the device performs a calibration, the endpoints of each interval segment include 0 and b i ,

[0077] in, k i Represents the slope corresponding to the i-th interval, j is a positive integer.

[0078] For example, analog input signals usually introduce nonlinearity due to non-ideal characteristics in the circuit, for example Figure 3a As shown, nonlinearity is introduced into the input signal after passing through a nonlinear unit (such as a nonlinear amplifier, a nonlinear sampling circuit, or any other circuit module that may cause nonlinearity). The presence of such nonlinearity may reduce the performance of the analog-to-digital converter 10. In each embodiment of the disclosed embodiment, the analog input signal input to the analog-to-digital converter 10 may be regarded as including nonlinearity. After the analog input signal is input to the analog-to-digital converter 10, it is quantized by the analog-to-digital converter 10 to obtain an N-bit output quantization result.

[0079] Exemplarily, the quantization result is sent to a segmented fold line nonlinear calibration device. The correction behavior of the segmented fold line nonlinear calibration device is determined by the number of segmented fold lines that are preset. Figure 3a As shown, taking 4 segments of broken lines as an example, assuming that the full swing is 0 to A, it can be divided into four segments according to the quantization results: 0 to A / 4, A / 4 to A / 2, A / 2 to 3A / 4, and 3A / 4 to A. The width of each segment is defined as b0 (here b0 = A / 4). The signal is quantized with a unit step of b0 to obtain the MSB (quantization result, high n bits) and LSB (quantization residual, Nn bits). In the disclosed embodiment, the MSB reflects the segment in which the signal is. For a segment number of 2 n In the case of a power of , the first n bits can be directly used as the MSB and the remaining (Nn) bits as the LSB (for example Figure 3a and Figure 3b The 4 broken lines in the middle correspond to n=2).

[0080] For example, Figure 3b , Figure 3c The curve shown shows the distribution of MSB and LSB with input when the number of broken lines is set to 4. After the above division, each LSB segment can be approximately regarded as a straight line. To achieve nonlinear calibration, you only need to adjust the slopes of all LSBs to be consistent and splice them together.

[0081] Therefore, the embodiment of the present disclosure can select the corresponding correction coefficient (k1-k4) through the MSB to change the slope of the LSB so that the slopes of the curves of each part are equal, such as Figure 3b As shown in the red curve. Figure 3b As shown, for the overall curve of the input and output of the analog-to-digital converter 10, after correction, the slope of each LSB curve changes from the original unequal (red dotted line) to equal (red solid line). This operation corresponds to the principle that the first adjustment unit 20 selects a target slope from the slope storage unit 40 according to the high n bits of the analog-to-digital conversion result, and uses the target slope to adjust the low-bit quantization value corresponding to the Nn bits of the analog-to-digital conversion result to obtain the adjusted low-bit quantization value.

[0082] At the same time, in the splicing process, considering that the slopes of each part have changed, it is also necessary to select a suitable offset to ensure the continuity after splicing. Figure 3b As shown in the figure, the first segment LSB corresponds to the range of 0 to b0 before correction. After multiplying by the correction coefficient k1, Figure 3c As shown in the figure, the corresponding range becomes 0~k1b0, so the starting point of the second LSB segment becomes k1b0, recorded as b1. At the same time, the width of the coverage range of the second LSB segment also changes from b0 to k2b0, so the corresponding coverage range after correction is k1b0~(k1+k2)b0, recorded as b1~b2.

[0083] In the embodiment of the present disclosure, the second adjustment unit 30 adjusts the high-order quantization value corresponding to the high n bits of the analog-to-digital conversion result according to the slopes of the multiple intervals before the interval corresponding to the target slope, so as to reselect the correct offset, thereby realizing nonlinear segmented curved line calibration efficiently and accurately. This operation corresponds to Figure 3a The second multiplexer MUX2, accumulator AND0, second multiplier MUL2 and first adder AND1 shown in the figure select the slopes of multiple intervals before the interval corresponding to the target slope through the MSB, use the accumulator AND0 to accumulate, correct the high-order quantization value, and add it to the LSB obtained in the previous step. cal The final output is obtained by summing.

[0084] In the above operation, the slope (ki) and the offset (bi) are required, where the offset can be determined by the slope and the predefined step size (b0). Taking a 4-segment polyline as an example, the endpoints are: 0;

[0086] b1=k1b0;

[0087] b2=(k1+k2)b0;

[0088] b3=(k1+k2+k3)b0.

[0089] In summary, for the general case of an M-segment polyline, the general formula mentioned above can be obtained:

[0090] See also Figure 4 , Figure 4 A schematic diagram of a piecewise broken line nonlinear calibration device for an analog-to-digital converter 10 according to an embodiment of the present disclosure is shown.

[0091] In a possible implementation, Figure 4 As shown, the device may further include a parameter updating module 60, which is used to update the slope in the slope register and the endpoints of each interval segment using the calibrated analog-to-digital conversion result.

[0092] The embodiment of the present disclosure does not limit the specific implementation method of the parameter update module 60. Those skilled in the art may adopt relevant technologies to implement it according to actual conditions and needs, as long as the corresponding parameter update function can be achieved. The preferred implementation method is exemplarily introduced below.

[0093] In a possible implementation, Figure 4As shown, the parameter updating module 60 may include an endpoint updating unit 620 and a plurality of slope updating units 610, wherein the slope updating unit 610 is used to perform a slope updating operation, and the endpoint updating unit 620 is used to perform an endpoint updating operation according to the updated slope.

[0094] Each slope updating unit 610 may include an absolute value determiner 6110, a third multiplier MUL3 and a minimum mean square filter. For any slope updating unit 610:

[0095] The absolute value judge 6110 is used to judge the absolute value of the input sample and the value of the corresponding endpoint, and output the judgment result to the third multiplier MUL3, wherein the input sample is the difference (D out,cal -D d ), the input sample is used as the final analog-to-digital conversion result (Dout), wherein, when the absolute value of the input sample is greater than the value of the corresponding endpoint, the judgment result is 1; when the absolute value of the input sample is less than or equal to the value of the corresponding endpoint, the judgment result is 0,

[0096] The third multiplier MUL3 is used to perform a multiplication operation of the judgment result and the sample, and input the operation result into the minimum mean square filter.

[0097] The least mean square filter is used to receive the preset update parameter and the operation result, and output the updated slope,

[0098] Wherein, the preset update parameter is related to the digital code.

[0099] It is worth mentioning that Figure 4 Although the third adder is used to realize the difference between the calibrated analog-to-digital conversion result and the digital code of the random signal added to the analog input signal, the embodiment of the present disclosure is not limited to this. For example, the digital code of the random signal of the analog input signal can also be input into Figure 3a In the first adder AND1 in the embodiment, the input sample is obtained by using the first adder AND1, thereby saving hardware overhead.

[0100] For example, Figure 4 As shown, the random signal Vd can be added to the input signal Vin by using an adder in advance, and the input signal Vin after adding the random signal Vd passes through a nonlinear unit and is input into the analog-to-digital converter 10 as an analog input signal.

[0101] The embodiments of the present disclosure do not limit the specific implementation method of the absolute value judgement device 6110. Those skilled in the art may adopt relevant technologies to implement it according to actual conditions and needs. For example, the absolute value judgement device 6110 may include a first comparator, an inverter, and a second comparator. The first comparator is used to compare the input sample with 0. If the input sample is less than 0, the input sample is inverted through the inverter to obtain the absolute value of the input sample. If the input sample is greater than 0, there is no need to perform an inversion operation through the inverter. The second comparator can be used to perform a comparison operation between the absolute value of the input sample and the value of the corresponding endpoint. When the absolute value of the input sample is greater than the value of the corresponding endpoint, the judgment result is 1 (the second comparator outputs a high-level signal); when the absolute value of the input sample is less than or equal to the value of the corresponding endpoint, the judgment result is 0 (the second comparator outputs a low-level signal).

[0102] Of course, other methods can also be used to determine the absolute value of the input sample, such as using built-in functions: Many hardware platforms provide built-in functions for calculating absolute values. For example, in C language, you can use the abs function to calculate the absolute value of integers and the fabs function to calculate the absolute value of floating-point numbers; Two's complement operation: For signed integers, you can use the properties of two's complement to calculate the absolute value. In the two's complement representation, the two's complement of a negative number is the inversion of the binary representation of its absolute value and then add one. Through this operation, the absolute value of a negative number can be directly obtained.

[0103] The embodiments of the present disclosure do not limit the specific implementation of the endpoint update unit 620. Those skilled in the art can use relevant technologies to implement it according to actual conditions and needs, for example, it can be implemented by a processing component. For example, the processing component includes but is not limited to a separate processor, or a discrete component, or a combination of a processor and a discrete component. The processor may include a controller with an execution instruction function in an electronic device. The processor may be implemented in any appropriate manner, for example, by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors or other electronic components. Inside the processor, the executable instructions can be executed by hardware circuits such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0104] Exemplarily, after receiving the updated slope, the endpoint updating unit 620 may use the aforementioned endpoint formula Update the endpoint.

[0105] The embodiments of the present disclosure do not limit the specific implementation of the least mean square filter. Those skilled in the art can adopt relevant technologies to implement it according to actual conditions and needs, as long as the corresponding parameter update function can be achieved. The preferred implementation method is exemplarily introduced below.

[0106] In a possible implementation, Figure 4 As shown, the minimum mean square filter may include a fourth multiplier MUL4, a second adder AND2, and a delayer Delay1, wherein:

[0107] The fourth multiplier MUL4 is used to receive the operation result output by the third multiplier MUL3 and the preset update parameter, the output end of the fourth multiplier MUL4 is connected to the first input end of the second adder AND2, and the output end of the fourth multiplier MUL4 is used to output the product of the operation result output by the third multiplier MUL3 and the preset update parameter.

[0108] The second input end of the second adder AND2 is connected to the output end of the delayer Delay1.

[0109] The input end of the delayer Delay1 is connected to the output end of the second adder AND2 as the output end of the minimum mean square filter.

[0110] The preset update parameter is μ·sign(D d ), μ represents the preset value, sign() represents the sign function, D d Represents the digital code.

[0111] The embodiment of the present disclosure does not limit the specific parameter settings of the delayer Delay1, and the delay size can be flexibly set according to actual conditions and needs.

[0112] For example, Figure 4 As shown, a voltage signal Vd modulated by a pseudo-random code is added to the input signal Vin. The random code is independent of the input signal. After the input signal Vin passes through the nonlinear unit, it is input as an input analog signal to the analog-to-digital converter 10 for quantization. The quantization result is input to the analog-to-digital converter 10 as shown in FIG. Figure 2 After the nonlinear segmented fold line nonlinear calibration device (first adjustment unit 20, second adjustment unit 30) mentioned above, the code word D corresponding to the random code d Subtracted from the number domain (D out,cal -D d ). Assuming that the segmented zigzag nonlinear calibration device can completely correct all nonlinear errors, then the output Dout obtained after subtraction is equal to the random code D dOn the contrary, if the nonlinearity is not completely eliminated, Dout and D d Using this characteristic, the embodiment of the present disclosure updates the slope (ki) through the least mean square filter so that Dout and D d Decorrelation between them.

[0113] Since different calibration coefficients involve different samples, the embodiment of the present disclosure creatively uses a gated minimum mean square filter with an adaptive threshold to implement the update of the calibration coefficient.

[0114] For example, Figure 2 In the calibration device shown (first adjustment unit 20, second adjustment unit 30), coefficient k1 will directly affect samples with absolute values ​​of 0 to b0, and the corresponding absolute value range of this part of samples after correction is 0 to b1. At the same time, k1 will also affect samples with absolute values ​​> b0, and the corresponding range after correction is > b1. Because the calculation of this part of samples involves b1, b2, and b3, and k1 participates in the calculation of b1, b2, and b3. In other words, k1 will affect all samples, so all samples will be used to update k1. In contrast, k4 will only affect samples with absolute values ​​> b3 after correction, so only this part of samples will be used to update k4.

[0115] Based on this observation, the embodiment of the present disclosure inserts an absolute value judger 6110 and a third multiplier MUL3 as a range selector before each minimum mean square filter to judge the range of the input sample. Only when the input sample is within the corresponding range will it be sent to the minimum mean square filter to update the corresponding correction coefficient.

[0116] For example, Figure 4 As shown, the threshold of the range selector is the offset (bi), and bi is not a fixed value, but is determined by ki (the specific calculation formula is given in the previous article ). That is to say, bi is used to select samples for updating ki, and after completing the update of k1~k4, the corresponding b1~b3 will be recalculated and used as new thresholds to select updated samples. This is the adaptive threshold gated least mean square filter proposed in the embodiment of the present disclosure. In short, the meaning of "adaptive threshold" is that the threshold (bi) determines whether to update the coefficient (ki), and the threshold will be adjusted after the coefficient is updated, so it is called "adaptive threshold" (different from "fixed threshold").

[0117] Through the above method, the background extraction of the segmented broken line calibration coefficients can be realized.

[0118] The nonlinear calibration algorithm of the disclosed embodiment has the following advantages:

[0119] 1. The use of piecewise zigzag nonlinear calibration can greatly reduce the computational complexity, save area overhead and improve energy efficiency compared to traditional polynomial calibration.

[0120] 2. The proposed adaptive threshold gated minimum mean square filter can realize the background extraction of piecewise broken line coefficients at a very low digital cost, thus greatly expanding the application scenarios of the algorithm.

[0121] The present disclosure proposes a piecewise zigzag nonlinear calibration technology based on jitter injection and adaptive threshold gated minimum mean square filter, which can realize the background extraction of piecewise zigzag coefficients with low hardware complexity, thereby greatly expanding the application scope of the piecewise zigzag nonlinear calibration technology. The invention can be applied to all application scenarios that require nonlinear error calibration, such as high-speed and high-precision pipeline analog-to-digital converters 10, high-linearity sampling and holding front ends, etc.

[0122] According to one aspect of the present disclosure, a driver chip is provided, the driver chip comprising the piecewise broken line nonlinear calibration device of the analog-to-digital converter 10 .

[0123] According to one aspect of the present disclosure, an electronic device is provided, and the electronic device includes the driving chip.

[0124] Among them, the terminal device can be a user equipment (UE), a mobile device, a user terminal, a terminal, a handheld device, a computing device or a vehicle-mounted device, etc. For example, some examples of terminals are: mobile phones, tablet computers, laptop computers, PDAs, mobile Internet devices (MID), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control (Industrial Control), wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids (Smart Grid), wireless terminals in transportation safety (Transportation Safety), wireless terminals in smart cities (Smart City), wireless terminals in smart homes (Smart Home), wireless terminals in Internet of Vehicles, etc. For example, the server can be a local server or a cloud server.

[0125] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A piecewise fold line nonlinear calibration device for an analog-to-digital converter, characterized in that: The analog-to-digital converter is used to perform analog-to-digital conversion on an input analog input signal and output an analog-to-digital conversion result, wherein the device comprises: A first adjustment unit is connected to the output end of the analog-to-digital converter, and is used to select a target slope from a slope storage unit according to the high n bits of the analog-to-digital conversion result, and use the target slope to adjust the low-bit quantization value corresponding to the Nn bits of the analog-to-digital conversion result to obtain an adjusted low-bit quantization value, wherein N>n and are all positive integers, N is the conversion accuracy of the analog-to-digital converter, and the output range of the analog-to-digital converter is divided into a plurality of continuous interval segments, each of which corresponds to a slope; A second adjustment unit is connected to the output end of the analog-to-digital converter and the output end of the first adjustment unit, and the second adjustment unit is used to: adjust the high-order quantization value corresponding to the high n bits of the analog-to-digital conversion result according to the slopes of multiple interval segments before the interval segment corresponding to the target slope to obtain the adjusted high-order quantization value, and use the sum of the adjusted high-order quantization value and the adjusted low-order quantization value to obtain the calibrated analog-to-digital conversion result.

2. The device according to claim 1, characterized in that The slope storage unit includes a plurality of slope registers, each slope register stores a corresponding slope, and the first adjustment unit includes a first multiplexer and a first multiplier, wherein: The multiple input terminals of the first multiplexer are respectively connected to the slope registers of the slope storage unit, the control terminal of the first multiplexer is used to receive the upper n bits of the analog-to-digital conversion result, the output terminal of the first multiplexer is connected to the first input terminal of the first multiplier, and the output terminal of the first multiplexer is used to output the target slope. The second input end of the first multiplier is used to receive the low-order quantization value corresponding to the Nn bits of the analog-to-digital conversion result, the first multiplier is used to implement the multiplication operation of the low-order quantization value corresponding to the Nn bits of the analog-to-digital conversion result and the target slope, and the output end of the first multiplier is used to output the adjusted low-order quantization value.

3. The device according to claim 1 or 2, characterized in that: The second adjustment unit includes a second multiplexer, an accumulator, a second multiplier and a first adder, wherein: The second multiplexer is used to select the slopes of multiple intervals before the interval corresponding to the target slope from the slope storage unit according to the upper n bits of the analog-to-digital conversion result, and input them into the accumulator, and the accumulator is used to output the slope accumulation result; The second multiplier is used to implement a multiplication operation of a high-order quantization value corresponding to high n bits of the analog-to-digital conversion result and the slope accumulation result to obtain the adjusted high-order quantization value; The first adder is connected to the output end of the accumulator and the output end of the first adjustment unit, and is used to sum the adjusted high-order quantization value and the adjusted low-order quantization value to obtain a calibrated analog-to-digital conversion result.

4. The device according to claim 1, characterized in that The target slope is the ratio of the ideal slope of the analog-to-digital converter to the actual slope corresponding to the interval to which the quantization value corresponding to the upper n bits of the analog-to-digital conversion result belongs.

5. The device according to claim 1, characterized in that 2 n is the total number of divided intervals, In the initial case, the endpoints of each interval segment include the origin 0 and i×b0, b0=A / 2 n , 1≤i≤2 n And i is an integer, A=2 N represents the maximum output value of the analog-to-digital converter, After the device performs a calibration, the endpoints of each interval segment include 0 and b i , in, k i Represents the slope corresponding to the i-th interval, j is a positive integer.

6. The device according to claim 5, characterized in that The device also includes a parameter updating module, which is used to update the slope in the slope register and the endpoints of each interval segment using the calibrated analog-to-digital conversion result.

7. The device according to claim 6, characterized in that The parameter updating module includes an endpoint updating unit and a plurality of slope updating units, wherein the slope updating unit is used to perform a slope updating operation, and the endpoint updating unit is used to perform an endpoint updating operation according to the updated slope. Each slope updating unit includes an absolute value judger, a third multiplier and a minimum mean square filter. For any slope updating unit: The absolute value judger is used to judge the size of the absolute value of the input sample and the value of the corresponding endpoint, and output the judgment result to the third multiplier, wherein the input sample is the difference between the calibrated analog-to-digital conversion result and the digital code of the random signal added to the analog input signal, and the input sample is used as the final analog-to-digital conversion result, wherein when the absolute value of the input sample is greater than the value of the corresponding endpoint, the judgment result is 1; when the absolute value of the input sample is less than or equal to the value of the corresponding endpoint, the judgment result is 0. The third multiplier is used to perform a multiplication operation of the judgment result and the sample, and input the operation result into the minimum mean square filter. The least mean square filter is used to receive the preset update parameter and the operation result, and output the updated slope, Wherein, the preset update parameter is related to the digital code.

8. The device according to claim 7, characterized in that The minimum mean square filter includes a fourth multiplier, a second adder, and a delayer, wherein: The fourth multiplier is used to receive the operation result output by the third multiplier and the preset update parameter, the output end of the fourth multiplier is connected to the first input end of the second adder, and the output end of the fourth multiplier is used to output the product of the operation result output by the third multiplier and the preset update parameter, The second input terminal of the second adder is connected to the output terminal of the delay device. The input end of the delay device is connected to the output end of the second adder as the output end of the minimum mean square filter. The preset update parameter is μ·sign(D d ), μ represents the preset value, sign() represents the sign function, D d Represents the digital code.

9. A driver chip, characterized in that: The driving chip includes the piecewise broken line nonlinear calibration device of the analog-to-digital converter as described in any one of claims 1-8.

10. An electronic device, characterized in that: The electronic device comprises the driving chip as claimed in claim 9.

Images