Implementation method of NS SAR ADC based on dynamic amplifier multiplexing
By adopting dynamic amplifier multiplexing technology and fully differential structure in NS SAR ADC, the problems of noise shaping capabilities and circuit area of the existing NS SAR ADC are solved, and the analog-to-digital conversion effect with high precision and low power consumption are achieved.
Patent Information
- Application Number
- CN202411606796.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-12
- Publication Date
- 2025-05-16
AI Technical Summary
The applicability of existing NS SAR ADCs in the field of high-precision ADCs is limited by noise shaping capabilities and circuit area, and the additional noise and power consumption caused by traditional multi-input comparators are also a major problem.
The NS SAR ADC structure based on dynamic amplifier multiplexing is adopted to amplify the integral voltage through a dynamic amplifier and add it to the input signal in the next cycle to achieve a steeper noise transmission function and improve noise shaping capabilities. At the same time, a fully differential structure and capacitor stacking technology are used to reduce the capacitance area to avoid the noise and power consumption caused by multiple input comparators.
It significantly improves the noise shaping capability of the system, reduces the circuit area, and reduces power consumption, achieving high-precision analog-to-digital conversion.
Smart Images
Figure CN120017064A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of digital-analog hybrid integrated circuit design, and more specifically to an analog-to-digital converter. Background Art
[0002] SAR ADC has occupied the market of medium and high precision ADC due to its low power consumption and higher adaptability to advanced processes. However, due to the limitations of comparator noise and capacitor area, the applicability of SAR ADC in the field of high precision ADC is greatly reduced. Most traditional high precision ADCs still use Sigma Delta ADC architecture, but since Sigma Delta ADC needs to use amplifiers with better performance to achieve the integration function, this not only brings about the problem of high power consumption, but also makes Sigma Delta ADC unable to perfectly adapt to advanced processes. In order to make full use of the design advantages brought by advanced processes, NS SAR ADC came into being. NS SAR ADC combines the advantages of both and adds a loop filter on the basis of SAR ADC. Compared with SAR ADC, NS SAR ADC uses noise shaping and oversampling technology to more easily achieve high precision requirements.
[0003] In order to allow NS SAR ADC to maintain the low power consumption advantage of SAR ADC, passive integration loop filter becomes the first choice. Although passive integration effectively ensures low power consumption, the noise transfer function (NTF) of the passive integration structure achieved by charge sharing is relatively smooth, resulting in its general noise shaping ability. Traditional NS SAR ADC generally uses multi-input comparators to realize the addition of integration voltage and input signal. The additional input end of the comparator brings additional thermal noise, kickback noise and power consumption. In addition, the total integration capacitance of the traditional differential structure NS SAR ADC is twice that of the single-ended integration capacitance, resulting in the NS SAR ADC not having an advantage in circuit area.
[0004] In summary, the technical problems existing in the current NS SAR ADC related technologies need to be improved. Summary of the invention
[0005] The present invention proposes a method for realizing a NS SAR ADC based on dynamic amplifier multiplexing. The structure optimizes the noise shaping effect of passive integration.
[0006] The present invention realizes a NS SAR ADC based on dynamic amplifier multiplexing through the following technical means, and the method includes: a NS SAR ADC based on dynamic amplifier multiplexing includes a sampling and holding circuit, a comparator, a logic control circuit, a DAC capacitor array, and a loop filter, wherein the DAC capacitor array is further divided into DACP and DACN, and the loop filter includes a residual sampling capacitor CS, a first-order integration capacitor Cint1P,o, Cint1P,e, Cint1N,o, Cint1N,e, a second-order integration capacitor Cint2P,o, Cint2P,e, Cint2N,o, Cint2N,e, a dynamic amplifier and a plurality of switches.
[0007] Furthermore, the working sequence of the overall NS SAR ADC can be summarized as the following stages: the input voltage is sampled and input into the comparator, the comparator result is input into the logic control circuit, and then the switch switching of the DAC capacitor array is controlled to realize the successive approximation analog-to-digital conversion process, and then the remaining difference voltage is processed, and then the first-order passive integration and the first-order active amplification are performed to obtain the first-order integrated voltage, the second-order passive integration and the second-order active amplification are performed to obtain the second-order integrated voltage, and the two integrated voltages are added to the input voltage sampled in the next cycle to start the analog-to-digital conversion process of the next cycle.
[0008] Furthermore, in the residual processing stage of the NS SAR ADC, switches between the upper and lower plates of the residual sampling capacitor CS and the upper plates of DACP and DACN are closed, respectively, and other switches are opened.
[0009] Furthermore, in the first-order passive integration stage of the NS SAR ADC, in odd conversion cycles, the upper and lower plates of Cint1P,o and Cint1N,o are respectively closed with the switches between the upper plates of DACP and DACN, and the other switches are opened; in even conversion cycles, the upper and lower plates of Cint1P,e and Cint1N,e are respectively closed with the switches between the upper plates of DACP and DACN, and the other switches are opened.
[0010] Furthermore, in the first-order active amplification stage of the NS SAR ADC, the switches between the upper plates of DACP and DACN and the two input terminals of the dynamic amplifier are closed. In the odd conversion cycle, the upper and lower plates of Cint1P,e and Cint1N,e are respectively closed with the switches between the two output terminals of the dynamic amplifier, and the other switches are opened; in the even conversion cycle, the upper and lower plates of Cint1P,o and Cint1N,o are respectively closed with the switches between the two output terminals of the dynamic amplifier, and the other switches are opened.
[0011] Furthermore, in the second-order passive integration stage of the NS SAR ADC, in the odd conversion cycle, the switch between the upper plate of Cint1P,o and the upper plate of Cint1N,o is closed to form a passive charge pump with a double gain, which is used to amplify the voltage after the first-order passive integration by two times for the second-order passive integration, and the lower plate of Cint1N,o and the lower plate of Cint1P,o are respectively closed with the switches between the upper and lower plates of Cint2P,o and Cint2N,o, and the remaining switches are opened; in the even conversion cycle, the switch between the upper plate of Cint1P,e and the upper plate of Cint1N,e is closed, and the lower plate of Cint1N,e and the lower plate of Cint1P,e are respectively closed with the switches between the upper and lower plates of Cint2P,e and Cint2N,e, and the remaining switches are opened.
[0012] Furthermore, in the second-order active amplification stage of the NS SAR ADC, in the odd conversion cycle, the switch between the upper plate of Cint1P,o and the upper plate of Cint1N,o and the reference voltage VCM is closed, the switch between the lower plate of Cint1N,o and the lower plate of Cint1P,o and the two input terminals of the dynamic amplifier is closed, the switch between the upper and lower plates of Cint2P,e and Cint2N,e and the two output terminals of the dynamic amplifier is closed, and the remaining switches are opened; in the even conversion cycle, the switch between the upper plate of Cint1P,e and the upper plate of Cint1N,e and the reference voltage VCM is closed, the switch between the lower plate of Cint1N,e and the lower plate of Cint1P,e and the two input terminals of the dynamic amplifier is closed, the switch between the upper and lower plates of Cint2P,o and Cint2N,o and the two output terminals of the dynamic amplifier is closed, and the remaining switches are opened.
[0013] Furthermore, after the residual voltage is processed by the loop filter and the first and second order integration and amplification are completed, the NS SAR ADC performs the next conversion cycle. After the sampling is completed, the input signal voltage and the integrated voltage are summed using capacitor stacking technology and input into the comparator for quantization.
[0014] Furthermore, the above process is specifically as follows: if it is an odd conversion cycle, the lower plate of Cint1P,e is connected to DACP, the upper plate is connected to the lower plate of Cint2P,e, the upper plate of Cint2P,e is connected to the non-inverting input terminal of the comparator, the lower plate of Cint1N,e is connected to DACN, the upper plate is connected to the lower plate of Cint2N,e, and the upper plate of Cint2N,e is connected to the inverting input terminal of the comparator; if it is an even conversion cycle, the lower plate of Cint1P,o is connected to DACP, the upper plate is connected to the lower plate of Cint2P,o, the upper plate of Cint2P,o is connected to the non-inverting input terminal of the comparator, the lower plate of Cint1N,o is connected to DACN, the upper plate is connected to the lower plate of Cint2N,o, and the upper plate of Cint2N,o is connected to the inverting input terminal of the comparator.
[0015] Furthermore, the dynamic amplifiers are implemented by the same hardware structure, that is, the dynamic amplifier multiplexing technology for second-order noise shaping proposed by the present invention.
[0016] Furthermore, the Z-domain expression of the transfer function of the NS SAR ADC is: In the above formula, Dout(z) represents the voltage corresponding to the output digital code, Vin(z) represents the input voltage, and Q(z) represents the quantization noise.
[0017] The present invention has the following technical features: In order to construct a steeper NTF and improve the noise shaping capability, the present invention uses a dynamic amplifier to amplify the integrated voltage after the integration is completed, and then adds it to the input signal of the next cycle and quantizes it. After this operation, the NTF is almost close to , significantly improving the noise shaping capability of the system. Since a large number of capacitors are required to realize the passive integration and active amplification processes proposed in the present invention, in order to minimize the area of the capacitors, the present invention uses a fully differential structure, and uses capacitor stacking technology while reducing the capacitor area, thereby avoiding the additional noise and power consumption caused by the multi-input comparator. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 Simplified block diagram for a noise shaping SAR ADC.
[0019] Figure 2 This is the overall circuit implementation scheme for the second-order noise shaping SAR ADC.
[0020] Figure 3 Figure 2 is the signal flow graph for a second-order noise shaping SAR ADC.
[0021] Figure 4 Schematic diagram of the first-order passive integration.
[0022] Figure 5 Schematic diagram of the first-order active amplification.
[0023] Figure 6 Schematic diagram of the second-order passive integration.
[0024] Figure 7 Schematic diagram of the second-order active amplification.
[0025] Figure 8 Schematic diagram of summing the input signal and the integrated voltage.
[0026] Fig. 9 This is the timing diagram of the second-order noise shaping SAR ADC. DETAILED DESCRIPTION
[0027] The simplified block diagram of NS SAR ADC is shown in Figure 1 As shown, the input signal Vin is output as Dout after analog-to-digital conversion in the previous cycle, Vin is subtracted from Dout to obtain a residual voltage Vres, and Vres is added to the input signal Vin of this cycle after being processed by the loop filter and input into the comparator for quantization, thereby completing the analog-to-digital conversion of this cycle and achieving the effect of noise shaping.
[0028] The circuit architecture of the NS SAR ADC based on dynamic amplifier multiplexing proposed by the present invention is as follows: Figure 2 As shown, the overall circuit includes a sampling and holding circuit, a comparator, a logic control circuit, a DAC capacitor array, and a loop filter, wherein the DAC capacitor array is further divided into DACP and DACN, and the loop filter includes a residual sampling capacitor CS, a first-order integrating capacitor Cint1P,o, Cint1P,e, Cint1N,o, Cint1N,e, a second-order integrating capacitor Cint2P,o, Cint2P,e, Cint2N,o, Cint2N,e, a dynamic amplifier and a number of switches, wherein DACP=DACPN=C; CS=C / 2; Cint1P,o=Cint1P,e=Cint1N,o=Cint1N,e=C / 4; Cint2P,o=Cint2P,e=Cint2N,o=Cint2N,e=C / 16, Figure 2 The switches between the devices are controlled by ΦS1, ΦS2, ΦCOMP, ΦNS, ΦRES, ΦNS1, ΦNS2, and ΦNS3. The timing diagram is shown in Fig. 9 shown.
[0029] The signal flow diagram of a NS SAR ADC based on dynamic amplifier multiplexing proposed by the present invention is as follows: Figure 3As shown in the figure, the working sequence of the overall NS SAR ADC can be summarized as the following stages: the input voltage is sampled and input into the comparator, and the comparator result is input into the logic control circuit, which then controls the switch switching of the DAC capacitor array to realize the successive approximation analog-to-digital conversion process, and then processes the residual difference voltage. In the residual processing stage of the NS SAR ADC, the switches between the upper and lower plates of the residual sampling capacitor CS and the upper plates of DACP and DACN are closed respectively, and the other switches are opened. Then, the first-order passive integration and the first-order active amplification are performed to obtain the first-order integrated voltage, and the second-order passive integration and the second-order active amplification are performed to obtain the second-order integrated voltage. The two integrated voltages are added to the input voltage sampled in the next cycle, and the analog-to-digital conversion process of the next cycle is started.
[0030] The first-order passive integration operation of the NS SAR ADC based on dynamic amplifier multiplexing proposed by the present invention is as follows: Figure 4 As shown, in the first-order passive integration stage of the NS SAR ADC, in odd conversion cycles, the upper and lower plates of Cint1P,o and Cint1N,o are respectively closed with the switches between the upper plates of DACP and DACN, and the other switches are opened; in even conversion cycles, the upper and lower plates of Cint1P,e and Cint1N,e are respectively closed with the switches between the upper plates of DACP and DACN, and the other switches are opened.
[0031] The first-order active amplification operation of the NS SAR ADC based on dynamic amplifier multiplexing proposed by the present invention is as follows: Figure 5 As shown, in the first-order active amplification stage of the NS SAR ADC, the switches between the upper plates of DACP and DACN and the two input terminals of the dynamic amplifier are closed. In odd conversion cycles, the upper and lower plates of Cint1P,e and Cint1N,e are respectively closed with the switches between the two output terminals of the dynamic amplifier, and the other switches are opened; in even conversion cycles, the upper and lower plates of Cint1P,o and Cint1N,o are respectively closed with the switches between the two output terminals of the dynamic amplifier, and the other switches are opened.
[0032] The second-order passive integration operation of the NS SAR ADC based on dynamic amplifier multiplexing proposed by the present invention is as follows: Figure 6As shown, in the second-order passive integration stage of the NS SAR ADC, in the odd conversion cycle, the switch between the upper plate of Cint1P,o and the upper plate of Cint1N,o is closed to form a passive charge pump with a double gain, which is used to amplify the voltage after the first-order passive integration by two times and then perform the second-order passive integration. The lower plate of Cint1N,o and the lower plate of Cint1P,o are respectively closed with the switches between the upper and lower plates of Cint2P,o and Cint2N,o, and the other switches are opened; in the even conversion cycle, the switch between the upper plate of Cint1P,e and the upper plate of Cint1N,e is closed, the lower plate of Cint1N,e and the lower plate of Cint1P,e are respectively closed with the switches between the upper and lower plates of Cint2P,e and Cint2N,e, and the other switches are opened.
[0033] The second-order active amplification operation of the NS SAR ADC based on dynamic amplifier multiplexing proposed by the present invention is as follows: Figure 7 As shown, in the second-order active amplification stage of the NS SAR ADC, in the odd conversion cycle, the switch between the upper plate of Cint1P,o and the upper plate of Cint1N,o and the reference voltage VCM is closed, the switch between the lower plate of Cint1N,o and the lower plate of Cint1P,o and the two input terminals of the dynamic amplifier is closed, the upper and lower plates of Cint2P,e and Cint2N,e are closed respectively and the switches between the two output terminals of the dynamic amplifier are closed, and the remaining switches are opened; in the even conversion cycle, the switch between the upper plate of Cint1P,e and the upper plate of Cint1N,e and the reference voltage VCM is closed, the lower plate of Cint1N,e and the lower plate of Cint1P,e are closed respectively and the switches between the two input terminals of the dynamic amplifier are closed, the upper and lower plates of Cint2P,o and Cint2N,o are closed respectively and the switches between the two output terminals of the dynamic amplifier are closed, and the remaining switches are opened.
[0034] The input signal and integrated voltage summing operation of the NS SAR ADC based on dynamic amplifier multiplexing proposed by the present invention is as follows: Figure 8As shown in the figure, after the residual voltage is processed by the loop filter and the first and second order integration and amplification are completed, the NS SAR The ADC performs the next conversion cycle. After completing the sampling, the capacitor stacking technology is used to sum the input signal voltage and the integrated voltage, and the sum is input to the comparator for quantization. Specifically, if it is an odd conversion cycle, the lower plate of Cint1P,e is connected to DACP, the upper plate is connected to the lower plate of Cint2P,e, the upper plate of Cint2P,e is connected to the non-inverting input of the comparator, the lower plate of Cint1N,e is connected to DACN, the upper plate is connected to the lower plate of Cint2N,e, and the upper plate of Cint2N,e is connected to the inverting input of the comparator; if it is an even conversion cycle, the lower plate of Cint1P,o is connected to DACP, the upper plate is connected to the lower plate of Cint2P,o, the upper plate of Cint2P,o is connected to the non-inverting input of the comparator, the lower plate of Cint1N,o is connected to DACN, the upper plate is connected to the lower plate of Cint2N,o, and the upper plate of Cint2N,o is connected to the inverting input of the comparator.
[0035] In a NS SAR ADC based on dynamic amplifier multiplexing proposed in the present invention, the dynamic amplifiers used for two amplifications are implemented by the same hardware structure, that is, the dynamic amplifier multiplexing technology for second-order noise shaping proposed in the present invention, and the Z-domain expression of the transfer function of the NS SAR ADC is: In the above formula, Dout(z) represents the voltage corresponding to the output digital code, Vin(z) represents the input voltage, and Q(z) represents the quantization noise. The final result is This shows that the NS SAR ADC based on dynamic amplifier multiplexing proposed in the present invention has a stronger second-order noise shaping effect.
[0036] The above are all preferred specific implementations of the present invention. All equivalent changes and modifications made according to the patent of the present invention should fall within the scope of the present invention.
Claims
1. A method for implementing NS SAR ADC based on dynamic amplifier multiplexing, characterized in that: The structure includes a sampling and holding circuit, a comparator, a logic control circuit, a DAC capacitor array, and a loop filter, wherein the DAC capacitor array is further divided into DACP and DACN, and the loop filter includes a residual sampling capacitor CS, a first-order integrating capacitor Cint1P,o, Cint1P,e, Cint1N,o, Cint1N,e, a second-order integrating capacitor Cint2P,o, Cint2P,e, Cint2N,o, Cint2N,e, a dynamic amplifier and a plurality of switches.
2. The NS SAR ADC based on dynamic amplifier multiplexing according to claim 1, characterized in that: The working sequence of the overall NSSAR ADC can be summarized as the following stages: the input voltage is sampled and input into the comparator, the comparator result is input into the logic control circuit, and then the switch of the DAC capacitor array is controlled to realize the successive approximation analog-to-digital conversion process, and then the remaining difference voltage is processed, and then the first-order passive integration and the first-order active amplification are performed to obtain the first-order integrated voltage, the second-order passive integration and the second-order active amplification are performed to obtain the second-order integrated voltage, and the two integrated voltages are added to the input voltage sampled in the next cycle to start the analog-to-digital conversion process of the next cycle.
3. The NS SAR ADC working sequence based on dynamic amplifier multiplexing according to claim 2 is characterized in that: In the residual processing stage of the NS SAR ADC, the switches between the upper and lower plates of the residual sampling capacitor CS and the upper plates of DACP and DACN are closed, and the other switches are opened.
4. The NS SAR ADC working sequence based on dynamic amplifier multiplexing according to claim 2 is characterized in that: In the first-order passive integration stage of the NS SAR ADC, in odd conversion cycles, the upper and lower plates of Cint1P,o and Cint1N,o are respectively closed with the switches between the upper plates of DACP and DACN, and the other switches are opened; in even conversion cycles, the upper and lower plates of Cint1P,e and Cint1N,e are respectively closed with the switches between the upper plates of DACP and DACN, and the other switches are opened.
5. The NS SAR ADC working sequence based on dynamic amplifier multiplexing according to claim 2 is characterized in that: In the first-order active amplification stage of the NS SAR ADC, the switches between the upper plates of DACP and DACN and the two input terminals of the dynamic amplifier are closed. In the odd conversion cycle, the upper and lower plates of Cint1P,e and Cint1N,e are respectively closed with the switches between the two output terminals of the dynamic amplifier, and the other switches are opened; in the even conversion cycle, the upper and lower plates of Cint1P,o and Cint1N,o are respectively closed with the switches between the two output terminals of the dynamic amplifier, and the other switches are opened.
6. The NS SAR ADC working sequence based on dynamic amplifier multiplexing according to claim 2, characterized in that: In the second-order passive integration stage of the NS SAR ADC, in the odd conversion cycle, the switch between the upper plate of Cint1P,o and the upper plate of Cint1N,o is closed, the lower plate of Cint1N,o and the lower plate of Cint1P,o are respectively closed with the switches between the upper and lower plates of Cint2P,o and Cint2N,o, and the other switches are opened; in the even conversion cycle, the switch between the upper plate of Cint1P,e and the upper plate of Cint1N,e is closed, the lower plate of Cint1N,e and the lower plate of Cint1P,e are respectively closed with the switches between the upper and lower plates of Cint2P,e and Cint2N,e, and the other switches are opened.
7. The NS SAR ADC working sequence based on dynamic amplifier multiplexing according to claim 2, characterized in that: In the second-order active amplification stage of the NS SAR ADC, in the odd conversion cycle, the switch between the upper plate of Cint1P,o and the upper plate of Cint1N,o and the reference voltage VCM is closed, the switch between the lower plate of Cint1N,o and the lower plate of Cint1P,o and the two input terminals of the dynamic amplifier is closed, the switch between the upper and lower plates of Cint2P,e and Cint2N,e and the two output terminals of the dynamic amplifier is closed, and the other switches are opened; in the even conversion cycle, the switch between the upper plate of Cint1P,e and the upper plate of Cint1N,e and the reference voltage VCM is closed, the switch between the lower plate of Cint1N,e and the lower plate of Cint1P,e and the two input terminals of the dynamic amplifier is closed, the switch between the upper and lower plates of Cint2P,o and Cint2N,o and the two output terminals of the dynamic amplifier is closed, and the other switches are opened.
8. The NS SAR ADC working sequence based on dynamic amplifier multiplexing according to claim 2 is characterized in that: After the residual voltage is processed by the loop filter and the first and second order integration and amplification are completed, the NS SAR The ADC performs the next conversion cycle. After completing the sampling, the input signal voltage is summed with the integrated voltage and input into the comparator for quantization. Specifically, if it is an odd conversion cycle, the lower plate of Cint1P,e is connected to DACP, the upper plate is connected to the lower plate of Cint2P,e, the upper plate of Cint2P,e is connected to the non-inverting input of the comparator, the lower plate of Cint1N,e is connected to DACN, the upper plate is connected to the lower plate of Cint2N,e, and the upper plate of Cint2N,e is connected to the inverting input of the comparator; if it is an even conversion cycle, the lower plate of Cint1P,o is connected to DACP, the upper plate is connected to the lower plate of Cint2P,o, the upper plate of Cint2P,o is connected to the non-inverting input of the comparator, the lower plate of Cint1N,o is connected to DACN, the upper plate is connected to the lower plate of Cint2N,o, and the upper plate of Cint2N,o is connected to the inverting input of the comparator.
9. Active amplification stage according to claims 5 and 7, characterized in that The dynamic amplifiers are implemented by the same hardware structure, that is, the dynamic amplifier multiplexing technology for second-order noise shaping proposed by the present invention.
10. The NS SAR ADC based on dynamic amplifier multiplexing according to claim 1, characterized in that: The Z-domain expression of the transfer function of the NS SAR ADC is: In the above formula, Dout(z) represents the voltage corresponding to the output digital code, Vin(z) represents the input voltage, and Q(z) represents the quantization noise.