A signature generation method for physically unclonable functions that reuse LBIST structures

Abstract

This invention discloses a signature generation method for a Physically Unclonable Function (PUF) reusing an LBIST structure, comprising: an excitation decoding stage, a capture clock cycle calibration stage, a response generation stage, and a signature correction stage. This invention enables the implementation of a PUF circuit without altering the original LBIST structure, thereby achieving low resource overhead while ensuring sufficient reliability of the PUF.

Description

Technical Field

[0001] This invention belongs to the field of information security technology, specifically a signature generation method for Physically Unclonable Functions (PUFs) that reuse the LBIST structure. Background Technology

[0002] With the exponential growth of IoT and edge computing devices, the demand for secure identity authentication of hardware devices is becoming increasingly urgent. Physically unclonable functions (PUFs), as a core technology in the field of hardware security, generate unique "fingerprints" by extracting inherent process deviations generated during chip manufacturing, and have shown unique advantages in areas such as device authentication and key generation.

[0003] With the exponential growth of IoT devices, PUF (Power-Only Function) technology must adapt to the stringent resource constraints of edge devices while maintaining stable response characteristics under complex operating conditions, posing a dual challenge to traditional implementation solutions. Among current mainstream silicon-based PUF implementations, SRAM-based architectures offer mature process compatibility, but achieving sufficient entropy sources requires large-area memory arrays, leading to a simultaneous increase in static power consumption and chip area. Auxiliary calibration circuits introduced to address response stability issues often increase the overall module's transistor count by more than 30%, which is particularly unsuitable for resource-constrained scenarios such as sensor nodes. On the other hand, while timing-competitive ring oscillator PUF architectures alleviate the area expansion problem to some extent, their response generation process is extremely sensitive to temperature drift and power supply noise, resulting in a high bit error rate. To compensate for reliability degradation caused by environmental disturbances, existing solutions must introduce complex error correction encoding / decoding modules, which not only leads to a step increase in system power consumption but also essentially creates a vicious cycle where reliability improvement depends on additional resource investment. This antagonistic relationship between resource efficiency and reliability has become a key bottleneck restricting the penetration of PUF technology into ultra-low power IoT nodes. Especially in industrial sensor networks that require long-term maintenance-free operation, the contradiction between the risk of bit error accumulation during the life cycle of the existing architecture and the energy consumption budget is becoming increasingly irreconcilable.

[0004] Therefore, there is an urgent need for a PUF implementation method that can both reuse existing hardware resources to reduce overhead and improve reliability through hardware and software co-design. Summary of the Invention

[0005] This invention addresses the shortcomings of existing technologies by proposing a signature generation method for Physically Unclonable Functions (PUFs) that reuse the LBIST structure. The aim is to achieve a low-overhead PUF circuit without altering the chip's circuit under test and scan chain structure, while simultaneously ensuring PUF stability. This effectively improves the overall security of IoT systems and supports the construction of a more reliable information infrastructure.

[0006] To achieve the above-mentioned objectives, the present invention adopts the following technical solution:

[0007] The present invention provides a signature generation method for a Physically Unclonable Function (PUF) that reuses an LBIST structure. The PUF circuit comprises: a main controller, a compensation circuit, a clock generator, a clock delay line, a clock switching circuit, and a clock shielding circuit. The main controller consists of an excitation decoding module, a control module, and a calibration module. The clock generator generates a reference clock. and offset clock The multiplexed LBIST structure comprises a phase-locked loop (PLL); the multiplexed LBIST structure includes a pseudo-random pattern generator, a circuit under test (DUT), and a multi-input feature register; wherein the DUT contains M scan chains, each scan chain has N flip-flops, and the signature generation method is performed according to the following steps:

[0008] Step 1: During the excitation decoding stage of the Physically Unclonable Function (PUF), the excitation decoding module of the main controller receives the externally input excitation signal Challenge and outputs the seed to the pseudo-random mode generator to initialize its initial state. At the same time, it outputs the capture time CM and the initial feedback coefficient fc of the multi-input feature register to the control module and sets the excitation decoding completion signal decoder_fin to 1.

[0009] Step 2: During the calibration phase of the Physically Unclonable Function (PUF), the control module controls the period T of the capture clock output by the clock switching circuit to be adjusted by the calibration module. capture Perform calibration and generate a calibration completion signal adjust_fin;

[0010] Step 3: In the response generation stage of the Physically Unclonable Function (PUF), generate the original response and redundant responses:

[0011] Step 4: In the signature correction stage of the Physically Unclonable Function (PUF), the redundant stimulus-response pair consisting of the stimulus signal Challenge and the redundant response is compared with the redundant stimulus-response pair registered in the server. The comparison result is used to list a system of linear equations and solve them to obtain the flip-flop that has reversed in the circuit under test. This flip-flop is used to correct the original response and obtain the final signature for security authentication of the Internet of Things.

[0012] The signature generation method for a physically unclonable function (PUF) reusing the LBIST structure described in this invention is also characterized in that step 2 includes:

[0013] Step 2.1: If the control module detects that the excitation decoding completion signal decoder_fin is 1, then initialize the delay reference clock of the clock delay line. The count of the rising edge is 0;

[0014] Step 2.2: Delay reference clock for clock delay lines When the first rising edge of the clock arrives, define the left endpoint and right endpoint of the interval, and initialize them to 0 and 31 respectively. Define the array variable Array_Tcapture

[32] , and the array variable Array_Tcapture

[32] stores the interval values ​​between 90% and 110% of the median of the transient response time of all test paths of the circuit under test.

[0015] The control module controls the clock offset of the clock generator. The phase of the clock and the clock path selection signal sel1 of the clock delay line are used to change the capture clock period T. capture The value can be taken as Array_Tcapture[(left+right) / 2-1];

[0016] The control module stores the initial feedback coefficient fc of the multi-input feature register in the first row Array_c[0] of the feedback coefficient array Array_c[M][N] of the multi-input feature register. The second row Array_c[1], the third row Array_c[2], the fourth row Array_c[3], ..., the Mth row Array_c[M-1] of the feedback coefficient array Array_c[M][N] sequentially store... , , ... ;

[0017] The control module sets the clock switching signal sel2 of the clock switching circuit to 1, causing the global clock CLK to switch to the phase-shift clock. At the same time, the calibration start signal adjust_flag is set to 1, and the current state of the output signal CCO of the compensation circuit is recorded.

[0018] The stimulus decoding module clears the stimulus decoding completion signal decoder_fin to zero.

[0019] Step 2.3: Delay the reference clock When the second rising edge of the clock arrives, if the calibration module detects that the calibration start signal adjust_flag is 1, it sets the clock enable signal sel3 of the compensation circuit to 1 to enable the clock of the compensation circuit; at the same time, the control module clears the clock switching signal sel2 to zero, so that the global clock CLK switches to the original clock. Simultaneously, the calibration start signal adjust_flag is cleared to zero, and the clock offset of the clock generator is controlled. The phase of the clock path selection signal sel1 and the clock path selection signal sel1 are used to change the capture clock period T. capture The value is Array_Tcapture[(left+right) / 2];

[0020] Step 2.4: Delay the reference clock When the third rising edge of the clock arrives, the calibration module clears the clock enable signal sel3 of the compensation circuit to zero, which is used as the clock for the disabling compensation circuit, and the control module sets the clock switching signal sel2 to 1, so that the global clock CLK switches to the phase-shift clock. Meanwhile, the current state of the output signal CCO of the compensation circuit is recorded. If the current state of the output signal CCO of the compensation circuit is opposite to the previous state, the output state array variable CCO_state[0] of the compensation circuit is set to 1; otherwise, the output state array variable CCO_state[0] of the compensation circuit is set to 0.

[0021] Step 2.5: Delay the reference clock When the fourth rising edge of the clock arrives, the calibration module sets the clock enable signal sel3 of the compensation circuit to 1 to enable the clock of the compensation circuit. At the same time, the control module clears the clock switching signal sel2, causing the global clock CLK to switch to the original clock. And control the offset clock of the clock generator. The phase of the clock path selection signal sel1 and the clock path selection signal sel1 are used to change the capture clock period T. capture The value can be taken as Array_Tcapture[(left+right) / 2+1];

[0022] Step 2.6: Delay the reference clock When the fifth rising edge of the clock arrives, the calibration module clears the clock enable signal sel3 of the compensation circuit to zero, which is used as the clock for the disabling compensation circuit. The control module sets the clock switching signal sel2 to 1, causing the global clock CLK to switch to the phase-shift clock. Meanwhile, the current state of the output signal CCO of the compensation circuit is recorded. If the current state of the output signal CCO of the compensation circuit is opposite to the previous state, the output state array variable CCO_state[1] of the compensation circuit is set to 1; otherwise, the output state array variable CCO_state[1] of the compensation circuit is set to 0.

[0023] Step 2.7: Delay the reference clock When the 6th rising edge of the clock arrives, the calibration module sets the compensation circuit clock enable signal sel3 to 1 to enable the clock of the compensation circuit, and the control module clears the clock switching signal sel2 to zero, so that the global clock CLK switches to the original clock. ;

[0024] Step 2.8: Delay the reference clock When the 7th rising edge of the clock arrives, the calibration module clears the clock enable signal sel3 of the compensation circuit to zero, which is used as the clock for the disabling compensation circuit. At the same time, if the output state array variable CCO_state[0]=1 and CCO_state[1]=1 of the compensation circuit, the calibration module sets the calibration completion signal adjust_fin to 3; if the output state array variable CCO_state[0]=0, CCO_state[1]=0 and the current state of the output signal CCO of the compensation circuit is opposite to the previous clock state, the calibration module sets the calibration completion signal adjust_fin to 3; otherwise, the calibration module sets the calibration completion signal adjust_fin to 2. CCO_state[0] ;

[0025] Step 2.9: Delay the reference clock When the 8th rising edge of the clock arrives, if the calibration completion signal adjust_fin is 3, the control module sets the left endpoint left and the right endpoint right of the interval to 0 and 31 respectively. At the same time, the calibration module clears the output state array variables CCO_state[0], CCO_state[1] and the calibration completion signal adjust_fin of the compensation circuit to zero, and then executes step 3.

[0026] If the calibration completion signal adjust_fin is 2, the control module sets the left endpoint of the interval to (left+right) / 2, and simultaneously controls the clock generator's offset clock. The phase of the clock path selection signal sel1 and the clock path selection signal sel1 are used to change the capture clock period T. capture The value is set to Array_Tcapture[(left+right) / 2-1], and the clock switching signal sel2 is set to 1, causing the global clock CLK to switch to the phase-shift clock. Simultaneously, the calibration module clears the output state array variables CCO_state[0], CCO_state[1] and the calibration completion signal adjust_fin of the compensation circuit to zero, and initializes the delay reference clock of the clock delay line. After the rising edge count reaches 0, return to step 2.3 and execute sequentially;

[0027] If the calibration completion signal adjust_fin is 1, the control module sets the right endpoint of the interval to (left+right) / 2, and simultaneously controls the clock generator's offset clock. The phase of the clock path selection signal sel1 and the clock path selection signal sel1 are used to change the capture clock period T. capture The value is set to Array_Tcapture[(left+right) / 2-1], and the clock switching signal sel2 is set to 1, causing the global clock CLK to switch to the phase-shift clock. Simultaneously, the calibration module clears the output state array variables CCO_state[0], CCO_state[1] and the calibration completion signal adjust_fin of the compensation circuit to zero, and initializes the delay reference clock of the clock delay line. After the rising edge count reaches 0, return to step 2.3 for sequential execution.

[0028] Furthermore, step 3 includes:

[0029] Step 3.1: Combine the number of generated responses cnt of the Physically Unclonable Function (PUF), the row index c_index of the feedback coefficient array Array_c[M][N], and the delay reference clock of the clock delay line. The number of rising edges is initialized to 0;

[0030] Step 3.2: Delay the reference clock When the first rising edge of the clock arrives, the control module clears the reset signal rst_prpg of the pseudo-random mode generator to prevent the triggers in the pseudo-random mode generator from being continuously reset.

[0031] Step 3.3: Delay the reference clock When the rising edge of the CM-th clock arrives, if the number of generated responses cnt is 0, the control module sets the clock switching signal sel2 to 1, causing the global clock CLK to switch to the phase-shifted clock. The clock enable signal sel4 of the clock shielding circuit is set to 1 to disable the clock of the multi-input feature register, and the scan enable signal SCAN_EN of the multiplexed LBIST structure is cleared to enable the scan chain to work in the functional mode.

[0032] If the number of generated responses cnt is not 0, the control module sets the reset signal rst_misr of the multi-input feature register to 1 to reset the flip-flops in the multi-input feature register, and sets the clock switching signal sel2 to 1, so that the global clock CLK switches to the phase-shift clock. Set the clock enable signal sel4 of the clock shielding circuit to 1 to disable the clock of the multi-input feature register, and clear the scan enable signal SCAN_EN to enable the scan chain to work in the functional mode.

[0033] Step 3.4: Delay the reference clock When the falling edge arrives, the control module sets the scan enable signal SCAN_EN to 1, enabling the scan chain to operate in scan mode;

[0034] Step 3.5: Delay the reference clock When the (CM+1)th rising edge of the clock arrives, the control module clears the reset signal rst_misr of the multi-input feature register to prevent continuous reset of the flip-flops in the multi-input feature register, and clears the clock switching signal sel2 to switch the global clock CLK to the original clock. Clear the clock enable signal sel4 to enable the clock of the multi-input feature register. Simultaneously, if the number of generated responses cnt is greater than 0, the output terminal OUT of the multi-input feature register will start outputting the first bit of the redundant response, and will be updated to the reference clock. When the next rising edge of the clock arrives, the next bit of the redundant response is output sequentially until the M-1 bits of the redundant response are output.

[0035] Step 3.6: Delay the reference clock When the (CM+M)th clock rising edge arrives, if the number of generated responses cnt is greater than 0, the output terminal OUT of the multi-input feature register begins to output the Mth bit of the redundant response, and at the reference clock... When the next rising edge of the clock arrives, the next bit of the redundant response is output sequentially until the M+N-2 bits of the redundant response are output.

[0036] If the number of generated responses, cnt, is 0, then the output terminal OUT of the multi-input feature register begins to output the first bit of the original response, and at the reference clock... When the next rising edge of the clock arrives, the next bit of the original response is output sequentially until the N-1 bits of the original response are output;

[0037] Step 3.7: Delay the reference clock When the rising edge of the clock (CM+M+N-1) arrives, if the number of generated responses (cnt) is 0, the output terminal OUT of the multi-input feature register will output the Nth bit of the original response, i.e., the last bit.

[0038] If the number of generated responses cnt is greater than 0, the output terminal OUT of the multi-input feature register outputs the M+N-1th bit of the redundant response, i.e., the last bit.

[0039] If the number of generated responses, cnt, equals M, the control module clears cnt to zero, sets the finish signal to 1, and delays the reference clock. When the rising edge of the CM+M+N clock arrives, the control module will clear the finish signal and then execute step 4.

[0040] If the number of generated responses, cnt, is less than M, the controller increments cnt by 1 and sets the reset signal rst_prpg of the pseudo-random pattern generator to 1 to reset the triggers in the pseudo-random pattern generator. Simultaneously, it sets the row index c_index of the feedback coefficient array Array_c[M][N] to 1. and initialize the delay reference clock of the clock delay line. After the count of the rising number reaches 0, return to step 3.2 for sequential execution.

[0041] The present invention provides an electronic device, including a memory and a processor, wherein the memory is used to store a program that supports the processor in executing the signature generation method, and the processor is configured to execute the program stored in the memory.

[0042] The present invention discloses a computer-readable storage medium on which a computer program is stored, wherein the computer program is executed by a processor to perform the steps of the signature generation method.

[0043] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0044] 1. This invention reuses the structure of LBIST without affecting its normal operation. It achieves low resource overhead while having a large number of stimulus response pairs, significantly reducing the hardware cost of resource-sensitive devices such as the Internet of Things and edge computing.

[0045] 2. This invention first uses a compensation circuit to calibrate the capture clock cycle, and then uses a signature correction algorithm to reduce the error during the capture transient response, thereby improving the reliability of PUF and ensuring the security of the Internet of Things.

[0046] 3. This invention uses a high-frequency adjustable clock to capture the transient response in the circuit under test, forming the chip's original "fingerprint," which is easy to integrate into existing systems and has high compatibility. Attached Figure Description

[0047] Figure 1 This is a structural diagram of the overall framework of the present invention;

[0048] Figure 2 This is an interface diagram of the main controller of the present invention;

[0049] Figure 3 This is a structural diagram of the clock circuit of the present invention;

[0050] Figure 4 This is a structural diagram of the compensation circuit of the present invention;

[0051] Figure 5 This is a schematic diagram of the test path structure in the circuit under test of this invention;

[0052] Figure 6 This is a structural diagram of the multi-input feature register of the present invention. Detailed Implementation

[0053] In this embodiment, a signature generation method for a physically unclonable function (PUF) that reuses the LBIST structure is described, such as... Figure 1 As shown, the circuit of the Physically Unclonable Function (PUF) is characterized by comprising: a main controller, a compensation circuit, a clock generator, a clock delay line, a clock switching circuit, and a clock shielding circuit; wherein, as... Figure 2 As shown, the main controller consists of an excitation decoding module, a control module, and a calibration module; as Figure 3 As shown, the clock generator consists of a unit that can generate a reference clock. and offset clock Composed of phase-locked loops; such as Figure 1 As shown, the reused LBIST structure includes: a pseudo-random pattern generator, a circuit under test (DUT), and a multi-input feature register; wherein, the DUT contains M scan chains, each with N flip-flops, and the signature generation method is performed according to the following steps:

[0054] Step 1: During the excitation decoding stage of the Physically Unclonable Function (PUF), the excitation decoding module of the main controller receives the externally input excitation signal Challenge and outputs the seed to the pseudo-random mode generator to initialize its initial state. At the same time, it outputs the capture time CM and the initial feedback coefficient fc of the multi-input feature register to the control module and sets the excitation decoding completion signal decoder_fin to 1.

[0055] Step 2: During the calibration phase of the Physically Unclonable Function (PUF), the control module controls the period T of the capture clock output by the clock switching circuit to be adjusted. capture For calibration, the Physically Unclonable Function (PUF) generates a response by capturing the transient response in the circuit under test (DUT), therefore the capture clock period T... captureThe relative relationship between voltage and transient response time determines the response result. However, changes in voltage and temperature can significantly alter the delay of cells or interconnects in the circuit, thus affecting the transient response time. Therefore, to obtain stable results, it is necessary to control the capture clock period T. capture Calibration is performed, and the basic principle of calibration is to make the capture clock period T... capture Approximately equal to the total delay of the calibration circuit, delay=t clk-to-q +d invs +t setup ,like Figure 4 As shown, t clk-to-q For the delay of the trigger clk-to-q, d invs For the delay of the inverter chain, t setup The total delay of the calibration circuit is approximately equal to the average transient response time of the circuit under test (DUT) to the setup time of the trigger. When voltage and temperature change, the total delay of the calibration circuit will change synchronously with the average transient response time of the DUT. A compensation circuit is used to calibrate the capture clock period T. capture After that, the capture clock cycle T can be made capture It is always approximately equal to the average transient response time of the circuit under test.

[0056] Step 2.1: If the control module detects that the excitation decoding completion signal decoder_fin is 1, then initialize the delay reference clock of the clock delay line. The count of the rising edge is 0;

[0057] Step 2.2: Delay reference clock for clock delay lines When the first rising edge of the clock arrives, define the left endpoint (left) and right endpoint (right) of the interval and initialize them to 0 and 31 respectively. Define an array variable Array_Tcapture

[32] , which stores the interval values ​​between 90% and 110% of the median of the transient response time of all test paths of the circuit under test, such as... Figure 5 As shown, the transient response time of the test path is the time it takes for the clock signal to pass through the first flip-flop, then through the test path, and finally reach the input of the second flip-flop.

[0058] The control module controls the offset clock of the clock generator. The phase and clock path selection signal sel1 of the clock delay line is used to change the capture clock period T. capture The value can be taken as Array_Tcapture[(left+right) / 2-1];

[0059] The control module stores the initial feedback coefficient fc of the multi-input feature register in the first row Array_c[0] of the feedback coefficient array Array_c[M][N] of the multi-input feature register. The second row Array_c[1], the third row Array_c[2], the fourth row Array_c[3], ..., the Mth row Array_c[M-1] of the feedback coefficient array Array_c[M][N] store the initial feedback coefficient fc of the multi-input feature register in the first row Array_c[0]. , , ... ;

[0060] The control module sets the clock switching signal sel2 of the clock switching circuit to 1, causing the global clock CLK to switch to the phase-shift clock. At the same time, the calibration start signal adjust_flag is set to 1, and the current state of the output signal CCO of the compensation circuit is recorded.

[0061] The stimulus decoding module clears the stimulus decoding completion signal decoder_fin to zero.

[0062] Step 2.3: Delay the reference clock When the second rising edge of the clock arrives, if the calibration module detects that the calibration start signal adjust_flag is 1, it sets the clock enable signal sel3 of the compensation circuit to 1 to enable the clock of the compensation circuit; at the same time, the control module clears the clock switching signal sel2 to zero, so that the global clock CLK switches to the original clock. Simultaneously, the calibration start signal adjust_flag is cleared to zero, and the clock offset of the clock generator is controlled. The phase and clock path selection signal sel1 is used to change the capture clock period T. capture The value is Array_Tcapture[(left+right) / 2].

[0063] Step 2.4: Delay the reference clock When the third rising edge of the clock arrives, the calibration module clears the clock enable signal sel3 of the compensation circuit to zero, which is used as the clock for the disabling compensation circuit, and the control module sets the clock switching signal sel2 to 1, causing the global clock CLK to switch to the phase-shift clock. Meanwhile, the current state of the output signal CCO of the compensation circuit is recorded. If the current state of the output signal CCO of the compensation circuit is opposite to the previous state, the output state array variable CCO_state[0] of the compensation circuit is set to 1; otherwise, the output state array variable CCO_state[0] of the compensation circuit is set to 0. The output state of the compensation circuit satisfies the following relationship (1):

[0064] (1)

[0065] In equation (1), t clk-to-q For the delay of the trigger clk-to-q, d invs For the delay of the inverter chain, t setup t is the setup time of the trigger. hold This is the hold time of the trigger.

[0066] Step 2.5: Delay the reference clock When the fourth rising edge of the clock arrives, the calibration module sets the clock enable signal sel3 of the compensation circuit to 1 to enable the clock of the compensation circuit. At the same time, the control module clears the clock switching signal sel2, causing the global clock CLK to switch to the original clock. And control the offset clock of the clock generator. The phase and clock path selection signal sel1 is used to change the capture clock period T. capture The value can be taken as Array_Tcapture[(left+right) / 2+1];

[0067] Step 2.6: Delay the reference clock When the fifth rising edge of the clock arrives, the calibration module clears the clock enable signal sel3 of the compensation circuit to zero, which is used as the clock for the disabling compensation circuit. The control module sets the clock switching signal sel2 to 1, causing the global clock CLK to switch to the phase-shift clock. Meanwhile, the current state of the output signal CCO of the compensation circuit is recorded. If the current state of the output signal CCO of the compensation circuit is opposite to the previous state, the output state array variable CCO_state[1] of the compensation circuit is set to 1; otherwise, the output state array variable CCO_state[1] of the compensation circuit is set to 0.

[0068] Step 2.7: Delay the reference clock When the 6th rising edge of the clock arrives, the calibration module sets the compensation circuit clock enable signal sel3 to 1 to enable the clock of the compensation circuit, and the control module clears the clock switching signal sel2 to zero, so that the global clock CLK switches to the original clock. ;

[0069] Step 2.8: Delay the reference clock When the 7th rising edge of the clock arrives, the calibration module clears the clock enable signal sel3 of the compensation circuit to zero, which is used as the clock for the disabling compensation circuit. At the same time, if the output state array variable CCO_state[0]=1 and CCO_state[1]=1 of the compensation circuit, the calibration module sets the calibration completion signal adjust_fin to 3. At this time, the current state of the output signal CCO of the compensation circuit recorded in the previous two times is the opposite of the previous state, indicating that the delay reference clock... The second clock adjustment capture clock cycle T capture T before capture < t clk-to-q +d invs -t hold In the delayed reference clock The second clock adjustment capture clock cycle T capture After T capture > t clk-to-q +d invs +t setup If the output state array variables CCO_state[0]=0 and CCO_state[1]=0 of the compensation circuit, and the current state of the output signal CCO of the compensation circuit is opposite to the previous clock state, then the calibration module sets the calibration completion signal adjust_fin to 3. At this time, the relationship between the current state of the output signal CCO of the compensation circuit recorded in the previous two times and the previous state is opposite, and the delay reference clock is also equal. On the 7th clock cycle, the current state of the compensation circuit's output signal CCO is opposite to the previous state, indicating that the delay reference clock... The 4th clock adjustment capture clock cycle T capture T before capture <t clk-to-q +d invs -t hold In the delayed reference clock The 4th clock adjustment capture clock cycle T capture After T capture >t clk-to-q +d invs +t setup Conversely, the calibration module sets the calibration completion signal adjust_fin to 2. CCO_state[0] When CCO_state[0]=0, it indicates that the capture clock cycle T is complete. capture The value is too large, and the capture clock period T needs to be further reduced. capture When CCO_state[0]=1, it indicates that the capture clock cycle T is complete. capture The time is too small; the capture clock period T needs to be increased further. capture .

[0070] Step 2.9: Delay the reference clock When the 8th rising edge of the clock arrives, if the calibration completion signal adjust_fin is 3, the control module sets the left endpoint left and the right endpoint right of the interval to 0 and 31 respectively. At the same time, the calibration module clears the output state array variables CCO_state[0], CCO_state[1] and the calibration completion signal adjust_fin of the compensation circuit to zero, and then executes step 3.

[0071] If the calibration completion signal adjust_fin is 2, the control module sets the left endpoint of the interval to (left+right) / 2, narrowing the interval to the right half, and simultaneously controls the offset clock of the clock generator. The phase and clock path selection signal sel1 is used to change the capture clock period T. capture The value is set to Array_Tcapture[(left+right) / 2-1], and the clock switching signal sel2 is set to 1, causing the global clock CLK to switch to the phase-shift clock. Meanwhile, the calibration module clears the output state array variables CCO_state[0], CCO_state[1] and the calibration completion signal adjust_fin of the compensation circuit to zero, and initializes the delay reference clock of the clock delay line. After the rising edge count reaches 0, return to step 2.3 and execute sequentially;

[0072] If the calibration completion signal adjust_fin is 1, the control module sets the right endpoint of the interval to (left+right) / 2, narrowing the interval to the left half, and simultaneously controls the clock offset of the clock generator. The phase and clock path selection signal sel1 is used to change the capture clock period T. capture The value is set to Array_Tcapture[(left+right) / 2-1], and the clock switching signal sel2 is set to 1, causing the global clock CLK to switch to the phase-shift clock. Meanwhile, the calibration module clears the output state array variables CCO_state[0], CCO_state[1] and the calibration completion signal adjust_fin of the compensation circuit to zero, and initializes the delay reference clock of the clock delay line. After the rising edge count reaches 0, return to step 2.3 for sequential execution.

[0073] Step 3: In the response generation phase of the Physically Unclonable Function (PUF), the original response and redundant responses are generated. This phase will generate 1 original response and M redundant responses:

[0074] Step 3.1: Combine the number of generated responses cnt of the Physically Unclonable Function (PUF), the row index c_index of the feedback coefficient array Array_c[M][N], and the delay reference clock of the clock delay line. The number of rising edges is initialized to 0;

[0075] Step 3.2: Delay the reference clock When the first rising edge of the clock arrives, the control module clears the reset signal rst_prpg of the pseudo-random mode generator to prevent the triggers in the pseudo-random mode generator from being continuously reset.

[0076] Step 3.3: Delay the reference clock When the rising edge of the CM-th clock arrives, if the number of generated responses cnt is 0, the control module sets the clock switching signal sel2 to 1, causing the global clock CLK to switch to the phase-shifted clock. The clock enable signal sel4 of the clock shielding circuit is set to 1 to disable the clock of the multi-input feature register, and the scan enable signal SCAN_EN of the multiplexed LBIST structure is cleared to enable the scan chain to work in functional mode.

[0077] If the number of generated responses, cnt, is not 0, the control module sets the reset signal rst_misr of the multi-input feature register to 1 to reset the flip-flops in the multi-input feature register, and sets the clock switching signal sel2 to 1, causing the global clock CLK to switch to the phase-shift clock. Set the clock enable signal sel4 of the clock shielding circuit to 1 to disable the clock of the multi-input feature register, and clear the scan enable signal SCAN_EN to enable the scan chain to work in functional mode.

[0078] Step 3.4: Delay the reference clock When the falling edge arrives, the control module sets the scan enable signal SCAN_EN to 1, enabling the scan chain to operate in scan mode.

[0079] Step 3.5: Delay the reference clock When the (CM+1)th rising edge of the clock arrives, the control module clears the reset signal rst_misr of the multi-input feature register to prevent continuous reset of the flip-flops in the multi-input feature register, and clears the clock switching signal sel2 to switch the global clock CLK to the original clock. Clear the clock enable signal sel4 to enable the clock of the multi-input feature register. Simultaneously, if the number of generated responses cnt is greater than 0, the output terminal OUT of the multi-input feature register will start outputting the first bit of the redundant response, and will be updated to the reference clock. When the next rising edge of the clock arrives, the next bit of the redundant response is output sequentially until the M-1 bits of the redundant response are output.

[0080] Step 3.6: Delay the reference clock When the (CM+M)th clock rising edge arrives, if the number of generated responses cnt is greater than 0, the output terminal OUT of the multi-input feature register begins to output the Mth bit of the redundant response, and at the reference clock... When the next rising edge of the clock arrives, the next bit of the redundant response is output sequentially until the M+N-2 bits of the redundant response are output.

[0081] If the number of generated responses, cnt, is 0, then the output terminal OUT of the multi-input feature register begins to output the first bit of the original response, and at the reference clock... When the next rising edge of the clock arrives, the next bit of the original response is output sequentially until the N-1 bits of the original response are output. The structure of the multi-input feature register is as follows: Figure 6 As shown, where c0, c1, ..., c m-1 (c m-1 =1) is the feedback coefficient of the multi-input feature register. M bits of data are input in parallel each cycle. The state transition equation of the scan flip-flop is equation (2):

[0082] (2)

[0083] In equation (2), Y(L) is the state vector of the flip-flop in the Lth clock cycle, Y(0) is the initial state vector of the flip-flop, A is the transformation matrix, and D... i Let M be the M-bit vector input to the flip-flop in the i-th cycle. Then, in the first M clock cycles, the output of the multi-input feature register is given by equation (3):

[0084] (3)

[0085] As can be seen from equation (3), the output does not depend on the feedback coefficient during the first M-1 clock cycles. Therefore, if the first M-1 bits of the output are retained, this part of the original response may be easily predicted by an attacker. To avoid this situation, the first bit of the original response is delayed from the reference clock. Starting from the (CM+M)th clock rising edge, and for the redundant response, since it does not involve the leakage of the original response, there is no need to remove the first M-1 bits. Therefore, the first bit of the redundant response starts from the delayed reference clock. It starts at the (CM+1)th rising edge of the clock.

[0086] Step 3.7: Delay the reference clock When the rising edge of the clock (CM+M+N-1) arrives, if the number of generated responses (cnt) is 0, the output terminal OUT of the multi-input feature register will output the Nth bit of the original response, i.e., the last bit.

[0087] If the number of generated responses cnt is greater than 0, the output terminal OUT of the multi-input feature register outputs the M+N-1th bit of the redundant response, i.e., the last bit.

[0088] If the number of generated responses, cnt, equals M, the control module clears cnt to zero, sets the finish signal to 1, and delays the reference clock. When the rising edge of the CM+M+N clock arrives, the control module will clear the finish signal and then execute step 4.

[0089] If the number of generated responses, cnt, is less than M, the controller increments cnt by 1 and sets the reset signal rst_prpg of the pseudo-random pattern generator to 1 to reset the triggers in the pseudo-random pattern generator. Simultaneously, it sets the row index c_index of the feedback coefficient array Array_c[M][N] to 1. and initialize the delay reference clock of the clock delay line. After the count of the rising number reaches 0, return to step 3.2 and execute sequentially.

[0090] Step 4: In the signature correction stage of the Physically Unclonable Function (PUF), the redundant stimulus response pair consisting of the stimulus signal Challenge and the redundant response is compared with the redundant stimulus response pair registered in the server. The comparison result is used to list the linear equations and solve them, because the multi-input feature register was reset before generating the redundant response in step 3.5. Combining with equation (3), it can be seen that the first M bits of the M redundant responses are the same. Then there are M*(M+N-1)-M*(M-1)=MN valid equations in this linear equation system. Since there are MN scan flip-flops, there are also MN unknowns. Therefore, the equation system has one and only one solution. The flip-flop that reversed in the circuit under test is obtained and used to correct the original response to obtain the final signature for the security authentication of the Internet of Things. The redundant stimulus response pair registered in the server refers to the redundant stimulus response pair generated by the Physically Unclonable Function (PUF) at room temperature, standard atmospheric pressure and standard voltage and stored in the server.

[0091] In this embodiment, an electronic device includes a memory and a processor. The memory stores a program that supports the processor in executing the above-described method, and the processor is configured to execute the program stored in the memory.

[0092] In this embodiment, a computer-readable storage medium stores a computer program, which is executed by a processor to perform the steps of the above method.

Claims

1. A signature generation method for a Physically Unclonable Function (PUF) reusing the LBIST structure, characterized in that, The circuitry of the Physically Unclonable Function (PUF) includes: a main controller, a compensation circuit, a clock generator, a clock delay line, a clock switching circuit, and a clock shielding circuit; wherein, the main controller consists of an excitation decoding module, a control module, and a calibration module; the clock generator comprises a component for generating a reference clock. and offset clock The multiplexed LBIST structure comprises a phase-locked loop (PLL); the multiplexed LBIST structure includes a pseudo-random pattern generator, a circuit under test (DUT), and a multi-input feature register; wherein the DUT contains M scan chains, each scan chain has N flip-flops, and the signature generation method is performed according to the following steps: Step 1: During the excitation decoding stage of the Physically Unclonable Function (PUF), the excitation decoding module of the main controller receives the externally input excitation signal Challenge and outputs the seed to the pseudo-random mode generator to initialize its initial state. At the same time, it outputs the capture time CM and the initial feedback coefficient fc of the multi-input feature register to the control module and sets the excitation decoding completion signal decoder_fin to 1. Step 2: During the calibration phase of the Physically Unclonable Function (PUF), the control module controls the period T of the capture clock output by the clock switching circuit to be adjusted by the calibration module. capture Perform calibration and generate a calibration completion signal adjust_fin; Step 2.1: If the control module detects that the excitation decoding completion signal decoder_fin is 1, then initialize the delay reference clock of the clock delay line. The count of the rising edge is 0; Step 2.2: Delay reference clock for clock delay lines When the first rising edge of the clock arrives, define the left endpoint and right endpoint of the interval, and initialize them to 0 and 31 respectively. Define the array variable Array_Tcapture[32], and the array variable Array_Tcapture[32] stores the interval values ​​between 90% and 110% of the median of the transient response time of all test paths of the circuit under test. The control module controls the clock offset of the clock generator. The phase of the clock and the clock path selection signal sel1 of the clock delay line are used to change the capture clock period T. capture The value can be taken as Array_Tcapture[(left+right) / 2-1]; The control module stores the initial feedback coefficient fc of the multi-input feature register in the first row Array_c[0] of the feedback coefficient array Array_c[M][N] of the multi-input feature register. The second row Array_c[1], the third row Array_c[2], the fourth row Array_c[3], ..., the Mth row Array_c[M-1] of the feedback coefficient array Array_c[M][N] sequentially store... , , ... ; The control module sets the clock switching signal sel2 of the clock switching circuit to 1, causing the global clock CLK to switch to the phase-shift clock. At the same time, the calibration start signal adjust_flag is set to 1, and the current state of the output signal CCO of the compensation circuit is recorded. The stimulus decoding module clears the stimulus decoding completion signal decoder_fin to zero. Step 2.3: Delay the reference clock When the second rising edge of the clock arrives, if the calibration module detects that the calibration start signal adjust_flag is 1, it sets the clock enable signal sel3 of the compensation circuit to 1 to enable the clock of the compensation circuit; at the same time, the control module clears the clock switching signal sel2 to zero, so that the global clock CLK switches to the original clock. Simultaneously, the calibration start signal adjust_flag is cleared to zero, and the clock offset of the clock generator is controlled. The phase of the clock path selection signal sel1 and the clock path selection signal sel1 are used to change the capture clock period T. capture The value is Array_Tcapture[(left+right) / 2]; Step 2.4: Delay the reference clock When the third rising edge of the clock arrives, the calibration module clears the clock enable signal sel3 of the compensation circuit to zero, which is used as the clock for the disabling compensation circuit, and the control module sets the clock switching signal sel2 to 1, so that the global clock CLK switches to the phase-shift clock. Meanwhile, the current state of the output signal CCO of the compensation circuit is recorded. If the current state of the output signal CCO of the compensation circuit is opposite to the previous state, the output state array variable CCO_state[0] of the compensation circuit is set to 1; otherwise, the output state array variable CCO_state[0] of the compensation circuit is set to 0. Step 2.5: Delay the reference clock When the fourth rising edge of the clock arrives, the calibration module sets the clock enable signal sel3 of the compensation circuit to 1 to enable the clock of the compensation circuit. At the same time, the control module clears the clock switching signal sel2, causing the global clock CLK to switch to the original clock. And control the offset clock of the clock generator. The phase of the clock path selection signal sel1 and the clock path selection signal sel1 are used to change the capture clock period T. capture The value can be taken as Array_Tcapture[(left+right) / 2+1]; Step 2.6: Delay the reference clock When the fifth rising edge of the clock arrives, the calibration module clears the clock enable signal sel3 of the compensation circuit to zero, which is used as the clock for the disabling compensation circuit. The control module sets the clock switching signal sel2 to 1, causing the global clock CLK to switch to the phase-shift clock. Meanwhile, the current state of the output signal CCO of the compensation circuit is recorded. If the current state of the output signal CCO of the compensation circuit is opposite to the previous state, the output state array variable CCO_state[1] of the compensation circuit is set to 1; otherwise, the output state array variable CCO_state[1] of the compensation circuit is set to 0. Step 2.7: Delay the reference clock When the 6th rising edge of the clock arrives, the calibration module sets the compensation circuit clock enable signal sel3 to 1 to enable the clock of the compensation circuit, and the control module clears the clock switching signal sel2 to zero, so that the global clock CLK switches to the original clock. ; Step 2.8: Delay the reference clock When the 7th rising edge of the clock arrives, the calibration module clears the clock enable signal sel3 of the compensation circuit to zero, which is used as the clock for the disabling compensation circuit. At the same time, if the output state array variable CCO_state[0]=1 and CCO_state[1]=1 of the compensation circuit, the calibration module sets the calibration completion signal adjust_fin to 3; if the output state array variable CCO_state[0]=0, CCO_state[1]=0 and the current state of the output signal CCO of the compensation circuit is opposite to the previous clock state, the calibration module sets the calibration completion signal adjust_fin to 3; otherwise, the calibration module sets the calibration completion signal adjust_fin to 2. CCO_state[0] ; Step 2.9: Delay the reference clock When the 8th rising edge of the clock arrives, if the calibration completion signal adjust_fin is 3, the control module sets the left endpoint left and the right endpoint right of the interval to 0 and 31 respectively. At the same time, the calibration module clears the output state array variables CCO_state[0], CCO_state[1] and the calibration completion signal adjust_fin of the compensation circuit to zero, and then executes step 3. If the calibration completion signal adjust_fin is 2, the control module sets the left endpoint of the interval to (left+right) / 2, and simultaneously controls the clock generator's offset clock. The phase of the clock path selection signal sel1 and the clock path selection signal sel1 are used to change the capture clock period T. capture The value is set to Array_Tcapture[(left+right) / 2-1], and the clock switching signal sel2 is set to 1, causing the global clock CLK to switch to the phase-shift clock. Simultaneously, the calibration module clears the output state array variables CCO_state[0], CCO_state[1] and the calibration completion signal adjust_fin of the compensation circuit to zero, and initializes the delay reference clock of the clock delay line. After the rising edge count reaches 0, return to step 2.3 and execute sequentially; If the calibration completion signal adjust_fin is 1, the control module sets the right endpoint of the interval to (left+right) / 2, and simultaneously controls the clock generator's offset clock. The phase of the clock path selection signal sel1 and the clock path selection signal sel1 are used to change the capture clock period T. capture The value is set to Array_Tcapture[(left+right) / 2-1], and the clock switching signal sel2 is set to 1, causing the global clock CLK to switch to the phase-shift clock. Simultaneously, the calibration module clears the output state array variables CCO_state[0], CCO_state[1] and the calibration completion signal adjust_fin of the compensation circuit to zero, and initializes the delay reference clock of the clock delay line. After the rising edge count reaches 0, return to step 2.3 and execute sequentially; Step 3: In the response generation stage of the Physically Unclonable Function (PUF), generate the original response and redundant responses: Step 3.1: Combine the number of generated responses cnt of the Physically Unclonable Function (PUF), the row index c_index of the feedback coefficient array Array_c[M][N], and the delay reference clock of the clock delay line. The number of rising edges is initialized to 0; Step 3.2: Delay the reference clock When the first rising edge of the clock arrives, the control module clears the reset signal rst_prpg of the pseudo-random mode generator to prevent the triggers in the pseudo-random mode generator from being continuously reset. Step 3.3: Delay the reference clock When the rising edge of the CM-th clock arrives, if the number of generated responses cnt is 0, the control module sets the clock switching signal sel2 to 1, causing the global clock CLK to switch to the phase-shifted clock. The clock enable signal sel4 of the clock shielding circuit is set to 1 to disable the clock of the multi-input feature register, and the scan enable signal SCAN_EN of the multiplexed LBIST structure is cleared to enable the scan chain to work in the functional mode. If the number of generated responses cnt is not 0, the control module sets the reset signal rst_misr of the multi-input feature register to 1 to reset the flip-flops in the multi-input feature register, and sets the clock switching signal sel2 to 1, so that the global clock CLK switches to the phase-shift clock. Set the clock enable signal sel4 of the clock shielding circuit to 1 to disable the clock of the multi-input feature register, and clear the scan enable signal SCAN_EN to enable the scan chain to work in the functional mode. Step 3.4: Delay the reference clock When the falling edge arrives, the control module sets the scan enable signal SCAN_EN to 1, enabling the scan chain to operate in scan mode; Step 3.5: Delay the reference clock When the (CM+1)th rising edge of the clock arrives, the control module clears the reset signal rst_misr of the multi-input feature register to prevent continuous reset of the flip-flops in the multi-input feature register, and clears the clock switching signal sel2 to switch the global clock CLK to the original clock. Clear the clock enable signal sel4 to enable the clock of the multi-input feature register. Simultaneously, if the number of generated responses cnt is greater than 0, the output terminal OUT of the multi-input feature register will start outputting the first bit of the redundant response, and will be updated to the reference clock. When the next rising edge of the clock arrives, the next bit of the redundant response is output sequentially until the M-1 bits of the redundant response are output. Step 3.6: Delay the reference clock When the (CM+M)th clock rising edge arrives, if the number of generated responses cnt is greater than 0, the output terminal OUT of the multi-input feature register begins to output the Mth bit of the redundant response, and at the reference clock... When the next rising edge of the clock arrives, the next bit of the redundant response is output sequentially until the M+N-2 bits of the redundant response are output. If the number of generated responses, cnt, is 0, then the output terminal OUT of the multi-input feature register begins to output the first bit of the original response, and at the reference clock... When the next rising edge of the clock arrives, the next bit of the original response is output sequentially until the N-1 bits of the original response are output; Step 3.7: Delay the reference clock When the rising edge of the clock (CM+M+N-1) arrives, if the number of generated responses (cnt) is 0, the output terminal OUT of the multi-input feature register will output the Nth bit of the original response, i.e., the last bit. If the number of generated responses cnt is greater than 0, the output terminal OUT of the multi-input feature register outputs the M+N-1th bit of the redundant response, i.e., the last bit. If the number of generated responses, cnt, equals M, the control module clears cnt to zero, sets the finish signal to 1, and delays the reference clock. When the rising edge of the CM+M+N clock arrives, the control module will clear the finish signal and then execute step 4. If the number of generated responses, cnt, is less than M, the controller increments cnt by 1 and sets the reset signal rst_prpg of the pseudo-random pattern generator to 1 to reset the triggers in the pseudo-random pattern generator. Simultaneously, it sets the row index c_index of the feedback coefficient array Array_c[M][N] to 1. and initialize the delay reference clock of the clock delay line. After the count of the rising number reaches 0, return to step 3.2 and execute sequentially; Step 4: In the signature correction stage of the Physically Unclonable Function (PUF), the redundant stimulus-response pair consisting of the stimulus signal Challenge and the redundant response is compared with the redundant stimulus-response pair registered in the server. The comparison result is used to list a system of linear equations and solve them to obtain the flip-flop that has reversed in the circuit under test. This flip-flop is used to correct the original response and obtain the final signature for security authentication of the Internet of Things.

2. An electronic device, comprising a memory and a processor, characterized in that, The memory is used to store a program that supports the processor in executing the signature generation method of claim 1, and the processor is configured to execute the program stored in the memory.

3. A computer-readable storage medium storing a computer program, characterized in that, The computer program is executed by the processor to perform the steps of the signature generation method of claim 1.

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