Wireless communication receiver and signal receiving control method thereof
By introducing a signal detection module into the wireless communication receiver, the signal validity is judged and signal synchronization is performed only when it is valid, the problem of high power consumption in the signal synchronization process of the wireless communication receiver is solved, and lower power consumption and more efficient signal processing is achieved.
Patent Information
- Application Number
- CN202510166297.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-14
- Publication Date
- 2025-05-16
AI Technical Summary
Wireless communication receivers consume a lot of hardware resources and power consumption during signal synchronization, especially when there is no valid signal input.
Before signal synchronization processing, the received signal is first detected to determine whether it is a valid signal. The signal synchronization process is performed only when a valid signal is detected, and the signal and reference sequence are quantized and compressed and sparse during related calculations to simplify the multiplication operation as a shift operation.
It effectively avoids the problem of dynamic power consumption caused by the constant operation of the signal synchronization module, reduces the power consumption in the standby state of the receiver, and reduces the calculation amount and hardware resources consumption.
Smart Images
Figure CN120017472A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a wireless communication receiver and a signal receiving control method thereof, belonging to the technical field of wireless communication signal processing. Background Art
[0002] Power Line Communication (PLC) technology has been widely used in smart grid data collection and meter reading systems, among which the OFDM (Orthogonal Frequency Division Multiplexing) method can effectively improve the communication rate and anti-interference performance in PLC. However, relying solely on power line communication may reduce the success rate of meter reading in a complex and changeable line environment. Therefore, a dual-mode architecture is gradually adopted, that is, the power line is used as the main communication channel, supplemented by the wireless communication mode, which complements each other under specific conditions to improve the success rate and reliability of meter reading.
[0003] In traditional solutions, the receiver often continuously synchronizes the received signal during the reception process. Signal synchronization involves complex complex signal correlation operations, which consumes a large number of chip hardware resources such as multipliers, adders, and registers. This will still consume a lot of power when there is no valid signal input. Summary of the invention
[0004] The object of the present invention is to provide a wireless communication receiver and a signal reception control method thereof, so as to solve the problem of high consumption in the current wireless communication receiver during the signal synchronization process of the received signal.
[0005] In order to solve the above technical problems, the present invention provides a signal reception control method of a wireless communication receiver, the control method comprising the following steps:
[0006] 1) Performing signal detection on the signal received by the wireless communication receiver to determine whether the received signal is a valid signal; the signal detection is obtained by performing correlation calculation on the received signal and the local reference sequence. During the correlation calculation, the received signal and the local reference sequence are quantized and compressed respectively to simplify the multiplication operation during the correlation calculation into a shift operation;
[0007] 2) If the detected signal is a valid signal, signal synchronization processing is performed, otherwise signal synchronization processing is not performed.
[0008] Furthermore, the process of quantizing and compressing the received signal and the local reference sequence respectively includes:
[0009] The received signal and the local reference sequence are quantized respectively, and the quantized data only contains 1 sign bit and exponent bits within N bits, where N is related to the length of the received signal and the local reference sequence.
[0010] Furthermore, the method also includes performing sparse processing on the local reference sequence and the received signal after quantization and compression processing, respectively, and performing correlation calculations on the local reference sequence after sparse processing and the received signal; the sparse processing refers to extracting valid points from the quantized local reference sequence or the received signal at certain multiple intervals in the time domain.
[0011] Furthermore, the method for determining a valid signal is:
[0012] The peak value and peak position are determined based on the correlation amplitude obtained by correlation calculation. If the interval with the peak position determined to be valid last time meets the set conditions, it is judged to be a valid signal.
[0013] Furthermore, the method also includes other receiving processing processes entering the time domain processing stage after the signal synchronization is successful, entering the frequency domain processing stage after obtaining the frequency domain data of the OFDM symbol in the time domain processing stage, and obtaining the constellation demapped data from the frequency domain data of the OFDM symbol in the frequency domain processing stage; entering the bit domain processing stage after obtaining the constellation demapped data in the frequency domain processing stage to complete the bit domain data processing in the bit domain processing stage; the time domain processing stage, the frequency domain processing stage and the bit domain processing stage are three processing stages of the signal receiving process received by the wireless communication receiver.
[0014] The present invention also provides a wireless communication receiver, including a signal synchronization module, which includes a signal detection module, the signal detection module is used to detect the signal received by the wireless communication receiver, and determine whether the received signal is a valid signal, if the detected signal is a valid signal, then start the rear signal synchronization module, otherwise do not start the signal synchronization module;
[0015] The signal detection module is used to perform correlation calculation on the received signal and the local reference sequence, and judge whether it is a valid signal according to the correlation amplitude of the correlation calculation. During the correlation calculation, the received signal and the local reference sequence are quantized and compressed respectively to simplify the multiplication operation during the correlation calculation into a shift operation.
[0016] Furthermore, the process of the signal detection module quantizing and compressing the received signal and the local reference sequence includes:
[0017] The received signal and the local reference sequence are quantized respectively, and the quantized data only contains 1 sign bit and exponent bits within N bits, where N is related to the length of the received signal and the local reference sequence.
[0018] Furthermore, the signal detection module is also used to perform sparse processing on the local reference sequence and the received signal after quantization and compression processing, and perform correlation calculation on the local reference sequence after sparse processing and the received signal; the sparse processing refers to extracting valid points from the quantized local reference sequence or the received signal at certain multiple intervals in the time domain.
[0019] Furthermore, the method for determining a valid signal is:
[0020] The peak value and peak position are determined based on the correlation amplitude obtained by correlation calculation. If the interval with the peak position determined to be valid last time meets the set conditions, it is judged to be a valid signal.
[0021] Furthermore, the signal synchronization module starts other parts in the time domain processing module when synchronization is successful, the frequency domain processing module starts only after the time domain processing module is finished, and the bit domain processing module starts only after the frequency domain processing module is finished;
[0022] The time domain processing module, the frequency domain processing module and the bit domain processing module are modules for receiving processing in a wireless communication receiver. The time domain processing module is used to perform signal detection, signal synchronization and time-frequency conversion on the received signal; the frequency domain processing module is used to perform channel estimation and compensation, diversity combining and constellation demapping on the frequency domain signal output by the time domain processing module; and the bit domain processing module is used to decode and verify the constellation demapped data output by the frequency domain processing module.
[0023] The beneficial effects of the present invention are as follows: as an improved invention, the present invention first performs signal detection on the received signal of the wireless communication receiver before performing signal synchronization processing on the signal received by the wireless communication receiver, determines whether the received signal is a valid signal, and starts signal synchronization processing only after determining that the signal is a valid signal, thereby avoiding the problem of high dynamic power consumption caused by the continuous operation of signal synchronization processing. At the same time, when performing correlation calculation, the signal detection quantizes and compresses the received signal and the local reference sequence respectively, so as to simplify the multiplication operation in the correlation calculation into a shift operation, thereby reducing the amount of calculation and the flipping of the combinational logic circuit, and reducing the power consumption of the receiver in the standby state. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 is a flow chart of a signal receiving control method of a wireless communication receiver of the present invention;
[0025] Figure 2 It is a schematic diagram of hierarchical gating adopted by the wireless communication receiver of the present invention;
[0026] Figure 3 It is a processing flow chart of the signal detection module in an embodiment of the present invention. DETAILED DESCRIPTION
[0027] The specific implementation of the present invention will be further described below in conjunction with the accompanying drawings.
[0028] The present invention performs signal detection on the received signal of the wireless communication receiver before performing signal synchronization processing on the received signal of the wireless communication receiver to determine whether the received signal is a valid signal. The signal synchronization processing is started only after a valid signal is determined, thereby avoiding the problem of high dynamic power consumption caused by the continuous operation of the signal synchronization processing. At the same time, when performing correlation calculation, the signal detection quantizes and compresses the received signal and the local reference sequence respectively.
[0029] Embodiments of wireless communication receivers
[0030] like Figure 1 As shown, the receiving processing flow of the wireless communication receiver includes a time domain processing process, a frequency domain processing process and a bit domain processing process, so the data receiving processing in the wireless communication receiver includes a time domain processing module, a frequency domain processing module and a bit domain processing module. The time domain processing module is used to perform signal detection, signal synchronization and time-frequency conversion on the received signal; the frequency domain processing module is used to perform channel estimation and compensation, diversity combining and constellation demapping on the frequency domain signal output by the time domain processing module; the bit domain processing module is used to decode and verify the constellation demapped data output by the frequency domain processing module. The present invention adds a signal detection module on the basis of the existing time domain processing, which is used to perform signal detection on the received signal of the wireless communication receiver and determine whether the received signal is a valid signal. If the detected signal is a valid signal, the rear signal synchronization module is started, otherwise the signal synchronization module is not started.
[0031] Specifically, the time domain processing module includes: signal detection module, signal synchronization module, frequency offset estimation and compensation module, cyclic prefix removal module and fast Fourier transform (FFT) module. The frequency domain processing module includes: channel estimation and compensation, diversity combining, constellation demapping and other modules. The bit domain processing module includes: Turbo decoding and CRC check modules. Except for the signal detection module, the other modules are commonly used in wireless communication receivers and will not be described in detail here. The processing of the signal detection module is explained below.
[0032] The signal detection module in this embodiment uses the short-time training sequence STF of the signal frame as the local reference sequence L, performs correlation calculation with the received signal R, and then performs peak detection to detect the signal. Assuming the length of the correlation sequence is n, the cross-correlation calculation formula is expressed as follows:
[0033]
[0034] Both L and R represent sequences. kand R k They represent the kth point in the corresponding sequence, and n represents the number of points in the sequence.
[0035] The input signal obtained by the receiver from the ADC is usually quantized data of more than 12 bits to support the original high-precision operation. When the cross-correlation value between the signal and the local reference sequence is directly calculated, it will lead to problems of large hardware resource consumption, high computational complexity and high power consumption. In order to reduce the computational complexity and amount of calculation of the signal detection module, the signal detection module is used to perform correlation calculation on the received signal and the local reference sequence, and judge whether it is a valid signal according to the correlation amplitude of the correlation calculation. During the correlation calculation, the received signal and the local reference sequence are quantized and compressed respectively to simplify the multiplication operation during the correlation calculation into a shift operation.
[0036] Specifically, only one sign bit and an exponent bit within 4 bits are retained for the local synchronization sequence and the received signal, and the original 12-bit or higher precision data is quantized and compressed, and mapped in the form of exponential power of 2, thereby simplifying the original complex multiplication operation into a simple shift operation, reducing the computational complexity and hardware storage resources, thereby reducing power consumption. Since this embodiment is aimed at 12-bit input data, the exponent bit is selected as 4 bits (2 to the fourth power is 16, 2 to the third power is 8, which is less than 12). Therefore, the length of the exponent bit here is related to the bit width of the input data. The larger the bit width of the input data, the longer the length of the exponent bit.
[0037] On this basis, the present invention further performs sparse processing on the local reference synchronization sequence to further reduce the amount of calculation. The sparse processing process of the present invention is: extracting valid points from the local sequence at a certain multiple interval in the time domain, such as extracting the local sequence every other point, which can reduce the original amount of calculation by half, thereby reducing hardware resource consumption and power consumption.
[0038] The peak value and peak position are determined based on the correlation amplitude obtained by correlation calculation. If the interval with the peak position determined to be valid last meets the set conditions, it is judged to be a valid signal.
[0039] The following uses a specific OFDM symbol as an example to illustrate the signal detection process. In this example, the OFDM symbol length is 64, the short-term training sequence STF at the signal head has a length of 4 symbols, and each symbol is added with a 1 / 4 cyclic prefix CP, so the STF is a total of 5 OFDM symbols long. According to the protocol design, the STF symbol is composed of a sequence of length 16 that is repeated after positive and negative coding of the scrambling code. The detection process of the signal detection module is as follows Figure 3As shown, firstly, the STF local reference sequence of length 16 is quantized, and the original floating point data is quantized into low-precision fixed-point data, and it is an exponential power of 2, such as quantized into 4 bits, 1 bit represents the sign bit, and 3 bits represent the exponent bit. Secondly, the local sequence of length 16 is further sparsely processed, such as retaining the data of the 2nd, 4th, 6th, 8th, 10th, 12th, 14th, and 16th in turn, and then the rest of the data is regarded as 0, thereby reducing the calculation. The local reference sequence is calculated in advance on the computer and then configured to the receiver.
[0040] The signal data received by the receiver is 12-bit signed complex IQ data. The data is compressed and quantized, retaining one sign bit and 4 exponent bits, and stored in the register array in sequence. When the received data reaches 16, 8 data are extracted in the form of local sequence sparseness, and then the correlation calculation is performed. Since the data are quantized into the form of exponential power of 2, the complex multiplication operation when the received data sequence and the local reference sequence are correlated is simplified to a simple shift operation, which greatly reduces the amount of calculation. After obtaining the calculated correlation value amplitude, it is determined whether it is a peak according to the set threshold condition, and the peak position is recorded. If the interval with the peak position of the last valid judgment meets the set conditions, such as the peak distance is in the range of 14 to 17, the signal detection is determined to be valid, and subsequent high-precision and complex signal synchronization calculations can be performed.
[0041] From the above process, it can be seen that the present invention first performs signal detection on the signal received by the wireless communication receiver to determine whether the received signal is a valid signal, and only starts signal synchronization processing when a valid signal is determined, thereby avoiding the problem of high energy consumption caused by keeping the signal synchronization module turned on all the time.
[0042] In addition, since there are other modules in the receiver, in order to further reduce power consumption, the various modules of the receiver do not need to work at the same time. When the signal detection module does not detect a signal, its subsequent modules do not work and are in a closed state. After the signal is detected, the signal synchronization module is triggered to work, and other subsequent modules do not work. When the signal synchronization is successful, the signal synchronization module starts other modules in the time domain processing module (such as the frequency offset estimation and compensation module, the cyclic prefix removal module, and the fast Fourier transform (FFT) module). The frequency domain processing module is only started after the time domain processing module is completed, and the bit domain processing module is only started after the frequency domain processing module is completed. In this way, the receiver can be guaranteed to operate with low computational complexity and low power consumption under the premise of ensuring communication performance.
[0043] Specifically, if Figure 2 As shown, the working clock of each module is switched on and off through the clock gating strategy. In the receiving state, if no signal arrives, only the signal detection module works. Figure 2The clocks of other modules in the signal processing module are gated off. When the signal detection module detects the signal, the clock of the subsequent signal synchronization module is turned on, and the clocks of other modules are still turned off. After the signal synchronization is successful, the other modules of the time domain processing module are triggered to start working and the clock gating is turned on. When the OFDM signal is processed by the time domain processing module through FFT to obtain the frequency domain data, the frequency domain module is triggered to start working and the clock gating is turned on. After the constellation demapped bit data is obtained after processing by the frequency domain processing module, the module in the bit domain is triggered to start working and the clock gating is turned on. If the signal synchronization module cannot successfully synchronize to the signal within the specified time, it is considered to be a false signal detection. At this time, the signal synchronization module is turned off, and the signal detection module continues to run, and so on. In addition, when the time domain processing module detects that the signal frame is input and the processing is completed, the source clock of the time domain processing module is turned off and no longer works. Similarly, the frequency domain processing module also turns off the frequency domain source clock and no longer works after processing a frame of frequency domain data. The bit domain processing module also turns off the source clock and no longer works after completing the bit decoding of a frame of signal.
[0044] Through the above clock gating solution, when the upstream data and conditions are not met, the clock of the corresponding downstream field remains in a closed state, and the clock of the corresponding field module itself remains in a closed state after the processing is completed, thereby greatly reducing the dynamic power consumption overhead during the idle period.
[0045] Embodiment of a signal reception control method for a wireless communication receiver
[0046] The control method of this embodiment includes the following steps: 1) performing signal detection on the received signal of the wireless communication receiver to determine whether the received signal is a valid signal; the signal detection is obtained by performing correlation calculation on the received signal and the local reference sequence. During the correlation calculation, the received signal and the local reference sequence are quantized and compressed respectively to simplify the multiplication operation during the correlation calculation into a shift operation; 2) if the detected signal is a valid signal, signal synchronization processing is performed, otherwise signal synchronization processing is not performed. The specific implementation process of this method has been described in detail in the wireless communication receiver embodiment and will not be repeated here.
Claims
1. A signal reception control method for a wireless communication receiver, characterized in that: The control method comprises the following steps: 1) Performing signal detection on the signal received by the wireless communication receiver to determine whether the received signal is a valid signal; the signal detection is obtained by performing correlation calculation on the received signal and the local reference sequence. During the correlation calculation, the received signal and the local reference sequence are quantized and compressed respectively to simplify the multiplication operation during the correlation calculation into a shift operation; 2) If the detected signal is a valid signal, signal synchronization processing is performed, otherwise signal synchronization processing is not performed.
2. The signal reception control method of a wireless communication receiver according to claim 1, characterized in that: The process of quantizing and compressing the received signal and the local reference sequence includes: The received signal and the local reference sequence are quantized respectively, and the quantized data only contains 1 sign bit and exponent bits within N bits, where N is related to the length of the received signal and the local reference sequence.
3. The signal reception control method of a wireless communication receiver according to claim 1, characterized in that: The method also includes performing sparse processing on the local reference sequence and the received signal after quantization compression processing respectively, and performing correlation calculation on the local reference sequence after sparse processing and the received signal; the sparse processing refers to extracting valid points from the quantized local reference sequence or the received signal at certain multiple intervals in the time domain.
4. The signal reception control method of a wireless communication receiver according to claim 1, characterized in that: The method for judging the effective signal is: The peak value and peak position are determined based on the correlation amplitude obtained by correlation calculation. If the interval with the peak position determined to be valid last time meets the set conditions, it is judged to be a valid signal.
5. The signal reception control method of a wireless communication receiver according to any one of claims 1 to 4, characterized in that: The method also includes other receiving processing processes in the time domain processing stage after the signal synchronization is successful, and then entering the frequency domain processing stage after obtaining the frequency domain data of the OFDM symbol in the time domain processing stage, and obtaining the constellation demapped data from the frequency domain data of the OFDM symbol in the frequency domain processing stage; After obtaining the constellation demapped data in the frequency domain processing stage, the bit domain processing stage is entered to complete the bit domain data processing in the bit domain processing stage; The time domain processing stage, the frequency domain processing stage and the bit domain processing stage are three processing stages of the signal receiving process received by the wireless communication receiver.
6. A wireless communication receiver, comprising a signal synchronization module, characterized in that: The device includes a signal detection module, which is used to detect the signal received by the wireless communication receiver and determine whether the received signal is a valid signal. If the detected signal is a valid signal, the rear signal synchronization module is started, otherwise the signal synchronization module is not started; The signal detection module is used to perform correlation calculation on the received signal and the local reference sequence, and judge whether it is a valid signal according to the correlation amplitude of the correlation calculation. During the correlation calculation, the received signal and the local reference sequence are quantized and compressed respectively to simplify the multiplication operation during the correlation calculation into a shift operation.
7. The wireless communication receiver according to claim 6, characterized in that: The process of the signal detection module quantizing and compressing the received signal and the local reference sequence includes: The received signal and the local reference sequence are quantized respectively, and the quantized data only contains 1 sign bit and exponent bits within N bits, where N is related to the length of the received signal and the local reference sequence.
8. The wireless communication receiver according to claim 6, characterized in that: The signal detection module is also used to perform sparse processing on the local reference sequence and the received signal after quantization and compression processing, and perform correlation calculation on the local reference sequence after sparse processing and the received signal; the sparse processing refers to extracting valid points from the quantized local reference sequence or the received signal at certain multiple intervals in the time domain.
9. The wireless communication receiver according to claim 6, characterized in that: The method for judging the effective signal is: The peak value and peak position are determined based on the correlation amplitude obtained by correlation calculation. If the interval with the peak position determined to be valid last time meets the set conditions, it is judged to be a valid signal.
10. The wireless communication receiver according to any one of claims 6 to 9, characterized in that: The signal synchronization module starts other parts of the time domain processing module after synchronization is successful, the frequency domain processing module is started only after the time domain processing module is finished, and the bit domain processing module is started only after the frequency domain processing module is finished; The time domain processing module, the frequency domain processing module and the bit domain processing module are modules for receiving processing in a wireless communication receiver. The time domain processing module is used to perform signal detection, signal synchronization and time-frequency conversion on the received signal; the frequency domain processing module is used to perform channel estimation and compensation, diversity combining and constellation demapping on the frequency domain signal output by the time domain processing module; and the bit domain processing module is used to decode and verify the constellation demapped data output by the frequency domain processing module.