Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device, a manufacturing method thereof and electronic equipment, and relates to but not limited to the semiconductor technology. The semiconductor device comprises a transistor and a capacitor which are arranged on a substrate; the capacitor comprises a first capacitor electrode, a capacitor dielectric layer and a second capacitor electrode, and the capacitor dielectric layer is at least arranged between the first capacitor electrode and the second capacitor electrode; the first capacitor electrode is connected with the first electrode; at least part of the first capacitor electrode is arranged on the side wall of the first electrode; therefore, the stability of the first capacitor electrode is improved.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to but are not limited to semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The present disclosure provides a semiconductor device, comprising: a substrate, a plurality of memory cells disposed on the substrate, the memory cells comprising transistors and capacitors arranged along a first direction parallel to the substrate;

[0006] The transistor comprises a channel, a gate insulating layer, a gate, a first electrode and a second electrode, wherein the gate insulating layer is arranged between the gate and the channel, and the first electrode and the second electrode are respectively connected to the channel;

[0007] The capacitor comprises a first capacitor electrode, a capacitor dielectric layer and a second capacitor electrode, wherein the capacitor dielectric layer is at least arranged between the first capacitor electrode and the second capacitor electrode; the first capacitor electrode is connected to the first electrode;

[0008] The first capacitor electrode and the first electrode connected to each other have an overlap in the first direction.

[0009] In some embodiments, the first capacitor electrode includes a main body portion and a clamping portion that are connected to each other, the clamping portion is arranged on a side of the main body portion close to the first electrode, a clamping groove is arranged in the clamping portion, an opening of the clamping groove is arranged toward the first electrode, at least a portion of the first electrode is arranged in the clamping groove, and the clamping portion and the first electrode overlap in the first direction.

[0010] In some embodiments, the clamping portion includes two clamping walls, which are parallel to the substrate and disposed on opposite sides of at least a portion of the first electrode in a direction perpendicular to the substrate.

[0011] In some embodiments, the main body portion and the clamping portion are an integrally formed structure and include the same conductive material.

[0012] In some embodiments, the material of the main body portion and the clamping portion both include titanium nitride.

[0013] In some embodiments, the main body portion has a U-shaped cross-section in a direction perpendicular to the substrate, and the main body portion includes a top wall, a bottom wall, and a side wall connecting the top wall and the bottom wall, the top wall and the bottom wall are arranged opposite to each other and are both parallel to the substrate, the side wall is perpendicular to the substrate, the side wall is connected to the clamping portion, and forms the clamping groove with the clamping portion.

[0014] In some embodiments, an insulating layer is further included, the insulating layer is located on at least one side of the first capacitor electrode in a direction perpendicular to the substrate, and the insulating layer overlaps with the orthographic projection of the clamping portion on the substrate.

[0015] In some embodiments, the insulating layer overlaps at least a portion of an orthographic projection of the body portion on the substrate.

[0016] In some embodiments, a cross-section of the first capacitor electrode in a direction perpendicular to the substrate is H-shaped.

[0017] In some embodiments, an isolation layer is disposed on the first surface of the first electrode, a portion of the first surface close to the first capacitor electrode is not disposed with the isolation layer, and at least a portion of the first capacitor electrode is disposed on the portion of the first surface.

[0018] In some embodiments, the isolation layer contacts the first electrode and the first capacitor electrode.

[0019] In some embodiments, the isolation layer and the first capacitor electrode are made of different materials.

[0020] In some embodiments, it also includes a hole perpendicular to the substrate, a portion of the first electrode is arranged in the hole, and the first capacitor electrode, the capacitor dielectric layer and the second capacitor electrode are arranged in sequence on the surface of the first electrode in the hole and on the side wall of the hole.

[0021] In some embodiments, the first capacitor electrode, the capacitor dielectric layer and the second capacitor electrode are all thin films, and the capacitor further includes a conductive filling layer, which fills the hole and is connected to the second capacitor electrode.

[0022] In some embodiments, a bit line is further included, wherein the bit line is parallel to the substrate and connected to the second electrode.

[0023] In some embodiments, a word line is further included, wherein the word line is perpendicular to the substrate and connected to the gate.

[0024] The present disclosure also provides a method for manufacturing a semiconductor device, including:

[0025] forming a stack structure including first electrodes and insulating layers alternately arranged in sequence on a substrate, wherein an isolation layer is arranged on a surface of the first electrode;

[0026] Using an etching process, a hole perpendicular to the substrate is formed in the stacked structure, wherein the hole exposes the side wall of the isolation layer and the side wall of the insulating layer;

[0027] Using an etching process, etching and removing a portion of the isolation layer in a direction parallel to the substrate to expose the first electrode;

[0028] A first capacitor electrode, a capacitor dielectric layer, and a second capacitor electrode are sequentially formed on the exposed first electrode and the sidewall of the hole to form a capacitor, and the first electrode and the capacitor are arranged along a first direction parallel to the substrate, so that the first capacitor electrode and the first electrode are interconnected and overlap in the first direction.

[0029] In some embodiments, a size of the hole portion at the location of the insulating layer in the first direction is smaller than a size of the hole portion at the location of the first electrode in the first direction.

[0030] In some embodiments, sequentially forming a first capacitor electrode, a capacitor dielectric layer, and a second capacitor electrode on the exposed first electrode and the sidewall of the hole includes:

[0031] Sequentially forming a capacitor electrode film and a barrier film on the exposed first electrode and the sidewall of the hole;

[0032] Using an etching process, etching away the blocking film at the position of the insulating layer, exposing the capacitor electrode film on the side wall of the insulating layer, retaining the blocking film at the position of the first electrode, and forming an etching blocking layer;

[0033] Using an etching process to etch away the capacitor electrode film on the side wall of the insulating layer, retaining the capacitor electrode film at the position of the first electrode, to form a first capacitor electrode;

[0034] Etching away the etching stop layer in a direction parallel to the substrate to expose the inner surface of the first capacitor electrode;

[0035] Etching and removing a portion of the insulating layer in a direction parallel to the substrate to expose at least a portion of the outer surface of the first capacitor electrode;

[0036] A capacitor dielectric layer and a second capacitor electrode are sequentially formed on the exposed inner surface of the first capacitor electrode and the exposed outer surface of the first capacitor electrode.

[0037] In some embodiments, etching and removing a portion of the insulating layer along a direction parallel to the substrate includes: etching and removing a portion of the insulating layer along the first direction, wherein a distance by which the insulating layer is etched is smaller than a length of the first capacitor electrode in the first direction.

[0038] An embodiment of the present disclosure also provides an electronic device, comprising any of the semiconductor devices described above.

[0039] The semiconductor device of the disclosed embodiment has an overlap in the first direction by the interconnected first capacitor electrode and the first electrode, so that the first capacitor electrode is pressed and fixed by the first electrode, thereby improving the stability of the connection between the first capacitor electrode and the first electrode and avoiding the collapse of the first capacitor electrode.

[0040] The semiconductor device of the disclosed embodiment clamps the first electrode through the clamping portion of the first capacitor electrode, thereby improving the stability of the connection between the first capacitor electrode and the first electrode.

[0041] The semiconductor device of the disclosed embodiment simplifies the production process and ensures the strength of the first capacitor electrode by making the main body and the clamping portion of the first capacitor electrode an integrally formed structure and including the same conductive material.

[0042] The semiconductor device of the embodiment of the present disclosure clamps the clamping portion of the first capacitor electrode through the insulating layer, thereby improving the stability of the first capacitor electrode and preventing the first capacitor electrode from collapsing.

[0043] In the semiconductor device of the disclosed embodiment, at least a portion of the first capacitor electrode is disposed on the exposed first electrode, so that the first capacitor electrode clamps the first electrode, thereby improving the stability of the connection between the first capacitor electrode and the first electrode.

[0044] The manufacturing method of the semiconductor device in the embodiment of the present disclosure removes the portion of the isolation layer exposed by the hole by etching in a direction parallel to the substrate to expose the first electrode, and then forms a first capacitor electrode on the exposed first electrode, so that at least a portion of the first capacitor electrode is arranged on the exposed first electrode, thereby improving the stability of the connection between the first capacitor electrode and the first electrode and avoiding the collapse of the first capacitor electrode.

[0045] In the method for manufacturing a semiconductor device according to an embodiment of the present disclosure, the orthographic projection of the hole corresponding to the insulating layer on the substrate is located in the orthographic projection of the hole corresponding to the first electrode on the substrate. When the blocking film on the side wall of the hole corresponding to the insulating layer is subsequently etched away, part of the blocking film can be retained in the hole corresponding to the first electrode to form an etching blocking layer.

[0046] The manufacturing method of the semiconductor device of the embodiment of the present disclosure can block the etching solution from etching the first electrode and the capacitor electrode film on the side wall of the hole corresponding to the first electrode when etching and removing the capacitor electrode film on the side wall of the insulating layer through the etching blocking layer, thereby retaining the first electrode and the capacitor electrode film on the side wall of the hole corresponding to the first electrode to form a first capacitor electrode.

[0047] The manufacturing method of the semiconductor device of the embodiment of the present disclosure removes the etch barrier layer and part of the insulating layer by etching, thereby exposing the inner surface and the outer surface of the first capacitor electrode, so that the second capacitor electrode can be arranged opposite to the exposed inner surface and the outer surface of the first capacitor electrode, thereby increasing the relative area between the second capacitor electrode and the first capacitor electrode and improving the capacitance of the capacitor.

[0048] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The objects and advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description and the drawings.

[0049] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution.

[0051] Figure 1 A schematic cross-sectional view of a semiconductor device along a direction parallel to a substrate provided in some embodiments;

[0052] Figure 2a for Figure 1 A cross-sectional view of the semiconductor device in a plane passing through line a-a' and perpendicular to the substrate;

[0053] Figure 2b for Figure 1 A cross-sectional view of the semiconductor device in a plane passing through line bb' and perpendicular to the substrate;

[0054] Figure 2c for Figure 1A cross-sectional view of the semiconductor device in a plane passing through line d-d' and perpendicular to the substrate;

[0055] Figure 3 A schematic diagram of connecting a first electrode and a first capacitor electrode in a semiconductor device provided in some embodiments;

[0056] Figure 4 A schematic structural diagram of a first capacitor electrode in a semiconductor device provided in some embodiments;

[0057] Figure 5a for Figure 1 A cross-sectional view in a plane passing through line aa' and perpendicular to the substrate after forming a first electrode, a second electrode and a hole in a manufacturing process of a semiconductor device;

[0058] Figure 5b for Figure 1 A cross-sectional view in a plane passing through line bb' and perpendicular to the substrate after forming a first electrode, a second electrode and a hole in a manufacturing process of a semiconductor device;

[0059] Figure 5c for Figure 1 A cross-sectional view in a plane passing through line c-c' and perpendicular to the substrate after forming a first electrode, a second electrode and a hole in a manufacturing process of a semiconductor device;

[0060] Figure 5d for Figure 1 A cross-sectional view in a plane passing through the d-d' line and perpendicular to the substrate after forming a first electrode, a second electrode and a hole in a manufacturing process of a semiconductor device;

[0061] Figure 6 for Figure 1 A cross-sectional view in a plane passing through line aa' and perpendicular to the substrate after one end of the first electrode is exposed during the manufacturing process of the semiconductor device;

[0062] Figure 7a for Figure 1 A cross-sectional view in a plane passing through line aa' and perpendicular to the substrate after a capacitor electrode film and a barrier film are formed during the manufacturing process of a semiconductor device;

[0063] Figure 7b for Figure 1 A cross-sectional view in a plane passing through the d-d' line and perpendicular to the substrate after a capacitor electrode film and a barrier film are formed during the manufacturing process of a semiconductor device;

[0064] Figure 8a for Figure 1 A cross-sectional view in a plane passing through line aa' and perpendicular to the substrate after an etching stop layer is formed during the manufacturing process of a semiconductor device;

[0065] Figure 8b for Figure 1 A cross-sectional view in a plane passing through line d-d' and perpendicular to the substrate after an etching stop layer is formed during the manufacturing process of a semiconductor device;

[0066] Figure 9a for Figure 1 A cross-sectional view in a plane passing through line aa' and perpendicular to the substrate after a first capacitor electrode is formed during the manufacturing process of the semiconductor device;

[0067] Figure 9b for Figure 1 A cross-sectional view in a plane passing through line d-d' and perpendicular to the substrate after a first capacitor electrode is formed during the manufacturing process of the semiconductor device;

[0068] Fig.10a for Figure 1 A cross-sectional view in a plane passing through line aa' and perpendicular to the substrate after the inner surface of the first capacitor electrode is exposed during the manufacturing process of the semiconductor device;

[0069] Fig.10b for Figure 1 A cross-sectional view in a plane passing through line d-d' and perpendicular to the substrate after the inner surface of the first capacitor electrode is exposed during the manufacturing process of the semiconductor device;

[0070] Fig.11a for Figure 1 A cross-sectional view in a plane passing through line aa' and perpendicular to the substrate after the outer surface of the first capacitor electrode is exposed during the manufacturing process of the semiconductor device;

[0071] Fig.11b for Figure 1 A cross-sectional view in a plane passing through line d-d' and perpendicular to the substrate after the outer surface of the first capacitor electrode is exposed during the manufacturing process of the semiconductor device. DETAILED DESCRIPTION

[0072] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other arbitrarily.

[0073] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the common meanings understood by one of ordinary skill in the art to which the present invention belongs.

[0074] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0075] The ordinal numbers such as “first”, “second” and “third” in the present disclosure are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0076] In the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the present specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the disclosure and can be appropriately replaced according to the circumstances.

[0077] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0078] In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region where current mainly flows.

[0079] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" may be interchanged.

[0080] In the present disclosure, "electrical connection" includes the case where components are connected together through an element having some kind of electrical function. There is no particular limitation on the "element having some kind of electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some kind of electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0081] In the present disclosure, "parallel" means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.

[0082] In the present disclosure, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film" in some cases. Similarly, "insulating film" may be replaced with "insulating layer" in some cases.

[0083] The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process. "The orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0084] In the embodiments of the present disclosure, "A and B are an integrated structure" may mean that there is no obvious boundary interface such as a fault or gap in the microstructure. Generally, a film layer patterned to form a connection is an integrated structure. For example, A and B use the same material to form a film layer and form a structure with a connection relationship at the same time through the same patterning process.

[0085] The present disclosure provides a semiconductor device, comprising: a substrate, a plurality of memory cells disposed on the substrate, the memory cells comprising transistors and capacitors arranged along a first direction parallel to the substrate;

[0086] The transistor comprises a channel, a gate insulating layer, a gate, a first electrode and a second electrode, the channel surrounds the gate, the gate insulating layer is arranged between the gate and the channel, and the first electrode and the second electrode are respectively connected to the channel;

[0087] The capacitor comprises a first capacitor electrode, a capacitor dielectric layer and a second capacitor electrode, wherein the capacitor dielectric layer is at least arranged between the first capacitor electrode and the second capacitor electrode; the first capacitor electrode is connected to the first electrode;

[0088] The first capacitor electrode and the first electrode connected to each other have an overlap in the first direction.

[0089] In some embodiments, the first capacitor electrode includes a main body portion and a clamping portion that are connected to each other, the clamping portion is arranged on a side of the main body portion close to the first electrode, a clamping groove is arranged in the clamping portion, an opening of the clamping groove is arranged toward the first electrode, at least a portion of the first electrode is arranged in the clamping groove, and the clamping portion and the first electrode overlap in the first direction.

[0090] The semiconductor device disclosed in the present invention is described below by way of some exemplary embodiments.

[0091] Figure 1 A schematic cross-sectional view of a semiconductor device provided in some embodiments along a direction parallel to the substrate. Figure 1 As shown, the semiconductor device may include: a word line, a bit line 3, a transistor 1 and a capacitor 2 arranged on a substrate. In one embodiment, a semiconductor device containing only a transistor 1 and a capacitor 2 forms a 1T1C structure. The first electrode of the transistor 1 is connected to the first capacitor electrode of the capacitor 2, and the second electrode of the transistor 1 is connected to the bit line 3; the word line is connected to the gate of the transistor 1; and the bit line 3 is connected to the second electrode of the transistor 1. The capacitor in this application can be understood as a capacitor.

[0092] In some embodiments, the transistor 1 may include a channel 23, a gate insulating layer 24, a gate 25, a first electrode, and a second electrode. The gate 25 may be perpendicular to the substrate, the gate insulating layer 24 is disposed between the gate 25 and the channel 23, the channel 23 surrounds the sidewall of the gate 25 through the gate insulating layer 24, and the first electrode and the second electrode are connected to the channel, respectively. Figure 1 The first electrode and the second electrode are not shown. The channel surrounding the sidewall of the gate includes at least one of the following: the channel completely surrounds the gate, the channel partially surrounds the gate, and the channel is arranged on one side of the gate.

[0093] In some embodiments, the gate and the word line are an integrated structure.

[0094] In some embodiments, the channel surrounds the gate, and the channel extends along the sidewall of the gate to form a ring extending in a direction perpendicular to the substrate. The film thickness direction of the channel is parallel to the substrate.

[0095] Wherein, the channel surrounding the gate can be understood as the channel partially or completely surrounding the gate. In some embodiments, the surrounding can be completely surrounded as a whole, and the cross section of the channel after the surrounding is a closed ring. The interception direction of the cross section is intercepted along the direction parallel to the substrate. In some embodiments, the surrounding can be partially surrounded, and the cross section after the surrounding is not closed, but presents a ring shape. For example, a ring with an opening.

[0096] In some embodiments, a word line may be perpendicular to the substrate and connected to gates of a plurality of transistors stacked along a direction perpendicular to the substrate, and the plurality of transistors may share the word line.

[0097] In some embodiments, the bit line may be parallel to the substrate and extend along the second direction D2. The bit line is connected to the second electrode of the transistor located in the same layer, and the transistors in the same layer may share the bit line. The second direction D2 intersects the first direction D1. For example, the second direction D2 is perpendicular to the first direction D1.

[0098] In some embodiments, the capacitor 2 includes a first capacitor electrode 71, a second capacitor electrode 72, and a capacitor dielectric layer 73, wherein the first capacitor electrode 71 is connected to the first electrode. The capacitor dielectric layer 73 is at least disposed between the first capacitor electrode 71 and the second capacitor electrode 72. At least a portion of the second capacitor electrode 72 is disposed on a side wall of the first capacitor electrode 71 through the capacitor dielectric layer 73.

[0099] In some embodiments, the first capacitor electrode 71, the second capacitor electrode 72 and the capacitor dielectric layer 73 are all thin films, the capacitor 2 also includes a conductive filling layer 74, the second capacitor electrode 72 is arranged on the side wall of the conductive filling layer 74, and the first capacitor electrode 71 is arranged on the second capacitor electrode 72 through the capacitor dielectric layer 73.

[0100] In some embodiments, the materials of the first capacitor electrode 71 and the second capacitor electrode 72 can both be titanium nitride.

[0101] In some embodiments, the conductive filling layer 74 may be made of germanium-doped polysilicon.

[0102] Figure 2a for Figure 1 A cross-sectional view of the semiconductor device in a plane passing through line a-a' and perpendicular to the substrate; Figure 2b for Figure 1 3c is a cross-sectional view of the semiconductor device in a plane passing through line bb' and perpendicular to the substrate; ... Figure 1 A cross-sectional view of a semiconductor device in a plane passing through line d-d' and perpendicular to the substrate. Figure 2a , Figure 2b and Figure 2cAs shown, the first electrode 21 and the second electrode 22 are respectively located on opposite sides of the channel in a direction parallel to the substrate 101, and are connected through the channel. The first electrode 21 is located on the side of the channel close to the capacitor, the first end of the first electrode 21 is connected to the first capacitor electrode 71 of the capacitor, and the second end of the first electrode 21 is connected to the channel. The second electrode 22 is located on the side of the channel away from the capacitor, the first end of the second electrode 22 is connected to the channel, and the second end of the second electrode 22 is connected to the bit line. Wherein, the channel between the first electrode and the second electrode is a horizontal channel.

[0103] In some embodiments, the word line 2 may be perpendicular to the substrate and connected to gates of a plurality of transistors stacked along a direction perpendicular to the substrate, and the plurality of transistors may share the word line.

[0104] In some embodiments, the semiconductor device of the present embodiment further includes a hole K extending in a direction perpendicular to the substrate, the sidewall of the hole K exposes the first end of the first electrode 21, a portion of the first electrode 21 is disposed in the hole K, the first capacitor electrode 71, the capacitor dielectric layer 73, and the second capacitor electrode 72 can be sequentially disposed on the surface of the first electrode 21 in the hole K and on the sidewall of the hole K by an atomic deposition process, and the conductive filling layer 74 fills the hole K. Among them, the hole K exposes the first end of the first electrode 21, and the first capacitor electrode 71 on the sidewall of the hole K is disposed on the exposed first electrode 21, so that the first capacitor electrode 71 clamps the first end of the exposed first electrode 21.

[0105] Figure 3 A schematic diagram of connecting a first electrode to a first capacitor electrode in a semiconductor device provided in some embodiments. Figure 3 As shown, the first capacitor electrode 71 and the first electrode 21 connected to each other overlap in the first direction D1 parallel to the substrate, so that at least part of the first capacitor electrode 71 is arranged on the side wall of the first electrode 21. Among them, at least part of the first capacitor electrode 71 is arranged on the opposite sides of the first electrode 21 in the direction perpendicular to the substrate, so that the first capacitor electrode 71 can clamp the first electrode 21.

[0106] In some embodiments, the first capacitor electrode may contact only the upper surface, the lower surface, or one of the two side surfaces of the first electrode, or may contact two, three, or four of the upper surface, the lower surface, or the two side surfaces of the first electrode.

[0107] In the semiconductor device of the disclosed embodiment, the first capacitor electrode is disposed on the first electrode, so that the first capacitor electrode can clamp the first electrode, thereby improving the stability of the connection between the first capacitor electrode and the first electrode and preventing the first capacitor electrode from collapsing.

[0108] In some embodiments, an isolation layer 211 is disposed on the first surface of the first electrode 21, and the isolation layer 211 is not disposed on a portion of the first surface close to the first capacitor electrode 71, and at least a portion of the first capacitor electrode 71 is disposed on the portion of the first surface, and an end of the isolation layer 211 close to the first capacitor electrode 71 exposes the first electrode 21, that is, an end of the first electrode 21 close to the first capacitor electrode 71 is not wrapped by the isolation layer 211. An end of the isolation layer 211 close to the first capacitor electrode 71 is connected to the first capacitor electrode 71. At least a portion of the first capacitor electrode 71 is disposed on the exposed first electrode 21.

[0109] In the semiconductor device of the disclosed embodiment, at least a portion of the first capacitor electrode is disposed on the exposed first electrode, so that the first capacitor electrode clamps the first electrode, thereby improving the stability of the connection between the first capacitor electrode and the first electrode.

[0110] In some embodiments, one end of the isolation layer 211 close to the first capacitor electrode 71 is connected to one end of the first capacitor electrode 71 close to the isolation layer 211 , and the orthographic projections of the isolation layer 211 and the corresponding first capacitor electrode 71 on the substrate do not overlap.

[0111] In some embodiments, the isolation layer 211 is in contact with both the first electrode 21 and the first capacitor electrode 71 .

[0112] In some embodiments, the material of the isolation layer 211 and the first capacitor electrode 71 may be the same or different. For example, the isolation layer may be made of copper, ITO, IZO, etc., which may reduce the contact resistance between the first electrode and the first capacitor electrode. In some embodiments, the material of the isolation layer 211 may be titanium nitride.

[0113] In some embodiments, the material of the first electrode 21 may include metal tungsten.

[0114] Figure 4 A schematic diagram of the structure of a first capacitor electrode in a semiconductor device provided in some embodiments. Figure 3 and Figure 4As shown, the first capacitor electrode 71 includes a main body portion 711 and a clamping portion 712 connected to each other. The clamping portion 712 is arranged on a side of the main body portion 711 close to the first electrode 21. The clamping portion 712 overlaps with the first electrode 21 in a first direction D1 parallel to the substrate. A clamping groove 713 is arranged in the clamping portion 712. The opening of the clamping groove 713 is arranged toward the first electrode 21. The end of the first electrode 21 close to the first capacitor electrode 71 extends into the clamping groove 713 through the opening of the clamping groove 713, so that the end of the first electrode 21 close to the first capacitor electrode 71 is arranged in the clamping groove 713. The clamping portion 713 is arranged on the end of the first electrode 21 close to the first capacitor electrode 71, so that the clamping portion 713 clamps the first electrode 21, thereby improving the stability of the connection between the first capacitor electrode 71 and the first electrode 21.

[0115] In some embodiments, the clamping portion 712 includes two clamping walls, which are parallel to the substrate and are disposed on opposite sides of at least a portion of the first electrode 21 in a direction perpendicular to the substrate. The first ends of the two clamping walls are connected to the main body 711, and the second ends of the two clamping walls are connected to the end of the isolation layer 211.

[0116] In some embodiments, the end of the first electrode 21 exposed by the isolation layer 211 is arranged in the clamping groove 713, so that the two clamping walls are arranged on the end of the first electrode 21 exposed by the isolation layer 211 and are located on opposite sides of the exposed first electrode 21 in a direction perpendicular to the substrate.

[0117] In some embodiments, the two clamping walls and the isolation layer 211 are located in the same film layer. The two clamping walls and the isolation layer 211 are made of the same material, for example, the two clamping walls and the isolation layer 211 may both include titanium nitride.

[0118] In some embodiments, the cross section of the main body 711 in a direction perpendicular to the substrate is U-shaped. The main body 711 includes a top wall 7111, a bottom wall 7112, and a side wall 7113 connecting the top wall 7111 and the bottom wall 7112. The top wall 7111 and the bottom wall 7112 are arranged opposite to each other and are parallel to the substrate, the side wall 7113 is perpendicular to the substrate, and the side wall 7113 is located on a side of the top wall 7111 and the bottom wall 7112 close to the first electrode 21. The side of the side wall 7113 away from the top wall 7111 and the bottom wall 7112 is connected to the first ends of the two clamping walls, and the side wall 7113 and the two clamping walls form the clamping groove 713.

[0119] In some embodiments, at least a portion of the second capacitor electrode is arranged on the inner and outer surfaces of the top wall 7111, the inner and outer surfaces of the bottom wall 7112, and the inner surface of the side wall 7113 through the capacitor dielectric layer, thereby increasing the relative area between the second capacitor electrode and the first capacitor electrode and improving the capacitance of the capacitor.

[0120] In some embodiments, the first capacitor electrode 71 formed by the main portion 711 and the clamping portion 712 has an H-shaped cross section perpendicular to the substrate direction.

[0121] In some embodiments, the main body 711 and the clamping portion 712 are integrally formed and include the same conductive material. For example, the main body 711 and the clamping portion 712 may both include titanium nitride.

[0122] The semiconductor device of the disclosed embodiment simplifies the production process and ensures the strength of the first capacitor electrode by making the main body and the clamping portion of the first capacitor electrode an integrally formed structure and including the same conductive material.

[0123] In some embodiments, Figure 2a As shown, the semiconductor device of the embodiment of the present application further includes an insulating layer 41. In the direction perpendicular to the substrate, the insulating layer 41 is disposed between adjacent first electrodes 21 to separate adjacent first electrodes 21. The insulating layer 41 is located on at least one side of the first capacitor electrode 71 in the direction perpendicular to the substrate, the insulating layer 41 overlaps with the orthographic projection of the clamping portion 712 on the substrate, and the insulating layer 41 overlaps with the orthographic projection of at least part of the main body portion 711 on the substrate, so that the insulating layer 41 can clamp the first capacitor electrode 71 and provide support for the first capacitor electrode 71.

[0124] The semiconductor device of the embodiment of the present disclosure clamps the clamping portion of the first capacitor electrode through the insulating layer, thereby improving the stability of the first capacitor electrode and preventing the first capacitor electrode from collapsing.

[0125] In some embodiments, a capacitor dielectric layer 73 and a second capacitor electrode 72 are sequentially disposed on an end surface of the insulating layer 41 close to one end of the capacitor.

[0126] In some embodiments, a groove is formed between the end surface of the insulating layer 41 close to one end of the capacitor and the adjacent first capacitor electrode 71 , and the capacitor dielectric layer 73 and the second capacitor electrode 72 are sequentially arranged on the inner wall of the groove.

[0127] In some embodiments, in a direction perpendicular to the substrate, the second capacitor electrodes 72 of the capacitors in the same column of different layers may be connected into an integrated structure, that is, the capacitors in the same column of different layers share the same second capacitor electrode 72 .

[0128] In some embodiments, in the direction perpendicular to the substrate, the capacitor dielectric layers 73 of the capacitors in the same column of different layers may be connected into an integrated structure, that is, the capacitors in the same column of different layers share the same capacitor dielectric layer 73. The capacitors in the same column of different layers refer to capacitors located in different film layers stacked along a direction perpendicular to the substrate and arranged along a direction perpendicular to the substrate.

[0129] The technical solution of this embodiment is further explained below through the manufacturing process of the semiconductor device of this embodiment. The "patterning process" mentioned in this embodiment includes deposition of film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this embodiment includes coating of film layer, mask exposure and development, which are mature manufacturing processes in related technologies. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here. In the description of this embodiment, it should be understood that "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or a photolithography process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" still requires a patterning process or a photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".

[0130] In some embodiments, the semiconductor device may be any of the semiconductor devices described above, and the manufacturing process of the semiconductor device may include:

[0131] Step 101, forming a first electrode, a second electrode and a hole.

[0132] The formation of the first electrode, the second electrode and the hole comprises: forming a stacking structure including insulating sacrificial layers and insulating layers 41 alternately arranged in sequence on the substrate 101; then, patterning and etching the stacking structure through a mask to form a plurality of grooves perpendicular to the substrate, wherein each layer of the insulating layers 41 respectively forms a first patterned structure stacked on each other and distributed cyclically in sequence, and each layer of the insulating sacrificial layers respectively forms a second patterned structure stacked on each other and distributed cyclically in sequence; then, etching the stacking structure through a dry etching process to form a plurality of through holes penetrating the plurality of insulating sacrificial layers and the plurality of insulating layers 41, wherein the side walls of the through holes expose the side walls of each insulating sacrificial layer and the insulating layer 41; then, removing at least a portion of each insulating sacrificial layer by lateral etching of the through holes, and removing the region where each insulating sacrificial layer is etched away A first electrode 21 and a second electrode 22 are formed on opposite sides of the through hole in a direction parallel to the substrate, and an isolation layer is provided on the surface of the first electrode 21 and the second electrode 22, and the isolation layer on the side wall of the first electrode 21 and the second electrode 22 is exposed by the through hole; then, a sacrificial layer 43 is formed in a plurality of through holes, and the sacrificial layer 43 fills the plurality of through holes; then, a barrier layer 44 is formed on the above stacked structure, and the material of the barrier layer 44 can be silicon nitride; finally, the stacked structure is etched by a dry etching process to form a hole K penetrating the barrier layer 44, a plurality of the insulating sacrificial layers and a plurality of the insulating layers 41, the hole K extends in a direction perpendicular to the substrate, and the hole K does not overlap with the orthographic projection of the sacrificial layer 43 on the substrate 101, and the hole K exposes the side wall of the isolation layer 211 and the side wall of the insulating layer 41, as shown in FIG. Figure 5a , Figure 5b , Figure 5c and Figure 5d shown.

[0133] In some embodiments, the size of the hole K portion at the position of the insulating layer 41 in the first direction D1 parallel to the substrate is smaller than the size of the hole K portion at the position of the first electrode 21 in the first direction D1, the area of ​​the orthographic projection of the hole K portion at the position of the insulating layer 41 on the substrate 101 is smaller than the area of ​​the orthographic projection of the hole K portion at the position of the first electrode 21 on the substrate, the side wall of the hole K corresponding to the insulating layer 41 and the side wall of the hole K corresponding to the first electrode 21 form a step shape, the first electrode 21 and the adjacent insulating layer 41 form a first groove, and the first groove is parallel to the substrate.

[0134] In some embodiments, in subsequent processes, the sacrificial layer 43 may be removed, and a semiconductor layer, a gate insulating layer, and a gate may be sequentially formed on the sidewalls of the through hole.

[0135] In some embodiments, the insulating layer and the insulating sacrificial layer may be deposited using a chemical vapor deposition method.

[0136] In some embodiments, the substrate may be a semiconductor substrate, such as a silicon substrate. Of course, it may be any substrate that plays a supporting role, not just a base, but may be a substrate formed by peripheral circuits on the substrate.

[0137] In some embodiments, the insulating layer serves to isolate the devices and may be a low-K dielectric layer, i.e., a dielectric layer with a dielectric constant K < 3.9, including but not limited to silicon oxides, such as silicon dioxide (SiO 2 )wait.

[0138] Step 102: exposing one end of the first electrode.

[0139] Exposing one end of the first electrode includes: on the basis of the substrate formed with the aforementioned pattern, using an etching process, etching away the isolation layer 211 of the first electrode 21 exposed by the hole K in a direction parallel to the substrate 101, exposing one end of the first electrode 21, for example, etching away the isolation layer 211, exposing the end surface, the upper surface and the lower surface of one end of the first electrode 21, the upper surface and the lower surface being two opposite surfaces of one end of the first electrode 21 on the vertical substrate 101, such as Figure 6 shown.

[0140] Step 103, forming a capacitor electrode film and a barrier film.

[0141] The formation of the capacitor electrode film and the barrier film includes: on the basis of the substrate formed with the aforementioned pattern, using an atomic deposition process, sequentially forming a capacitor electrode film 70 and a barrier film 60 on the exposed first electrode and the sidewall of the hole K, wherein the barrier film 60 covers the capacitor electrode film 70, the barrier film 60 fills a first groove formed by the first electrode 21 and the adjacent insulating layer 41, and the barrier film 60 does not completely fill the hole K, and the barrier film 60 forms a second groove in the hole, the second groove being perpendicular to the substrate 101, such as Figure 7a and Figure 7b shown.

[0142] Step 104: forming an etching stop layer.

[0143] The etching stop layer is formed by: on the basis of the substrate formed with the aforementioned pattern, using a wet etching process to etch away the blocking film at the position of the insulating layer 41, exposing the capacitor electrode film 70 on the side wall of the insulating layer 41, retaining the blocking film at the position of the first electrode 21, forming an etching stop layer 61, and the etching stop layer 61 fills the first groove formed by the first electrode 21 and the adjacent insulating layer 41, such as Figure 8a and Figure 8b shown.

[0144] Step 105: forming a first capacitor electrode.

[0145] The first capacitor electrode is formed by: on the basis of the substrate formed with the aforementioned pattern, a wet etching process is used to etch away the capacitor electrode film on the side wall of the insulating layer 41, so that the capacitor electrode films on the inner walls of adjacent first grooves are disconnected from each other; the etching stopper layer 61 can block the etching liquid from etching the capacitor electrode film at the position of the first electrode and on the side wall of the hole corresponding to the first electrode, so that the retained capacitor electrode film forms the first capacitor electrode 71, such as Figure 9a and Figure 9b shown.

[0146] Step 106: exposing the inner surface of the first capacitor electrode.

[0147] Exposing the first capacitor electrode includes: on the basis of the substrate formed with the aforementioned pattern, using a wet etching process to remove the etching barrier layer in a direction parallel to the substrate, so as to expose the inner surface of the first capacitor electrode 71. Fig.10a and Fig.10b shown.

[0148] Step 107: exposing the outer surface of the first capacitor electrode.

[0149] Exposing the outer surface of the first capacitor electrode includes: on the basis of the substrate formed with the aforementioned pattern, using a wet etching process to etch away a portion of the insulating layer 41 in a direction parallel to the substrate, so as to expose at least a portion of the outer surface of the first capacitor electrode 71. Fig.11a and Fig.11b shown.

[0150] In some embodiments, a portion of the insulating layer 41 is etched away along the first direction D1 , and the etched distance of the insulating layer 41 is smaller than the length of the first capacitor electrode in the first direction D1 .

[0151] Step 108: forming a capacitor dielectric layer and a second capacitor electrode.

[0152] The formation of the capacitor dielectric layer and the second capacitor electrode comprises: on the basis of the substrate formed with the aforementioned pattern, using an atomic deposition process to sequentially form a capacitor dielectric layer 73 and a second capacitor electrode 72 on the inner surface and the outer surface of the exposed first capacitor electrode 71; then, using a chemical deposition process to form a conductive filling layer 74 filling the hole K, grinding the conductive filling layer 74, such as Figure 2a , Figure 2b and Figure 2c shown.

[0153] In some embodiments, the capacitor dielectric layer 73 may be made of a high-K dielectric material, that is, a dielectric material with a dielectric constant K ≥ 3.9. The high-K dielectric material may include but is not limited to at least one of the following: silicon oxide, aluminum oxide (Al 2 O 3 ), hafnium oxide.

[0154] In some embodiments, the second capacitor electrode 72 may be made of titanium nitride.

[0155] In some embodiments, the conductive filling layer 74 may be made of germanium-doped polysilicon.

[0156] Step 109 , forming a channel, a gate insulating layer and a gate.

[0157] The forming of the channel, the gate insulating layer and the gate comprises: on the basis of the substrate formed with the aforementioned pattern, removing the sacrificial layer, and sequentially forming the channel, the gate insulating layer and the gate on the inner wall of the through hole.

[0158] The solution provided in this embodiment simplifies the process flow, is easy to implement, improves production efficiency, and has the advantages of easy process implementation, low production cost, and high yield rate.

[0159] The present disclosure also provides a method for manufacturing a semiconductor device, including:

[0160] forming a stack structure including first electrodes and insulating layers alternately arranged in sequence on a substrate, wherein an isolation layer is arranged on a surface of the first electrode;

[0161] Using an etching process, a hole perpendicular to the substrate is formed in the stacked structure, wherein the hole exposes the side wall of the isolation layer and the side wall of the insulating layer;

[0162] Using an etching process, etching and removing a portion of the isolation layer in a direction parallel to the substrate to expose the first electrode;

[0163] A first capacitor electrode, a capacitor dielectric layer, and a second capacitor electrode are sequentially formed on the exposed first electrode and the sidewall of the hole to form a capacitor, and the first electrode and the capacitor are arranged along a first direction parallel to the substrate, so that the first capacitor electrode and the first electrode are interconnected and overlap in the first direction.

[0164] In some embodiments, a size of the hole portion at the location of the insulating layer in the first direction is smaller than a size of the hole portion at the location of the first electrode in the first direction.

[0165] In some embodiments, sequentially forming a first capacitor electrode, a capacitor dielectric layer, and a second capacitor electrode on the exposed first electrode and the sidewall of the hole includes:

[0166] Sequentially forming a capacitor electrode film and a barrier film on the exposed first electrode and the sidewall of the hole;

[0167] Using an etching process, etching away the blocking film at the position of the insulating layer, exposing the capacitor electrode film on the side wall of the insulating layer, retaining the blocking film at the position of the first electrode, and forming an etching blocking layer;

[0168] Using an etching process to etch away the capacitor electrode film on the side wall of the insulating layer, retaining the capacitor electrode film at the position of the first electrode, to form a first capacitor electrode;

[0169] Etching away the etching stop layer in a direction parallel to the substrate to expose the inner surface of the first capacitor electrode;

[0170] Etching and removing a portion of the insulating layer in a direction parallel to the substrate to expose at least a portion of the outer surface of the first capacitor electrode;

[0171] A capacitor dielectric layer and a second capacitor electrode are sequentially formed on the exposed inner surface of the first capacitor electrode and the exposed outer surface of the first capacitor electrode.

[0172] In some embodiments, etching and removing a portion of the insulating layer along a direction parallel to the substrate includes: etching and removing a portion of the insulating layer along the first direction, wherein a distance by which the insulating layer is etched is smaller than a length of the first capacitor electrode in the first direction.

[0173] The manufacturing method of the semiconductor device in the embodiment of the present disclosure removes the portion of the isolation layer exposed by the hole by etching in a direction parallel to the substrate to expose the first electrode, and then forms a first capacitor electrode on the exposed first electrode, so that at least a portion of the first capacitor electrode is arranged on the exposed first electrode, thereby improving the stability of the connection between the first capacitor electrode and the first electrode and avoiding the collapse of the first capacitor electrode.

[0174] The manufacturing method of the semiconductor device of the embodiment of the present disclosure makes the size of the hole portion at the location of the insulating layer in the first direction smaller than the size of the hole portion at the location of the first electrode in the first direction. When the blocking film at the location of the insulating layer is subsequently etched away, part of the blocking film at the location of the first electrode can be retained to form an etching blocking layer.

[0175] The manufacturing method of the semiconductor device of the embodiment of the present disclosure can block the etching solution from etching the first electrode and the capacitor electrode film at the position of the first electrode when etching and removing the capacitor electrode film at the position of the insulating layer through the etching blocking layer, thereby retaining the first electrode and the capacitor electrode film at the position of the first electrode to form a first capacitor electrode.

[0176] The manufacturing method of the semiconductor device of the embodiment of the present disclosure removes the etch barrier layer and part of the insulating layer by etching, thereby exposing the inner surface and the outer surface of the first capacitor electrode, so that the second capacitor electrode can be arranged opposite to the exposed inner surface and the outer surface of the first capacitor electrode, thereby increasing the relative area between the second capacitor electrode and the first capacitor electrode and improving the capacitance of the capacitor.

[0177] The present disclosure also provides an electronic device, including the semiconductor device described in any of the above embodiments. The electronic device may be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply. The storage device may include a memory in a computer, etc., which is not limited here.

[0178] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted to facilitate understanding of the present invention and are not intended to limit the present invention. Any technician in the field to which the present invention belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present invention, but the patent protection scope of the present invention shall still be subject to the scope defined in the attached claims.

Claims

1. A semiconductor device, characterized in that: include: A substrate, and a plurality of memory cells disposed on the substrate, wherein the memory cells include transistors and capacitors arranged along a first direction parallel to the substrate; The transistor comprises a channel, a gate insulating layer, a gate, a first electrode and a second electrode, wherein the gate insulating layer is arranged between the gate and the channel, and the first electrode and the second electrode are respectively connected to the channel; The capacitor comprises a first capacitor electrode, a capacitor dielectric layer and a second capacitor electrode, wherein the capacitor dielectric layer is at least arranged between the first capacitor electrode and the second capacitor electrode; the first capacitor electrode is connected to the first electrode; The first capacitor electrode and the first electrode connected to each other have an overlap in the first direction.

2. The semiconductor device according to claim 1, wherein: The first capacitor electrode includes a main body portion and a clamping portion that are connected to each other. The clamping portion is arranged on a side of the main body portion close to the first electrode. A clamping groove is arranged in the clamping portion. The opening of the clamping groove is arranged toward the first electrode. At least a portion of the first electrode is arranged in the clamping groove. The clamping portion and the first electrode overlap in the first direction.

3. The semiconductor device according to claim 2, characterized in that The clamping portion includes two clamping walls, which are parallel to the substrate and are arranged on opposite sides of at least a portion of the first electrode in a direction perpendicular to the substrate.

4. The semiconductor device according to claim 2, characterized in that The main body and the clamping portion are an integrally formed structure and comprise the same conductive material.

5. The semiconductor device according to claim 4, characterized in that The materials of the main body portion and the clamping portion both include titanium nitride.

6. The semiconductor device according to claim 2, wherein: The main body portion has a U-shaped cross-section in a direction perpendicular to the substrate, and includes a top wall, a bottom wall, and a side wall connecting the top wall and the bottom wall. The top wall and the bottom wall are arranged opposite to each other and are both parallel to the substrate. The side wall is perpendicular to the substrate, and the side wall is connected to the clamping portion and forms the clamping groove with the clamping portion.

7. The semiconductor device according to claim 2, characterized in that It also includes an insulating layer, which is located on at least one side of the first capacitor electrode in a direction perpendicular to the substrate, and the insulating layer overlaps with the orthographic projection of the clamping portion on the substrate.

8. The semiconductor device according to claim 7, characterized in that The insulating layer overlaps at least a portion of an orthographic projection of the body portion on the substrate.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that: The cross section of the first capacitor electrode in a direction perpendicular to the substrate is H-shaped.

10. The semiconductor device according to any one of claims 1 to 8, characterized in that: An isolation layer is disposed on the first surface of the first electrode, a portion of the first surface close to the first capacitor electrode is not disposed with the isolation layer, and at least a portion of the first capacitor electrode is disposed on the portion of the first surface.

11. The semiconductor device according to claim 10, characterized in that The isolation layer contacts the first electrode and the first capacitor electrode.

12. The semiconductor device according to claim 10, characterized in that The isolation layer and the first capacitor electrode are made of different materials.

13. The semiconductor device according to any one of claims 1 to 8, characterized in that: It also includes a hole perpendicular to the substrate, a portion of the first electrode is arranged in the hole, and the first capacitor electrode, the capacitor dielectric layer and the second capacitor electrode are arranged in sequence on the surface of the first electrode in the hole and on the side wall of the hole.

14. The semiconductor device according to claim 13, characterized in that The first capacitor electrode, the capacitor dielectric layer and the second capacitor electrode are all thin films. The capacitor further includes a conductive filling layer, which fills the hole and is connected to the second capacitor electrode.

15. The semiconductor device according to any one of claims 1 to 8, characterized in that: The device also includes a bit line, wherein the bit line is parallel to the substrate and connected to the second electrode.

16. The semiconductor device according to any one of claims 1 to 8, characterized in that: The invention also includes a word line, wherein the word line is perpendicular to the substrate and connected to the gate.

17. A method for manufacturing a semiconductor device, characterized in that: include: forming a stack structure including first electrodes and insulating layers alternately arranged in sequence on a substrate, wherein an isolation layer is arranged on a surface of the first electrode; Using an etching process, a hole perpendicular to the substrate is formed in the stacked structure, wherein the hole exposes the side wall of the isolation layer and the side wall of the insulating layer; Using an etching process, etching and removing a portion of the isolation layer in a direction parallel to the substrate to expose the first electrode; A first capacitor electrode, a capacitor dielectric layer, and a second capacitor electrode are sequentially formed on the exposed first electrode and the sidewall of the hole to form a capacitor, and the first electrode and the capacitor are arranged along a first direction parallel to the substrate, so that the first capacitor electrode and the first electrode are interconnected and overlap in the first direction.

18. The method for manufacturing a semiconductor device according to claim 17, wherein: The size of the hole portion at the location of the insulating layer in the first direction is smaller than the size of the hole portion at the location of the first electrode in the first direction.

19. The method for manufacturing a semiconductor device according to claim 18, wherein: Sequentially forming a first capacitor electrode, a capacitor dielectric layer, and a second capacitor electrode on the exposed first electrode and the sidewall of the hole comprises: Sequentially forming a capacitor electrode film and a barrier film on the exposed first electrode and the sidewall of the hole; Using an etching process, etching away the blocking film at the position of the insulating layer, exposing the capacitor electrode film on the side wall of the insulating layer, retaining the blocking film at the position of the first electrode, and forming an etching blocking layer; Using an etching process to etch away the capacitor electrode film on the side wall of the insulating layer, retaining the capacitor electrode film at the position of the first electrode, to form a first capacitor electrode; Etching away the etching stop layer in a direction parallel to the substrate to expose the inner surface of the first capacitor electrode; Etching and removing a portion of the insulating layer in a direction parallel to the substrate to expose at least a portion of the outer surface of the first capacitor electrode; A capacitor dielectric layer and a second capacitor electrode are sequentially formed on the exposed inner surface of the first capacitor electrode and the exposed outer surface of the first capacitor electrode.

20. The method for manufacturing a semiconductor device according to claim 19, wherein: Etching and removing part of the insulating layer along a direction parallel to the substrate includes: etching and removing part of the insulating layer along the first direction, wherein a distance by which the insulating layer is etched is smaller than a length of the first capacitor electrode in the first direction.

21. An electronic device, characterized in that: Comprising the semiconductor device according to any one of claims 1 to 16.

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