Semiconductor device and preparation method thereof, and storage system

Abstract

The embodiment of the invention provides a semiconductor device, a preparation method and a memory system. The semiconductor device includes a first semiconductor structure and a second semiconductor structure. The second semiconductor structure is arranged on one side of the first semiconductor structure along the first direction and is in direct contact with the first semiconductor structure, the second semiconductor structure comprises a plurality of memory units, and the first semiconductor structure comprises a first peripheral circuit connected with the plurality of memory units; and in a plane perpendicular to the first direction, at least part of the first peripheral circuit is located right below the plurality of memory cells, and the first peripheral circuit comprises at least one of a driving structure and a sensing structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor design and preparation, and more specifically, to a semiconductor device, a method for preparing a semiconductor device, and a storage system. Background Art

[0002] Dynamic Random Access Memory (DRAM) is one of the important storage components in electronic systems. Taking DRAM as an example, a semiconductor device may include a storage unit composed of a capacitor and a transistor, wherein a plurality of storage units may be arranged in the form of a two-dimensional array. In order to further reduce the size of the two-dimensional array, the transistor may include a vertical gate transistor (VGT). In this structure, the source and drain of the transistor are respectively located at both ends of the extension direction of the channel of the transistor, and the gate structure of the transistor is located at least on one side of the channel.

[0003] With the rapid development of semiconductor technology, how to improve the storage density of semiconductor devices such as DRAM, optimize their comprehensive performance and reduce their process costs is one of the important research directions in the industry. Summary of the invention

[0004] The present application provides a method for preparing a semiconductor device, a semiconductor device, and a memory system that can at least partially solve the above-mentioned problems existing in the related art or other problems in the art.

[0005] On the one hand, the present application provides a semiconductor device, which includes: a first semiconductor structure; and a second semiconductor structure, which is arranged on one side of the first semiconductor structure along a first direction and directly contacts the first semiconductor structure, wherein the second semiconductor structure includes a plurality of memory cells, and the first semiconductor structure includes a first peripheral circuit connected to the plurality of memory cells; and in a plane perpendicular to the first direction, at least a portion of the first peripheral circuit is located directly below the plurality of memory cells, wherein the first peripheral circuit includes at least one of a driving structure and a sensing structure.

[0006] In one embodiment of the present application, the first semiconductor structure also includes a first interconnect structure, wherein the first interconnect structure is located on a side of the first peripheral circuit close to the second semiconductor structure along the first direction, and connects the first semiconductor structure and the second semiconductor structure; and the second semiconductor structure also includes a power layer and a second interconnect structure, wherein the second interconnect structure connects the power layer and the first semiconductor structure.

[0007] In one embodiment of the present application, the power layer is located on a side of the plurality of memory cells away from the first semiconductor structure along the first direction.

[0008] In one embodiment of the present application, the semiconductor structure includes word lines and bit lines connected to the multiple memory cells; the driving structure includes a word line driving structure connected to the word lines, and the sensing structure includes a bit line sensing amplification structure connected to the bit lines.

[0009] In one embodiment of the present application, the semiconductor structure also includes a word line contact structure connecting the word line and the word line driving structure, and a bit line contact structure connecting the bit line and the bit line sensing amplification structure, wherein at least one of the word line contact structure and the bit line contact structure extends along the first direction.

[0010] In one embodiment of the present application, the bit line extends along a second direction, and the word line extends along a third direction, wherein the first direction, the second direction, and the third direction intersect with each other, wherein in a plane parallel to the second direction and the third direction, the driving structure and the sensing structure are alternately arranged along the second direction or the third direction.

[0011] In one embodiment of the present application, the bit line extends along the second direction, and the word line extends along the third direction, wherein the first direction, the second direction and the third direction intersect with each other, wherein, in a plane parallel to the second direction and the third direction, a plurality of the driving structures are symmetrically distributed; and / or a plurality of the sensing structures are symmetrically distributed.

[0012] In one embodiment of the present application, at least one of the plurality of memory cells includes a vertical transistor and a memory cell connected to the vertical transistor, wherein along the first direction, the vertical transistor is close to the first semiconductor structure relative to the memory cell.

[0013] In one embodiment of the present application, the vertical transistor includes at least one of a full-all-around gate transistor, a multi-gate transistor, and a single-gate transistor.

[0014] In one embodiment of the present application, the vertical transistor includes a thin film transistor.

[0015] In one embodiment of the present application, the vertical transistor includes a semiconductor body extending along the first direction, wherein the semiconductor body includes an oxide semiconductor layer.

[0016] On the other hand, the present application provides a method for preparing a semiconductor device, the method comprising: forming a first semiconductor structure on a substrate; and forming a second semiconductor structure on the first semiconductor structure and in direct contact with the first semiconductor structure, wherein the second semiconductor structure comprises a plurality of memory cells, and the first semiconductor structure comprises a first peripheral circuit connected to the plurality of memory cells; and in a plane parallel to the substrate, the first peripheral circuit is located directly below the plurality of memory cells, wherein the first peripheral circuit comprises at least one of a driving structure and a sensing structure.

[0017] In one embodiment of the present application, forming a second semiconductor structure on the first semiconductor structure in direct contact with the first semiconductor structure includes: forming a first dielectric layer on the first semiconductor structure; forming a memory unit on the first dielectric layer; forming a semiconductor body connected to the memory unit and a gate structure connected to the semiconductor body on the memory unit, wherein the semiconductor body extends along a first direction perpendicular to the substrate.

[0018] In one embodiment of the present application, forming a second semiconductor structure on the first semiconductor structure in direct contact with the first semiconductor structure includes: forming a bit line on the first semiconductor structure; forming a semiconductor body and a gate structure connected to the semiconductor body on the bit line, wherein the semiconductor body extends along a first direction perpendicular to the substrate; and forming a storage unit on the semiconductor body connected to the semiconductor body.

[0019] In one embodiment of the present application, the semiconductor body is formed by a low temperature deposition process, wherein a process temperature T of the low temperature deposition process satisfies: 200°C≤T≤300°C.

[0020] On the other hand, the present application provides a semiconductor device, which includes: a first semiconductor structure; and a semiconductor body, which is arranged on one side of the first semiconductor structure along a first direction, wherein the semiconductor body includes a first part and a second part connected to each other; the first part extends along the first direction; and the second part extends along a direction perpendicular to the first direction and is in direct contact with the first semiconductor structure.

[0021] In one embodiment of the present application, the first semiconductor structure includes a first peripheral circuit, wherein at least a portion of the first peripheral circuit is located directly below the plurality of semiconductor bodies, and the first peripheral circuit includes at least one of a driving structure and a sensing structure.

[0022] In one embodiment of the present application, the semiconductor structure further includes a first interconnect structure, a power layer, and a second interconnect structure, wherein the first interconnect structure is located on a side of the first peripheral circuit close to the semiconductor body along the first direction; the power layer is located on a side of the semiconductor body away from the first semiconductor structure along the first direction; and the second interconnect structure connects the power layer and the first semiconductor structure.

[0023] In one embodiment of the present application, the first portion includes a first end and a second end arranged opposite to each other in the first direction, and a side surface located between the first end and the second end, wherein the semiconductor structure further includes a gate structure and a bit line, the gate structure is located on the side surface of the semiconductor body in the second direction, and the bit line is connected to the first end or the second end, wherein the second direction intersects with the first direction.

[0024] In one embodiment of the present application, the plurality of gate structures adjacent to each other in the second direction are distributed in a mirror-symmetrical manner along the first direction.

[0025] In one embodiment of the present application, a plurality of semiconductor bodies adjacent to each other in the second direction are distributed in a mirror-symmetrical manner along the first direction.

[0026] In one embodiment of the present application, the semiconductor structure also includes a word line connected to the gate structure and extending along a third direction, wherein the first direction, the second direction and the third direction intersect with each other; and the first semiconductor structure includes a first peripheral circuit, wherein the first peripheral circuit includes at least one of a driving structure and a sensing structure, wherein the driving structure includes a word line driving structure connected to the word line, and the sensing structure includes a bit line sensing amplification structure connected to the bit line.

[0027] In one embodiment of the present application, the semiconductor structure also includes a word line contact structure connecting the word line and the word line driving structure, and a bit line contact structure connecting the bit line and the bit line sensing amplification structure, wherein at least one of the word line contact structure and the bit line contact structure extends along the first direction.

[0028] In one embodiment of the present application, in a plane parallel to the second direction and the third direction, the driving structure and the sensing structure are alternately arranged along the second direction or the third direction.

[0029] In one embodiment of the present application, in a plane parallel to the second direction and the third direction, the plurality of driving structures are symmetrically distributed; and / or the plurality of sensing structures are symmetrically distributed.

[0030] In one embodiment of the present application, the semiconductor body includes an oxide semiconductor layer.

[0031] Another aspect of the present application provides a storage system, which includes the semiconductor device provided in one aspect of the present application and a controller coupled to the semiconductor device, wherein the controller is used to store data in the semiconductor device.

[0032] According to the semiconductor device, preparation method and memory system provided by at least one embodiment of the present application, the semiconductor device includes a first semiconductor structure and a second semiconductor structure located above and in direct contact with the first semiconductor structure, wherein the second semiconductor structure includes a plurality of memory cells, and the first semiconductor structure includes a first peripheral circuit connected to the plurality of memory cells, and at least part of the first peripheral circuit is located directly below the plurality of memory cells. In other words, the second semiconductor structure including the plurality of memory cells is formed on a peripheral circuit wafer, and part of the peripheral circuit can be located directly below the plurality of memory cells, thereby reducing the preparation cost of the semiconductor device, reducing the overall size of the semiconductor device, and improving the storage density of the semiconductor device without affecting the comprehensive performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings, in which:

[0034] Figure 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present application;

[0035] Figure 2 is a cross-sectional view of a semiconductor device according to one embodiment of the present application;

[0036] Figure 3 is a partial cross-sectional view of a second semiconductor structure according to one embodiment of the present application;

[0037] Figure 4 is a partial top view of a second semiconductor structure according to one embodiment of the present application;

[0038] Figure 5 is a partial cross-sectional view of a second semiconductor structure according to another embodiment of the present application;

[0039] Figure 6 is a partial top view of a second semiconductor structure according to another embodiment of the present application;

[0040] Figure 7 is a partial cross-sectional view of a second semiconductor structure according to another embodiment of the present application;

[0041] Figure 8 is a partial top view of a second semiconductor structure according to another embodiment of the present application;

[0042] Fig. 9 is a top view of a first peripheral circuit according to an embodiment of the present application;

[0043] Fig.10 is a top view of a first peripheral circuit according to another embodiment of the present application;

[0044] Fig.11 is a top view of a first peripheral circuit according to another embodiment of the present application;

[0045] Fig.12 is a flow chart of a method for preparing a semiconductor device according to an exemplary embodiment of the present application;

[0046] Figure 13-Figure 33 They are respectively process schematic diagrams of a method for preparing a semiconductor device according to an embodiment of the present application;

[0047] Figure 34-Figure 38 are respectively process schematic diagrams of a method for preparing a semiconductor device according to another embodiment of the present application; and

[0048] Fig.39 It is a schematic diagram of the storage system structure according to one embodiment of the present application. DETAILED DESCRIPTION

[0049] In order to better understand the present application, a more detailed description will be made of various aspects of the present application with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0050] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature area, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teaching of this application, the first semiconductor structure discussed in this application may also be referred to as the second semiconductor structure, and vice versa.

[0051] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0052] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0053] Unless otherwise specified, all words (including engineering terms and scientific and technological terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0054] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments in this application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method recorded in this application are not necessarily limited to the recorded order, but can be performed in any order or in parallel.

[0055] In addition, in the present application, when “connected” or “coupled” is used, it may indicate direct contact or indirect contact between corresponding components, unless otherwise clearly defined or inferred from the context.

[0056] The present application will be described in detail below with reference to the accompanying drawings and in combination with implementation modes.

[0057] Some embodiments of the present application provide a semiconductor device. Figure 1 is a cross-sectional view of a semiconductor device 1000 according to one embodiment of the present application. Figure 2 is a cross-sectional view of a semiconductor device 1000 according to one embodiment of the present application.

[0058] like Figure 1-Figure 2As shown, the semiconductor device 1000 includes a first semiconductor structure 200 and a second semiconductor structure 300. The second semiconductor structure 300 is disposed on one side of the first semiconductor structure 200 along a first direction (z direction) and is in direct contact with the first semiconductor structure 200. The second semiconductor structure 300 includes a plurality of memory cells 400, and the first semiconductor structure 200 includes a first peripheral circuit 201 connected to the plurality of memory cells 400. In a plane perpendicular to the z direction (e.g., an xy plane, in which the x direction, the y direction, and the z direction are perpendicular to each other), at least a portion of the first peripheral circuit 201 is located directly below the plurality of memory cells 400, wherein the first peripheral circuit 201 includes at least one of a driving structure 700 and a sensing structure 800.

[0059] It should be noted that in this article Figure 1-Figure 2 In the figure, only the number and position of the memory unit and the peripheral circuit are shown exemplarily, but it can be understood that the memory unit and the peripheral circuit shown in the figure and related content of this invention are only shown for the convenience of illustration, and the present application is not limited thereto. Those skilled in the art can adjust the memory unit and the peripheral circuit according to the idea of ​​the present invention to achieve the same technical effect.

[0060] In addition, the cross-section of the semiconductor device 1000 parallel to the xz plane and the cross-section parallel to the yz plane are respectively arranged on both sides of the dotted line for easy observation. In addition, those skilled in the art will know that the term "directly below" in "at least part of the first peripheral circuit 201 is located directly below the multiple memory cells 400" can be understood as that the setting space of part of the first peripheral circuit overlaps with the setting space of the multiple memory cells along the z direction, so as to reduce the overall size of the semiconductor device and improve the storage density of the semiconductor device without affecting the comprehensive performance of the semiconductor device. In other words, the projection of the multiple memory cells in the xy plane can roughly cover the projection of part of the first peripheral circuit in the xy plane; in other words, at least a part of the first region 01 where the first peripheral circuit 201 is located can be located directly below the multiple memory cells 400.

[0061] In some embodiments, a plurality of memory cells (e.g., a memory array) of a semiconductor device and a peripheral circuit structure connected to the plurality of memory cells may be formed on two different wafers (e.g., a memory array wafer and a peripheral circuit wafer), respectively, and then the peripheral circuit wafer is bonded to the memory array wafer by processes such as wafer bonding, and the peripheral circuit and the memory array circuit are connected together by, for example, connecting wires. However, as the structure of semiconductor devices continues to develop toward high density, the area of ​​the peripheral circuit wafer is increasingly becoming a key factor in determining the size of the entire chip.

[0062] In at least one embodiment of the present application, the second semiconductor structure is disposed on one side of the first semiconductor structure and is in direct contact with the first semiconductor structure. In other words, the second semiconductor structure including a plurality of memory cells is formed on a peripheral circuit wafer, thereby reducing the manufacturing cost of the semiconductor device while not causing distortion caused by the above-mentioned wafer bonding process and limiting the location of the connection line. In addition, the first peripheral circuit including at least one of the driving structure and the sensing structure is at least partially disposed directly below the plurality of memory cells, which is conducive to shortening the length of the connection line between the first peripheral circuit and the plurality of memory cells, thereby reducing the parasitic capacitance of the connection line and improving the sensing tolerance and storage density of the semiconductor device.

[0063] Figure 3 is a partial cross-sectional view of a second semiconductor structure 300 according to one embodiment of the present application. Figure 4 is a partial top view of the second semiconductor structure 300 according to one embodiment of the present application. Figure 5 is a partial cross-sectional view of a second semiconductor structure 300 according to another embodiment of the present application. Figure 6 is a partial top view of a second semiconductor structure 300 according to another embodiment of the present application. Figure 7 is a partial cross-sectional view of a second semiconductor structure 300 according to another embodiment of the present application. Figure 8 is a partial top view of a second semiconductor structure 300 according to another embodiment of the present application.

[0064] Specifically, Figure 1-Figure 8 As shown, the memory cell 400 may include a transistor 401 and a storage cell 402 coupled to the transistor 401, wherein a plurality of memory cells 400 may be formed into a memory cell array. Taking DRAM (Dynamic Random Access Memory) as an example, the semiconductor device 1000 may include a memory cell 400 composed of a capacitor (storage cell 402) and a transistor 401, and a plurality of memory cells 400 may be arranged in the form of a two-dimensional array.

[0065] In other words, in some embodiments, the storage cell 402 may include a capacitor for storing charge as binary information stored by the corresponding DRAM cell. In addition, in some embodiments, the storage cell 402 may include a PCM element (e.g., including a chalcogenide alloy) for storing binary information of the corresponding PCM cell based on the different resistivity of the PCM element in the amorphous phase and the crystalline phase. In addition, in some embodiments, the storage cell 402 may include a ferroelectric capacitor for storing binary information of the corresponding FRAM (Ferroelectric Random Access Memory) cell based on the switching between two polarization states of the ferroelectric material under an external electric field.

[0066] In some embodiments, in order to further reduce the size of the two-dimensional array, the transistor 401 may include a vertical gate transistor (VGT). In this structure, the source and drain of the transistor are respectively located at both ends of the extension direction of the channel of the transistor, and the gate structure of the transistor is at least located on one side of the channel. For example, Figure 3-Figure 8 As shown, the transistor 401 may include a semiconductor body 411 extending along the z-direction and a gate structure 412 located at at least one sidewall of the semiconductor body 411 .

[0067] In one embodiment of the present application, a vertical transistor such as a vertical metal oxide semiconductor field effect transistor (MOSFET) can replace a conventional planar transistor as a transfer transistor of a memory cell to reduce the area occupied by the transfer transistor, coupling capacitance, and interconnect wiring complexity. In some embodiments, unlike a planar transistor in which an active region is formed in a substrate, a vertical transistor may include a semiconductor body 411 extending vertically in the z direction above a substrate (not shown). The semiconductor body 411 may extend above the top surface of the substrate, exposing not only the top surface of the semiconductor body 411, but also one or more sidewalls of the semiconductor body 411.

[0068] Optionally, the semiconductor body 411 may have a cubic shape to expose its four side walls. However, it should be understood by those skilled in the art that the semiconductor body 411 may have any suitable 3D shape, such as a polyhedral shape or a cylindrical shape. In other words, the cross-section of the semiconductor body 411 in the xy plane may have a square shape, a rectangular shape, a trapezoidal shape, a circular shape, an elliptical shape, or any other suitable shape. It should be understood that, consistent with the scope of the present application, for a semiconductor body having a circular or elliptical cross-section in the above plane, the semiconductor body may still be considered to have multiple sidewalls so that the gate structure contacts one of the sidewalls of the semiconductor body. As described below with respect to the preparation process, the semiconductor body 411 may be formed from a substrate by, for example, etching or epitaxial processes, and may therefore have the same semiconductor material as the substrate.

[0069] As an option, the material of the substrate may include, but is not limited to, silicon (e.g., single crystal silicon c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable semiconductor material. For example, the substrate may be a silicon substrate. Accordingly, the semiconductor body 411 may include at least one of the above materials.

[0070] In some embodiments, the transistor 401 may further include a source (not shown) and a drain (not shown) formed at two ends of the semiconductor body 411 in the z direction, respectively, which may be understood as a doped region of the semiconductor body 411, and may also be referred to as a source electrode and a drain electrode. As an option, the source and the drain may be doped with any suitable P-type dopant, and the P-type dopant may include any one or a combination of boron (B) or gallium (Ga). As another option, the source and the drain may be doped with any suitable N-type dopant, and the N-type dopant may include any one or a combination of phosphorus (P), arsenic (As) and antimony (Sb). The source and the drain may be separated by the gate structure 412 in the z direction. In other words, the gate structure 412 is formed between the source and the drain along the z direction. Therefore, when the gate voltage applied to the gate structure 412 is higher than the threshold voltage of the vertical transistor, the channel of the vertical transistor may be formed in the semiconductor body 411 along the z direction between the source and the drain (which may be understood as the gate control capability of the gate structure).

[0071] Alternatively, if Figure 1 As shown, along the z direction, the transistor 401 is closer to the first semiconductor structure 200 than the memory cell 402, so as to shorten the length of the connection line between the transistor 401 and the first semiconductor structure 200 and reduce the parasitic capacitance of the connection line.

[0072] Fig. 9 is a top view of the first peripheral circuit 201 according to an embodiment of the present application.

[0073] Fig.10 is a top view of a first peripheral circuit 201 according to another embodiment of the present application. Fig.11 is a top view of a first peripheral circuit 201 according to another embodiment of the present application.

[0074] Combination Figure 1 , Figure 2 as well as Figure 9-11 , optionally, one of the source and the drain of the transistor 401 may be coupled to the memory cell 402. In addition, the second semiconductor structure 300 further includes a bit line 500 and a word line 600, wherein the bit line 500 may extend along the x-direction and be connected to the other of the source and the drain of the transistor 401. The word line 600 may extend along the y-direction and be connected to the gate structure 412 of the transistor 401. It can be understood that the gate structure 412 and the word line 600 may be continuous conductive structures, and the gate structure 412 may be regarded as an extension of the word line 600 to couple the semiconductor body 411; or, the word line 600 may be regarded as an extension of the gate structure 412 to couple to a peripheral circuit, such as the first peripheral circuit 201.

[0075] Alternatively, if Figure 1 , Figure 2 and Fig. 9 As shown, the semiconductor device 1000 may include a first region 01 and a second region 02 , wherein a first peripheral circuit 201 is located in the first region 01 , and the first peripheral circuit 201 includes at least one of a driving structure 700 and a sensing structure 800 ; in addition, other parts of the peripheral circuit may be located in the second region 02 .

[0076] Alternatively, if Figure 1 , Figure 2 and Fig.10 As shown, in the xy plane parallel to the xy plane, the plurality of driving structures 700 are symmetrically distributed; or, the plurality of sensing structures 800 are symmetrically distributed; or, the plurality of driving structures 700 and the plurality of sensing structures 800 are both symmetrically distributed. For example, the plurality of driving structures 700 are centrally symmetrically distributed; or, the plurality of sensing structures 800 are centrally symmetrically distributed; or, the plurality of driving structures 700 and the plurality of sensing structures 800 are centrally symmetrically distributed. Optionally, as Figure 1 , Figure 2 and Fig.11 As shown, in the xy plane parallel to the driving structure 700 and the sensing structure 800 are alternately arranged along the x direction or the y direction. It is understandable that due to process errors, the symmetrical distribution here should be understood as a roughly symmetrical distribution, and structures with similar arrangements should also be considered to fall within the protection scope of this application.

[0077] In other words, the bit line 500 and the word line 600 may extend in two lateral directions perpendicular to each other, and the semiconductor body 411 of the transistor 401 may extend in a vertical direction perpendicular to the two lateral directions along which the bit line 500 and the word line 600 extend. Therefore, due to the vertical arrangement of the transistor 401, the word line 600 and the bit line 500 may be arranged in different planes in the vertical direction, which simplifies the wiring of the word line 600 and the bit line 500.

[0078] In addition, at least one of the sensing structure 800 connected to the bit line 500 and the driving structure 700 connected to the word line 600 is arranged directly below the multiple memory cells 400, or in other words, in a plane perpendicular to the z-direction, the projections of the multiple memory cells 400 partially overlap with at least one projection of the sensing structure 800 and the driving structure 700, which is beneficial to shorten the length of the connecting line between the first peripheral circuit 201 and the multiple memory cells 400, thereby reducing the parasitic capacitance of the connecting line and improving the sensing tolerance and storage density of the semiconductor device 1000.

[0079] In addition, combined Figure 1 and Figure 2 The semiconductor device 1000 further includes a bit line contact structure 58 connecting the bit line 500 and the sensing structure 800, and a word line driving structure 67 connecting the word line 600 and the driving structure 700. To enhance the above effect, at least one of the bit line contact structure 58 and the word line driving structure 67 may extend along the z direction to enhance the effect of shortening the length of the connection line, thereby reducing the parasitic capacitance of the connection line and improving the sensing tolerance and storage density of the semiconductor device 1000.

[0080] It can be understood that the sensing structure 800 mentioned above includes a bit line sensing amplification structure connected to the bit line 500 , and the driving structure 700 includes a word line driving structure connected to the word line 600 .

[0081] In addition, according to some embodiments, both word line 600 and bit line 500 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), thallium nitride (TaN), polysilicon, silicide, or any combination thereof. In some embodiments, word line 600 and bit line 500 may include multiple conductive layers, such as a W layer on a TiN layer.

[0082] In addition, in some embodiments of the present application, the first semiconductor structure 200 further includes a first interconnect structure 910 , wherein the first interconnect structure 910 is located on a side of the first peripheral circuit 201 close to the second semiconductor structure 300 along the z direction to connect the first semiconductor structure 200 and the second semiconductor structure 300 .

[0083] In addition, the semiconductor device 1000 further includes a power layer 930 for providing electrical signals to the peripheral circuit. In some embodiments of the present application, the power layer 930 is located in the second semiconductor structure 300 and is connected to the peripheral circuit of the first semiconductor structure 200 through the second interconnect structure 920 of the second semiconductor structure 300.

[0084] In addition, the power layer 930 may be located on one side of the plurality of memory cells 400 away from the first semiconductor structure 200 along the z direction. On this basis, the second interconnect structure 920 may extend along the z direction to connect the power layer 930 and the peripheral circuit of the first semiconductor structure 200.

[0085] In the related art, the power layer that provides electrical signals to the peripheral circuit is usually arranged close to the peripheral circuit. In addition, the first interconnection structure used to connect the peripheral circuit with multiple memory cells and the second interconnection structure used to connect the power layer with the peripheral circuit are usually arranged together. However, this layout limits the location of the connection line and reduces the flexibility of the layout.

[0086] As described above, the interconnect structure (which can be understood as the connection line above) includes a first interconnect structure connecting the first semiconductor structure and the second semiconductor structure and a second interconnect structure connecting the power layer and the first semiconductor structure. In some embodiments of the present application, the first interconnect structure and the second interconnect structure are arranged separately, which can expand the spatial position of the interconnect structure layout and improve the flexibility of the interconnect structure layout. On this basis, in order to increase the above-mentioned effect, the power layer that provides electrical signals to the peripheral circuit of the first semiconductor structure can also be arranged on the side of the plurality of memory cells away from the first semiconductor structure along the z direction.

[0087] In addition, the semiconductor device 1000 further includes a first pad 940 connected to an external electrical signal, and the first pad 940 can be connected to the power layer 930 or a peripheral circuit in the first semiconductor structure 200. Optionally, the first pad 940 can be disposed in the second semiconductor structure 300 to expand the spatial position of the interconnection structure layout in the semiconductor device 1000 and improve the flexibility of the interconnection structure layout.

[0088] In addition, refer again Figure 3-Figure 8 In some embodiments of the present application, the transistor 401 may include at least one of a full-ring gate transistor, a multi-gate transistor, and a single-gate transistor.

[0089] Specifically, Figure 3 and Figure 4As shown, in some embodiments of the present application, the transistor 401 may include a single-gate transistor. In this case, the semiconductor body 411 includes a first portion A and a second portion B connected to each other, wherein the first portion A extends along the z direction and the second portion B extends along the x direction perpendicular to the z direction. Optionally, the cross-section of the semiconductor body 411 in the xz plane is "L"-shaped. Multiple semiconductor bodies 411 may be arranged in an array, and the conductive portion of the gate structure 412 (which can be understood as the gate conductive layer below) is located on the side wall of the first portion A of the semiconductor body 411 in the x direction.

[0090] In addition, optionally, multiple semiconductor bodies 411 adjacent in the x direction are distributed in a mirror-symmetrical manner along the z direction. Optionally, multiple gate structures 412 adjacent in the x direction are also distributed in a mirror-symmetrical manner along the z direction. Therefore, in at least one embodiment of the present application, the semiconductor device includes single-gate transistors (also referred to as single-side gate transistors) that are adjacent and mirror-symmetrically arranged in the bit line direction, which can significantly increase the memory cell density in the bit line direction without overly complicating the manufacturing process. In addition, compared with conventional planar transistors, multi-gate vertical transistors (e.g., with double-side gates) or full-ring gate vertical transistors, mirror-symmetrical single-gate transistors have a larger process window for reducing word line, bit line and transistor spacing.

[0091] In addition, if Figure 5-Figure 8 As shown, in some embodiments of the present application, the transistor 401 may include a multi-gate transistor. In this case, the transistor 401 may include a gate structure 412 in contact with one or more sidewalls of the semiconductor body 411. For example, the gate structure 412 may be located on two sidewalls of the semiconductor body 411 that are opposite in the x-direction (also referred to as a double-side gate transistor). In addition, on this basis, the gate structure 412 may also be located on the remaining sidewalls of the semiconductor body 411 except for the two sidewalls that are opposite in the x-direction (also referred to as a full-ring gate transistor), which is not limited in the present application.

[0092] In other words, the gate structure 412 may contact more than one sidewall of the semiconductor body 411 to form more than one gate structure, so that more than one channel may be formed between the source and the drain in operation. For example, the gate structure 412 may be located on one of the two opposite sidewalls of the semiconductor body 411 in the x-direction, and on this basis, also located on the remaining sidewalls of the semiconductor body 411 except the two opposite sidewalls in the x-direction.

[0093] Unlike a planar transistor including only a single planar gate, due to the 3D structure of the semiconductor body 411 and the gate structure 412 surrounding the multiple sidewalls of the semiconductor body 411, the multi-gate vertical transistor has a larger gate control area compared to the planar transistor to achieve better channel control with a smaller subthreshold swing. In addition, for the purpose of, for example, increasing the density of transistors and memory cells, the gate structure 412 may also be in contact with only a single sidewall of the semiconductor body 411, for example, the gate structure 412 is in contact with one of the two sidewalls of the semiconductor body 411 that are opposite in the x-direction, and the present application is not limited to this.

[0094] Specifically, Figure 5-Figure 6 As shown, in the case where the transistor 401 is a double-side gate transistor, the semiconductor body 411 may include a first portion A and a second portion B connected to each other. The first portion A extends along the z direction, and the second portion B extends along the x direction perpendicular to the z direction. Optionally, the cross section of the semiconductor body 411 in the xz plane is an inverted "T" shape. The conductive portion of the gate structure 412 (which can be understood as the gate conductive layer below) is symmetrically located on the sidewall of the first sub-portion of the semiconductor body 411 in the x direction.

[0095] like Figure 7-Figure 8 As shown, when the transistor 401 is a full-all-around gate transistor, the semiconductor body 411 may include a plurality of sidewalls, and the conductive portion of the gate structure 412 (which may be understood as the gate conductive layer hereinafter) surrounds all the sidewalls of the semiconductor body 411 .

[0096] In addition, refer again Figure 3-Figure 8 In one embodiment of the present application, the gate structure 412 may include a gate dielectric layer 412-1 on one or more sidewalls of the semiconductor body 411. In addition, the gate structure 412 may also include a gate conductive layer 412-2 on and in contact with the gate dielectric layer 412-1. The gate conductive layer 412-2 may include a gate adhesion layer (not shown) and a gate metal layer (not shown) on and in contact with the gate adhesion layer. In other words, the gate adhesion layer is located between the gate dielectric layer 412-1 and the gate metal layer.

[0097] The gate dielectric layer 412-1 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric layer 412-1 may include silicon oxide. In addition, the gate adhesion layer may include, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, etc. In addition, the gate metal layer may include any suitable conductive material, such as the gate metal layer may include, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc. The gate adhesion layer is used to block the diffusion of metal materials in the gate metal layer, and is also used to improve the adhesion between the gate metal layer and the gate dielectric layer 412-1.

[0098] In addition, refer again Figure 1 and Figure 2 In some embodiments of the present application, the transistor 401 may include a thin film transistor. In other words, a plurality of memory cells 400 including thin film transistors may be formed on the first semiconductor structure 200 by a thin film manufacturing process.

[0099] Specifically, the semiconductor body 411 included in the thin film transistor may be an oxide semiconductor layer containing at least one of indium, gallium or zinc. For example, the semiconductor body 411 formed of the low-temperature material IGZO (Indium Gallium Zinc Oxide) can further save the use of semiconductor materials, reduce the preparation cost and reduce the overall size of the semiconductor device due to its relatively high carrier mobility and relatively low leakage current.

[0100] In addition, the thin film transistor further includes a source electrode layer and a drain electrode layer. As an option, a buffer layer may be provided between the source electrode layer, the drain electrode layer and the oxide semiconductor layer, wherein the carrier concentration of the buffer layer is higher than the carrier concentration of the oxide semiconductor layer to form an ohmic contact. Optionally, the buffer layer may contain an N-type or P-type conductive impurity element.

[0101] Therefore, as described above, according to at least one embodiment of the present application, the semiconductor device includes a first semiconductor structure and a second semiconductor structure located above and in direct contact with the first semiconductor structure, wherein the second semiconductor structure includes a plurality of memory cells, and the first semiconductor structure includes a first peripheral circuit connected to the plurality of memory cells, and at least part of the first peripheral circuit is located directly below the plurality of memory cells. In other words, the second semiconductor structure including the plurality of memory cells is formed on a peripheral circuit wafer, and part of the peripheral circuit may be located directly below the plurality of memory cells, thereby reducing the preparation cost of the semiconductor device, reducing the overall size of the semiconductor device, and improving the storage density of the semiconductor device without affecting the overall performance of the semiconductor device.

[0102] In addition, refer again Figure 1-Figure 6Some embodiments of the present application provide a semiconductor device 1000. Specifically, the semiconductor device 1000 includes: a first semiconductor structure 200 and a semiconductor body 411. The semiconductor body 411 is disposed on one side of the first semiconductor structure 200 along the z direction, and the semiconductor body 411 includes a first portion A and a second portion B connected to each other. The first portion A extends along the z direction, and the second portion B extends along a direction perpendicular to the z direction and directly contacts the first semiconductor structure 200.

[0103] Therefore, according to the semiconductor device provided by at least one embodiment of the present application, the semiconductor device includes a first semiconductor structure and a plurality of memory cells located on the first semiconductor structure along the z direction and in direct contact with the first semiconductor structure. Specifically, the plurality of memory cells may each include a semiconductor column, the semiconductor column including a first portion and a second portion connected to each other, the second portion may extend in a direction perpendicular to the z direction and in direct contact with the first semiconductor device. Through the above arrangement, a plurality of memory cells may be formed on a peripheral circuit wafer, and the preparation cost of the semiconductor device may be reduced, the overall size of the semiconductor device may be reduced, and the storage density of the semiconductor device may be increased without affecting the comprehensive performance of the semiconductor device.

[0104] Specifically, in order to enhance the above-mentioned effects, in one embodiment of the present application, the first semiconductor structure 200 may include a first peripheral circuit 201, and the first peripheral circuit 201 may include at least one of a driving structure 700 and a sensing structure 800 connected to a plurality of memory cells, wherein at least a portion of the first peripheral circuit 201 may be located directly below the plurality of semiconductor bodies 411.

[0105] In addition, the semiconductor device 1000 further includes a power layer 930 for providing electrical signals to the peripheral circuit. In some embodiments of the present application, the power layer 930 is located on a side of the semiconductor body 411 away from the first semiconductor structure 200 along the z direction. The second interconnect structure 920 of the semiconductor device 1000 connects the peripheral circuit of the first semiconductor structure 200 and the power layer 930.

[0106] In addition, the semiconductor device 1000 further includes a first interconnect structure 910 , wherein the first interconnect structure 910 is located on a side of the first peripheral circuit 201 close to the semiconductor body 411 along the z direction to connect the first semiconductor structure 200 and the semiconductor body 411 .

[0107] The interconnect structure of the semiconductor device includes the first interconnect structure and the second interconnect structure. The first interconnect structure and the second interconnect structure are arranged separately, which can expand the spatial position of the interconnect structure layout and improve the flexibility of the interconnect structure layout. On this basis, in order to increase the above effect, the power supply layer that provides electrical signals to the peripheral circuit of the first semiconductor structure can also be arranged on the side of the plurality of memory cells away from the first semiconductor structure along the z direction.

[0108] In addition, in one embodiment of the present application, the semiconductor body 411 includes an oxide semiconductor layer. In other words, a plurality of semiconductor bodies 411 can be formed on the first semiconductor structure 200 by a thin film preparation process. For example, the semiconductor body 411 formed of the low-temperature material IGZO (Indium Gallium Zinc Oxide) can further save the use of semiconductor materials, reduce the preparation cost and reduce the overall size of the semiconductor device due to its relatively high carrier mobility and relatively low leakage current.

[0109] In addition, in one embodiment of the present application, the semiconductor structure 1000 further includes a gate structure 412. The gate structure 412 is located at the first portion A and the second portion B. Optionally, the gate structure 412 includes a gate dielectric layer 412-1 and a gate conductive layer 412-2 on the gate dielectric layer 412-1 and in contact with the gate dielectric layer 412-1. The gate conductive layer 412-2 extends on the first portion A along the z direction and includes two opposite ends in the z direction, one of which is located on the second portion B.

[0110] In addition, in one embodiment of the present application, the semiconductor structure 1000 further includes a bit line 500 and a word line 600. The bit line 500 may extend along the x-direction and be located on a side of the second portion B away from the first portion A, or on a side of the first portion A away from the second portion B. The word line 600 may extend along the y-direction and be connected to the gate structure 412 of the transistor 401. It can be understood that the gate structure 412 and the word line 600 may be continuous conductive structures, and the gate structure 412 may be regarded as an extension of the word line 600 to couple the semiconductor body 411; or, the word line 600 may be regarded as an extension of the gate structure 412 to couple to a peripheral circuit, such as the first peripheral circuit 201.

[0111] Alternatively, if Figure 3 and Figure 4 As shown, multiple semiconductor bodies 411 adjacent in the x direction are distributed in a mirror-symmetrical manner along the z direction. Optionally, multiple gate structures 412 adjacent in the x direction are also distributed in a mirror-symmetrical manner along the z direction. Therefore, in at least one embodiment of the present application, the semiconductor device includes single-gate transistors (also referred to as single-side gate transistors) that are adjacent and mirror-symmetrically arranged in the bit line direction, which can significantly increase the memory cell density in the bit line direction without overly complicating the manufacturing process. In addition, compared with conventional planar transistors or multi-gate vertical transistors (e.g., with double-sided or full-ring gates), mirror-symmetrical single-gate transistors have a larger process window for reducing word line, bit line and transistor spacing.

[0112] In addition, if Figure 1 , Figure 2 and Figure 9-11 As shown, in one embodiment of the present application, the driving structure 700 included in the first peripheral circuit 201 is connected to the word line 600, and the sensing structure 800 included is connected to the bit line 500. Optionally, in parallel to the xy plane, multiple driving structures 700 are centrally symmetrically distributed; or, multiple sensing structures 800 are centrally symmetrically distributed; or, multiple driving structures 700 and multiple sensing structures 800 are centrally symmetrically distributed. Optionally, in parallel to the xy plane, the driving structures 700 and the sensing structures 800 are alternately arranged along the x direction or the y direction.

[0113] In other words, the bit line 500 and the word line 600 may extend in two lateral directions perpendicular to each other, and the semiconductor body 411 of the transistor 401 may extend in a vertical direction perpendicular to the two lateral directions along which the bit line 500 and the word line 600 extend. Therefore, due to the vertical arrangement of the transistor 401, the word line 600 and the bit line 500 may be arranged in different planes in the vertical direction, which simplifies the wiring of the word line 600 and the bit line 500.

[0114] In addition, at least one of the sensing structure 800 connected to the bit line 500 and the driving structure 700 connected to the word line 600 is arranged directly below the multiple memory cells 400, which is beneficial to shorten the length of the connecting line between the first peripheral circuit 201 and the multiple memory cells 400, thereby reducing the parasitic capacitance of the connecting line and improving the sensing tolerance and storage density of the semiconductor device 1000.

[0115] In addition, combined Figure 1 and Figure 2 The semiconductor device 1000 further includes a bit line contact structure 58 connecting the bit line 500 and the sensing structure 800, and a word line driving structure 67 connecting the word line 600 and the driving structure 700. To enhance the above effect, at least one of the bit line contact structure 58 and the word line driving structure 67 may extend along the z direction to enhance the effect of shortening the length of the connection line, thereby reducing the parasitic capacitance of the connection line and improving the sensing tolerance and storage density of the semiconductor device 1000.

[0116] It can be understood that the sensing structure 800 mentioned above includes a bit line sensing amplification structure connected to the bit line 500 , and the driving structure 700 includes a word line driving structure connected to the word line 600 .

[0117] Some embodiments of the present application provide a method for preparing a semiconductor device. Fig.12 is a flow chart of a method 2000 for fabricating a semiconductor device according to an exemplary embodiment of the present application. Figure 13-Figure 33 They are respectively process schematic diagrams of a method 2000 for preparing a semiconductor device according to an embodiment of the present application; and Figure 34-Figure 38 They are respectively process schematic diagrams of a method 2000 for preparing a semiconductor device according to another embodiment of the present application.

[0118] like Fig.12 As shown, the present application provides a method 2000 for preparing a semiconductor device, comprising:

[0119] S1, forming a first semiconductor structure on a substrate, wherein the first semiconductor structure includes a first peripheral circuit, and the first peripheral circuit includes at least one of a driving structure and a sensing structure.

[0120] S2, forming a second semiconductor structure on the first semiconductor structure and in direct contact with the first semiconductor structure, wherein the second semiconductor structure includes a plurality of memory cells connected to the first peripheral circuit, and in a plane parallel to the substrate, the first peripheral circuit is located directly below the plurality of memory cells.

[0121] The following will be combined Figure 13-Figure 33 The specific process of each step of the above-mentioned preparation method 2000 in Example 1 is described in detail.

[0122] Example 1

[0123] Step S1

[0124] Fig.13 It is a schematic top view of a structure formed after forming a first semiconductor structure 200 according to a preparation method in one embodiment of the present application.

[0125] like Figure 12-13 As shown, step S1 forms a first semiconductor structure on a substrate, wherein the first semiconductor structure includes a first peripheral circuit, and the first peripheral circuit includes at least one of a driving structure and a sensing structure, which may for example include: providing a substrate 100; and forming a first peripheral circuit 201 in the substrate 100.

[0126] Specifically, in one embodiment of the present application, the material for preparing the substrate 100 can be any suitable semiconductor material, for example, single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon on insulator (SOI), germanium on insulator (GOI) or III-V compounds such as gallium arsenide. As an option, the substrate 100 can be selected from single crystal silicon.

[0127] In one embodiment of the present application, the substrate 100 may be, for example, a composite substrate for supporting a device structure thereon. The substrate 100 may be formed by sequentially arranging a plurality of layers made of different materials through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0128] In one embodiment of the present application, the substrate 100 may include a substrate sacrificial layer (not shown). Optionally, the substrate sacrificial layer may include a single layer, a multilayer or a suitable composite layer. For example, the substrate sacrificial layer may include any one or more of a silicon oxide layer, a silicon nitride layer and a silicon oxynitride layer. As an option, the substrate sacrificial layer may be a high dielectric constant dielectric layer. As another option, the substrate sacrificial layer may include a dielectric layer, a sacrificial layer and a dielectric layer arranged in sequence, wherein the dielectric layer may be a silicon nitride layer and the sacrificial layer may be a silicon oxide layer. As another option, the substrate sacrificial layer may include any one or more of a dielectric material, a semiconductor material and a conductive material. For example, the sacrificial layer may be single crystal silicon or polycrystalline silicon. Specifically, in one embodiment of the present application, an exemplary material for forming the sacrificial layer may be polycrystalline silicon.

[0129] In addition, a part of the substrate 100 may also form a well region (not shown) formed by doping with an N-type or P-type dopant via an ion implantation or diffusion process. The dopant may include any one or a combination of phosphorus (P), arsenic (As) and antimony (Sb); or any one or a combination of boron (B), gallium (Ga) or indium (In). In some embodiments of the present application, the well region may be prepared with the same dopant or with different dopants. Further, the doping concentration of the well region may be the same or different, which is not limited in the present application.

[0130] After forming the substrate 100 , a peripheral circuit may be formed in the substrate 100 , wherein the peripheral circuit includes a first peripheral circuit 201 , and the first peripheral circuit 201 may include at least one of a driving structure 700 and a sensing structure 800 .

[0131] Optionally, the driving structure 700 includes a word line driving structure connected to a word line in a second semiconductor structure formed subsequently. The sensing structure 800 includes a bit line sensing amplification structure connected to a bit line in a second semiconductor structure formed subsequently. The manufacturing process of the driving structure 700, the sensing structure 800 and other peripheral circuits can adopt existing conventional processes and be manufactured according to actual needs, which will not be described in detail here.

[0132] Optionally, at least a portion of the first peripheral circuit 201 is formed in the first region 01 of the substrate 100 , and a plurality of memory cells in the subsequently formed second semiconductor structure are formed above the first region 01 .

[0133] It should be noted that in this article Figure 13-Figure 33 In the present invention, only the number and location of memory cells and peripheral circuits are shown exemplarily, but it can be understood that the memory cells and peripheral circuits shown in the figures and related contents of this article are only shown for the convenience of illustration, and this application is not limited thereto. Those skilled in the art can adjust the memory cells and peripheral circuits according to the concept of the present invention to achieve the same technical effect. In addition, in this article Fig.13 As in other figures in Embodiment 1, the cross section of the intermediate body of the semiconductor device 1000 parallel to the xz plane and the cross section parallel to the yz plane are respectively arranged on both sides of the dotted line for easy observation.

[0134] Optionally, refer to Fig.10 and Fig.11 In a plane (xy plane) parallel to the substrate 100, the driving structure 700 and the sensing structure 800 may be alternately arranged along the x direction or the y direction. Optionally, in the xy plane, a plurality of driving structures 700 may be arranged in a centrally symmetrical distribution; and / or a plurality of sensing structures 800 may be arranged in a centrally symmetrical distribution.

[0135] In addition, in one embodiment of the present application, step S1 forms a first semiconductor structure on a substrate, wherein the first semiconductor structure includes a first peripheral circuit, the first peripheral circuit includes at least one of a driving structure and a sensing structure, and further includes: forming an interconnection contact 921 connected to a second interconnection structure, the second interconnection structure is used to connect the first semiconductor structure 200 and a subsequently formed power supply layer. The structure and preparation process of the interconnection contact 921 can be prepared according to actual needs using existing conventional processes, and will not be described in detail here.

[0136] In addition, in one embodiment of the present application, after forming the first peripheral circuit 201, step S1 forms a first semiconductor structure on the substrate, wherein the first semiconductor structure includes the first peripheral circuit, and the first peripheral circuit includes at least one of a driving structure and a sensing structure, and further includes: forming a first dielectric spacer 202 covering at least the first peripheral circuit 201 by one or more thin film deposition processes, and the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. Thin film deposition process or any combination thereof. Optionally, the first dielectric spacer 202 may include any suitable dielectric material, such as oxide, nitride, oxynitride or high-k dielectric. For example, the first dielectric spacer 202 may include silicon oxide. In addition, the first dielectric spacer 202 and the subsequently formed initial second dielectric spacer 203' have no obvious boundary when they are made of the same material.

[0137] Step S2

[0138] Fig.14 It is a schematic cross-sectional view of a structure formed after forming a semiconductor body 411 according to a preparation method in one embodiment of the present application. Fig.15 It is a schematic cross-sectional view of a structure formed after forming an initial gate structure 412 ′ according to a preparation method in one embodiment of the present application. Fig.16 It is a schematic cross-sectional view of a structure formed after forming a gate structure 412 according to a preparation method in one embodiment of the present application. Fig.17 for Fig.16 The intermediate shown is a schematic cross-sectional view of the structure formed after rotating 90° in the xy plane.

[0139] like Figure 13-Figure 17 As shown, step S2 forms a second semiconductor structure directly in contact with the first semiconductor structure on the first semiconductor structure, wherein the second semiconductor structure includes a plurality of memory cells connected to the first peripheral circuit, and in a plane parallel to the substrate, the first peripheral circuit is located directly below the plurality of memory cells and may, for example, include: forming a bit line 500 on the first semiconductor structure 200; forming a semiconductor body 411 and a gate structure 412 connected to the semiconductor body 411 on the bit line 500, wherein the semiconductor body 411 extends in a first direction (z direction) perpendicular to the substrate 100; and forming a memory cell 402 connected to the semiconductor body 411 on the semiconductor body 411.

[0140] Specifically, Fig.13As shown, in one embodiment of the present application, a bit line 500 is formed on the first peripheral circuit 201 by one or more thin film deposition processes, and the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0141] The bit line 500 may extend in an x-direction perpendicular to the z-direction. Optionally, the bit line 500 may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), thallium nitride (TaN), polysilicon, silicide, or any combination thereof. In some embodiments, the bit line 500 may include multiple conductive layers, such as a W layer on a TiN layer.

[0142] After forming the bit line 500, an initial second dielectric spacer 203' covering the first semiconductor structure 200 and the bit line 500 may be formed by one or more thin film deposition processes, and the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0143] Optionally, the initial second dielectric spacer 203' may include any suitable dielectric material, such as oxide, nitride, oxynitride or high-k dielectric. For example, the initial second dielectric spacer 203' may include silicon oxide. In addition, the initial second dielectric spacer 203' and the first dielectric spacer 202 are made of the same material without obvious boundaries.

[0144] like Fig.13 and Fig.14 As shown, in one embodiment of the present application, forming a semiconductor body 411 extending along the z direction on the bit line 500 may, for example, include: forming a first opening 123, wherein the first opening 123 extends along the z direction in the initial second dielectric spacer 203' to the bit line 500; forming an initial semiconductor body (not shown) on the inner wall of the first opening 123; and removing a portion of the initial semiconductor body to form the semiconductor body 411.

[0145] Optionally, the first openings 123 extending along the z direction are formed in the initial second dielectric spacer 203' by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, etc., may also be performed. The number and position of the first openings 123 are determined by the position and number of the semiconductor bodies formed subsequently. For example, two semiconductor bodies 411 that are mirror-symmetric along the x direction may be formed in the first openings 123. In addition, the radial size of the first openings 123 located at the edge may be smaller than the radial size of the first openings 123 located in the middle, because only one semiconductor body 411 may be formed in the first openings 123 located at the edge.

[0146] After forming the first opening 123, an initial semiconductor body may be formed on the inner wall of the first opening 123 by one or more thin film deposition processes, and the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0147] Alternatively, the initial semiconductor body may be formed by a thin film fabrication process. For example, the initial semiconductor body may be an oxide semiconductor layer including at least one of indium, gallium, or zinc.

[0148] Optionally, a low temperature deposition process is used to form the initial semiconductor body. The process temperature T of the low temperature deposition process may satisfy: 200°C ≤ T ≤ 300°C. For example, the initial semiconductor body is formed using a low temperature material IGZO, which has a relatively high carrier mobility and a relatively low leakage current, thereby further saving the use of semiconductor materials, reducing the preparation cost and reducing the overall size of the semiconductor device.

[0149] After the initial semiconductor body is formed, it is formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes may also be performed, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, etc., to remove part of the initial semiconductor body to form a semiconductor body 411.

[0150] In addition, a source (not shown) and a drain (not shown) may be formed at opposite ends of the semiconductor body 411 in the z direction through a doping process, which may be understood as a doping region of the semiconductor body 411, and may also be referred to as a source electrode and a drain electrode. As an option, the source and the drain may be doped with any suitable P-type dopant, which may include any one or a combination of boron (B) or gallium (Ga). As another option, the source and the drain may be doped with any suitable N-type dopant, which may include any one or a combination of phosphorus (P), arsenic (As) and antimony (Sb).

[0151] like Fig.14 As shown, the semiconductor body 411 includes a first portion A and a second portion B connected to each other, wherein the first portion A extends along the z direction, and the second portion B extends along the x direction perpendicular to the z direction. Optionally, the cross section of the semiconductor body 411 in the xz plane is "L" shaped. Multiple semiconductor bodies 411 can be arranged in an array.

[0152] In addition, if Figure 13-14 As shown, in one embodiment of the present application, after the semiconductor body 411 is formed, a dielectric material layer can be filled in the first opening 123 in which the semiconductor body 411 has been formed by one or more thin film deposition processes, and the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0153] In addition, any suitable planarization process, such as grinding and / or chemical mechanical polishing process, may be performed to process the upper surface of the filling dielectric material layer and the initial second dielectric spacer layer 203', so that the processed filling dielectric material layer and the initial second dielectric spacer layer 203' have a relatively flat upper surface, so as to facilitate the subsequent processes to be performed on the flat surface.

[0154] like Figure 14-16 As shown, in one embodiment of the present application, forming a gate structure 412 connected to the semiconductor body 411 may, for example, include: forming a second opening (not shown) extending along the z direction in the filling dielectric material layer; forming an initial gate structure 412' on the inner wall of the second opening; and removing a portion of the initial gate structure 412' to form the gate structure 412.

[0155] Optionally, the second opening extending along the z direction is formed in the filling dielectric material layer by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, etc., may also be performed. The number and position of the second openings are determined by the position and number of the gate structures formed subsequently. For example, two gate structures 412 that are mirror-symmetric along the x direction may be formed in the second openings. In addition, the radial size of the second opening located at the edge may be smaller than the radial size of the second opening located in the middle, because only one gate structure 412 may be formed in the second opening located at the edge.

[0156] After forming the second opening, an initial gate structure 412' may be formed on the inner wall of the second opening by one or more thin film deposition processes, and the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0157] Optionally, the initial gate structure 412' includes: an initial gate dielectric layer 412-1' and an initial gate conductive layer 412-2' on the initial gate dielectric layer 412-1' and in contact with the initial gate dielectric layer 412-1'. In addition, the initial gate conductive layer 412-2' may include: an initial gate adhesion layer (not shown) and an initial gate metal layer (not shown) on the initial gate adhesion layer and in contact with the initial gate adhesion layer. In other words, the initial gate adhesion layer is located between the initial gate dielectric layer 412-1' and the initial gate metal layer.

[0158] The initial gate dielectric layer 412-1' may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the initial gate dielectric layer 412-1' may include silicon oxide. In addition, the initial gate adhesion layer may include, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, etc. In addition, the initial gate metal layer may include any suitable conductive material, such as the initial gate metal layer may include, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc. The initial gate adhesion layer is used to block the diffusion of metal materials in the initial gate metal layer, and is also used to improve the adhesion between the initial gate metal layer and the initial gate dielectric layer 412-1'.

[0159] After the initial gate structure 412' is formed, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can also be performed, such as a patterning process including photolithography, cleaning and chemical mechanical polishing, etc., to remove part of the initial gate structure 412' to form the gate structure 412.

[0160] like Fig.16 and Fig.17 As shown, after forming the gate structure 412, it can be understood that the transistor 401 has been formed. In the transistor 401, the conductive portion of the gate structure 412 (which can be understood as the gate conductive layer mentioned above) is located on the sidewall of the first portion A of the semiconductor body 411 in the x direction.

[0161] In other words, multiple semiconductor bodies 411 adjacent in the x direction are distributed in a mirror-symmetrical manner along the z direction, and multiple gate structures 412 adjacent in the x direction are also distributed in a mirror-symmetrical manner along the z direction. Therefore, in at least one embodiment of the present application, the semiconductor device includes single-gate transistors (also referred to as single-side gate transistors) adjacent and arranged in a mirror-symmetrical manner in the bit line direction, which can significantly increase the density of memory cells in the bit line direction without overly complicating the manufacturing process. In addition, compared with conventional planar transistors or multi-gate vertical transistors (e.g., with double-side gates) or full-ring gate vertical transistors, mirror-symmetrical single-gate transistors have a larger process window for reducing word line, bit line and transistor spacing.

[0162] Optionally, the word line 600 connected to the gate structure 412 may be formed by one or more thin film deposition processes, which may include but are not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0163] The word line 600 may extend in a y direction perpendicular to the z direction. Optionally, the word line 600 may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), thallium nitride (TaN), polysilicon, silicide, or any combination thereof. In some embodiments, the word line 600 may include multiple conductive layers, such as a W layer on a TiN layer.

[0164] In addition, combined Figure 1 and Fig.17 After forming the transistor 401, a memory cell 402 connected to the semiconductor body 411 may be formed on the semiconductor body 411. The structure and preparation process of the memory cell 402 may adopt existing conventional processes and be prepared according to actual needs, and this application will not elaborate on them here.

[0165] Alternatively, in some embodiments, taking DRAM as an example, the storage unit 402 may include a capacitor, and a plurality of storage units 402 may be arranged in a two-dimensional array. Alternatively, in some embodiments, taking a PCM element as an example, the storage unit 402 may include a unit having different resistivities in an amorphous phase and a crystalline phase to store a corresponding PCM. For example, a chalcogenide alloy is included. Alternatively, in some embodiments, taking FRAM as an example, the storage unit 402 may include a ferroelectric capacitor. This application is not limited thereto.

[0166] In addition, if Fig.16 and Fig.17As shown, after the gate structure 412 is formed, one or more thin film deposition processes can be used to fill the space between the multiple gate structures 412 with a gate structure spacing dielectric layer, or the space remaining in the second opening after the gate structure 412 is formed. The thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. Thin film deposition process or any combination thereof.

[0167] Optionally, the gate structure spacing filling dielectric layer may include any suitable dielectric material, such as oxide, nitride, oxynitride or high-k dielectric. For example, the gate structure spacing filling dielectric layer may include silicon oxide. In addition, when the gate structure spacing filling dielectric layer and the initial second dielectric spacing layer 203' are made of the same material, there is no obvious boundary. After the gate structure spacing filling dielectric layer is formed, the gate structure spacing filling dielectric layer and the initial second dielectric spacing layer 203' remaining in the above step form the second dielectric spacing layer 203.

[0168] As mentioned above, Figure 13-Figure 17 A semiconductor device 1000 having a single-side gate transistor is described. Figure 1 The preparation process shown in Figure 18-Figure 25 , Figure 26-Figure 33 The manufacturing process of the semiconductor device 1000 having multi-gate transistors and all-around gate transistors is described in detail.

[0169] Specifically, since the contents involved in the method 2000 for preparing a semiconductor device with a single-side gate transistor described above can be fully or partially applied to the method for preparing a semiconductor device with a multi-gate transistor or a full-ring gate transistor described here, the contents related or similar thereto are not described in detail. However, it can be understood by those skilled in the art that the semiconductor device 1000 (such as the semiconductor device 1000) can be formed based on the method 2000 for preparing a semiconductor device described above. Figure 1 As shown in FIG. 1 , the semiconductor device 1000 can also be formed according to the semiconductor device manufacturing method 2000 described below. Based on this, the semiconductor device manufacturing method 2000 described in Embodiment 1 has the same beneficial effects as the semiconductor structure 1000, and will not be described in detail here.

[0170] Fig.18 It is a cross-sectional schematic diagram of a structure after the third opening 124 is formed according to a preparation method in one embodiment of the present application. Fig.19 It is a schematic top view of a structure after the third opening 124 is formed according to a preparation method in one embodiment of the present application. Fig. 20 It is a schematic cross-sectional view of a structure after a gate conductive layer 412 - 2 is formed according to a preparation method in one embodiment of the present application. Fig.21 It is a schematic top view of a structure after a gate conductive layer 412 - 2 is formed according to a preparation method in one embodiment of the application. Fig. 22 It is a schematic cross-sectional view of a structure after a gate dielectric layer 412 - 1 is formed according to a preparation method in one embodiment of the present application. Fig.23 It is a schematic top view of a structure after a gate dielectric layer 412 - 1 is formed according to a preparation method in one embodiment of the present application. Fig.24 It is a schematic cross-sectional view of a structure after a semiconductor body 411 is formed according to a preparation method in one embodiment of the present application. Fig.25 It is a schematic top view of a structure after a semiconductor body 411 is formed according to a preparation method in one embodiment of the present application.

[0171] Combination Fig.13 , Fig.18 , Fig.19 In some embodiments of the present application, after the bit line 500 is formed in step S2, an initial second dielectric spacer 203' covering the first semiconductor structure 200 and the bit line 500 may be formed by one or more thin film deposition processes, and the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0172] Optionally, the initial second dielectric spacer 203' may include any suitable dielectric material, such as oxide, nitride, oxynitride or high-k dielectric. For example, the initial second dielectric spacer 203' may include silicon oxide. In addition, the initial second dielectric spacer 203' and the first dielectric spacer 202 are made of the same material without obvious boundaries.

[0173] Optionally, the initial second dielectric spacer 203' may include two parts stacked in sequence, a first initial second dielectric spacer 203'-1 and a second initial second dielectric spacer 203'-2. As an option, the first initial second dielectric spacer 203'-1 directly in contact with the bit line 500 may be made of the same material as the gate dielectric layer 412-1 formed subsequently. In the case of using the same material, there is no obvious boundary between the two. In this case, the second initial second dielectric spacer 203'-2 may also be made of the same material as the first dielectric spacer 202. In the case of using the same material, there is no obvious boundary between the two.

[0174] like Figure 18-19As shown, after the initial second dielectric spacer 203' is formed, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can also be performed, such as a patterning process including photolithography, cleaning and chemical mechanical polishing, etc., to form a third opening 124 extending along the z direction in the second portion of the initial second dielectric spacer 203'-2, and the third opening 124 can extend to the first portion of the initial second dielectric spacer 203'-1.

[0175] like Figure 18-Figure 23 As shown, after the third opening 124 is formed, a gate structure 412 is formed on the inner wall of the third opening 124 by one or more thin film deposition processes, and the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0176] Alternatively, if Figure 18-Figure 21 As shown, forming the gate structure 412 may include: forming a gate conductive layer 412-2 on the inner wall of the third opening 124 by one or more thin film deposition processes, and the gate conductive layer 412-2 may include: a gate adhesion layer (not shown) and a gate metal layer on the gate adhesion layer and in contact with the gate adhesion layer. The gate adhesion layer may include but is not limited to titanium, titanium nitride, tantalum, tantalum nitride, etc. In addition, the gate metal layer may include any suitable conductive material, for example, the gate metal layer may include but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc.

[0177] It should be noted that during the formation of the gate conductive layer 412 - 2 , an initial gate conductive layer may be first formed on the sidewalls and bottom surface of the third opening 124 , and then the bottom portion of the initial gate conductive layer may be removed by a process such as etching.

[0178] like Figure 20-23 As shown, after the gate conductive layer 412-2 is formed, a gate dielectric layer 412-1 may be formed on the surface of the gate conductive layer 412-2 by one or more thin film deposition processes, and the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0179] Alternatively, the gate dielectric layer 412-1 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric layer 412-1 may include silicon oxide. In addition, the gate adhesion layer is used to block the diffusion of metal materials in the gate metal layer and to improve the adhesion between the gate metal layer and the gate dielectric layer 412-1.

[0180] In one embodiment of the present application, Figure 22-Figure 25 As shown, after forming the gate structure 412, the third opening 124 (eg Fig.18 A semiconductor body 411 is formed in the remaining space (as shown).

[0181] As an option, the semiconductor body 411 can be formed by a thin film preparation process. For example, the semiconductor body 411 can be an oxide semiconductor layer containing at least one of indium, gallium or zinc. Optionally, the semiconductor body 411 is formed by a low temperature deposition process. The process temperature T of the low temperature deposition process can satisfy: 200°C ≤ T ≤ 300°C. For example, the semiconductor body is formed using a low temperature material IGZO, because its carrier mobility is relatively high and the leakage current is relatively low, the use of semiconductor materials can be further saved, the preparation cost can be reduced, and the overall size of the semiconductor device can be reduced.

[0182] Through the above process, a multi-gate vertical transistor with double side gates can be formed. Due to the 3D structure of the semiconductor body 411 and the gate structure 412 surrounding the multiple sidewalls of the semiconductor body 411, the multi-gate vertical transistor has a larger gate control area compared to a single-gate transistor to achieve better channel control with a smaller subthreshold swing.

[0183] Fig.26 It is a schematic cross-sectional view after forming the first gate conductive layer 412 - 2 - 1 according to a preparation method in one embodiment of the present application. Fig. 27 It is a top perspective schematic diagram of a structure after forming a first gate conductive layer 412 - 2 - 1 according to a preparation method in one embodiment of the present application. Fig.28 It is a schematic cross-sectional view of a structure after forming a second gate conductive layer 412 - 2 - 2 according to a preparation method in one embodiment of the present application. Fig.29 It is a top perspective schematic diagram of a structure after forming a second gate conductive layer 412 - 2 - 2 according to a preparation method of an embodiment of the application. Fig.30 It is a schematic cross-sectional view of a structure after a gate conductive layer 412 - 2 is formed according to a preparation method in one embodiment of the present application. Fig.31 It is a top perspective schematic diagram of a structure after a gate conductive layer 412 - 2 is formed according to a preparation method in one embodiment of the present application. Fig.32 It is a schematic diagram of forming a semiconductor body 411 according to a manufacturing method according to one embodiment of the present application. Fig.33 It is a schematic top perspective view of a structure for forming a semiconductor body 411 according to a manufacturing method in accordance with an embodiment of the present application.

[0184] Combination Fig.13 , Fig.26 , Fig. 27In some embodiments of the present application, after the bit line 500 is formed in step S2, an initial second dielectric spacer 203' and a first gate conductive layer 412-2-1 covering the first semiconductor structure 200 and the bit line 500 may be formed by one or more thin film deposition processes, and the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. Thin film deposition process or any combination thereof.

[0185] Optionally, the initial second dielectric spacer 203' may include two parts, a third part, an initial second dielectric spacer 203'-3, and a fourth part, an initial second dielectric spacer 203'-4. The initial second dielectric spacer 203' may include any suitable dielectric material, such as an oxide, a nitride, an oxynitride, or a high-k dielectric. For example, the initial second dielectric spacer 203' may include silicon oxide. As an option, the initial second dielectric spacer 203' may be made of the same material as the first dielectric spacer 202, and in the case of being made of the same material, there is no obvious boundary between the two.

[0186] Optionally, the third initial second dielectric spacer layer 203 ′- 3 and the fourth initial second dielectric spacer layer 203 ′- 4 are made of the same material. When the same material is used, there is no obvious boundary between the two.

[0187] Specifically, through the above process, a third initial second dielectric spacer 203'-3 can be formed on at least the surface of the bit line 500; then, a first gate conductive layer 412-2-1 is formed on the surface of the third initial second dielectric spacer 203'-3; then, a fourth initial second dielectric spacer 203'-4 is formed on the first gate conductive layer 412-2-1.

[0188] Optionally, the first gate conductive layer 412-2-1 may include: a first gate adhesion layer (not shown) and a first gate metal layer on the first gate adhesion layer and in contact with the first gate adhesion layer. The first gate adhesion layer may include, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, etc. In addition, the first gate metal layer may include any suitable conductive material, for example, the gate metal layer may include, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc.

[0189] like Figure 26-Figure 29As shown, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, can also be performed to remove part of the first gate conductive layer 412-2-1 to form the second gate conductive layer 412-2-2. In addition, the fifth initial second dielectric spacer 203'-5 can be filled in the space formed after removing part of the first gate conductive layer 412-2-1 through one or more thin film deposition processes to separate the multiple second gate conductive layers 412-2-2. Optionally, the fifth initial second dielectric spacer 203'-5 can be made of the same material as the third initial second dielectric spacer 203'-3 and the fourth initial second dielectric spacer 203'-4. When the same material is used, there is no obvious boundary between the three.

[0190] like Figure 28-Figure 31 As shown, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes may also be performed, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, etc., to remove a portion of the second gate conductive layer 412-2-2 to form a fourth opening 125 extending along the z direction and the gate conductive layer 412-2.

[0191] like Figure 30-Figure 33 As shown, a gate dielectric layer 412-1 and a semiconductor body 411 may be formed in the fourth opening 125 by one or more thin film deposition processes, and the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0192] Alternatively, the gate dielectric layer 412-1 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric layer 412-1 may include silicon oxide. In addition, the gate adhesion layer is used to block the diffusion of metal materials in the gate metal layer and to improve the adhesion between the gate metal layer and the gate dielectric layer 412-1.

[0193] In addition, the semiconductor body 411 may be an oxide semiconductor layer containing at least one of indium, gallium or zinc. Optionally, the semiconductor body 411 is formed by a low temperature deposition process. The process temperature T of the low temperature deposition process may satisfy: 200°C ≤ T ≤ 300°C. For example, the semiconductor body is formed by using a low temperature material IGZO, because its carrier mobility is relatively high and the leakage current is relatively low, thus further saving the use of semiconductor materials, reducing the preparation cost and reducing the overall size of the semiconductor device.

[0194] Through the above process, a full-all-around gate transistor can be formed. Due to the 3D structure of the semiconductor body 411 and the gate structure 412 surrounding the entire sidewall of the semiconductor body 411, the full-all-around gate transistor has a larger gate control area than a single-gate transistor to achieve better channel control with a smaller subthreshold swing.

[0195] Fig.26 It is a schematic cross-sectional view after forming the first gate conductive layer 412 - 2 - 1 according to a preparation method in one embodiment of the present application. Fig. 27 It is a top perspective schematic diagram of a structure after forming a first gate conductive layer 412 - 2 - 1 according to a preparation method in one embodiment of the present application. Fig.28 It is a schematic cross-sectional view of a structure after forming a second gate conductive layer 412 - 2 - 2 according to a preparation method in one embodiment of the present application. Fig.29 It is a top perspective schematic diagram of a structure after forming a second gate conductive layer 412 - 2 - 2 according to a preparation method of an embodiment of the application. Fig.30 It is a schematic cross-sectional view of a structure after a gate conductive layer 412 - 2 is formed according to a preparation method in one embodiment of the present application. Fig.31 It is a top perspective schematic diagram of a structure after a gate conductive layer 412 - 2 is formed according to a preparation method in one embodiment of the present application. Fig.32 It is a schematic diagram of forming a semiconductor body 411 according to a manufacturing method according to one embodiment of the present application. Fig.33 It is a schematic top perspective view of a structure for forming a semiconductor body 411 according to a manufacturing method in accordance with an embodiment of the present application.

[0196] In addition, reference Figure 1 After forming the memory cell 400, a power layer 930 and a second interconnection structure 920 may be further formed above the memory cell 400. The preparation process of the power layer 930 and the second interconnection structure 920 may adopt the existing conventional process and be prepared according to actual needs, which will not be described in detail here.

[0197] Optionally, the second interconnect structure 920 may extend along the z-direction to connect the power layer 930 and the peripheral circuit of the first semiconductor structure 200 .

[0198] In addition, the semiconductor device 1000 further includes a first pad 940 connected to an external electrical signal, and the first pad 940 can be connected to the power layer 930 or a peripheral circuit in the first semiconductor structure 200. The preparation process of the first pad 940 can adopt an existing conventional process and be prepared according to actual needs, which will not be described in detail here.

[0199] Optionally, the first pad 940 is disposed in the second semiconductor structure 300 to expand the spatial position of the interconnection structure layout in the semiconductor device 1000 and improve the flexibility of the interconnection structure layout.

[0200] Example 2

[0201] like Figure 2 As shown, as another option, in the semiconductor device 1000 , the memory cell 402 is closer to the first semiconductor structure 200 than the transistor 401 .

[0202] The following will be combined Figure 34-Figure 38 The specific process of each step of the above-mentioned preparation method 2000 in Example 2 is described in detail to form Figure 2 A semiconductor device 1000 is shown.

[0203] Since the contents involved in the method 2000 for preparing a semiconductor device described in the above embodiment 1 can be fully or partially applied to the method for preparing a semiconductor device described here (embodiment 2), the contents related or similar thereto are not described in detail. However, it can be understood by those skilled in the art that the semiconductor device 1000 (such as the semiconductor device 1000) can be formed according to the method 2000 for preparing a semiconductor device described in embodiment 1. Figure 1 ), the semiconductor device 1000 (as shown) can also be formed according to the semiconductor device manufacturing method 2000 described in Embodiment 2. Figure 2 Based on this, the semiconductor device manufacturing methods 2000 described in Embodiments 1 and 2 have the same beneficial effects as the semiconductor structure 1000, which will not be described in detail here.

[0204] Step S2

[0205] Fig.34 It is a cross-sectional schematic diagram of a structure after a storage unit 402 is formed according to a preparation method in one embodiment of the present application. Fig.35 It is a schematic cross-sectional view of a structure after transistor 401 is formed according to a preparation method in one embodiment of the present application. Fig.36 It is a cross-sectional schematic diagram of a structure after the second dielectric spacer layer 203 according to a preparation method in one embodiment of the present application.

[0206] Fig.37 It is a cross-sectional schematic diagram of a structure after a bit line 500 and a word line 600 are formed according to a manufacturing method in one embodiment of the application. Fig.38 for Fig.37 The intermediate shown is a schematic cross-sectional view of the structure formed after rotating 90° in the xy plane.

[0207] like Figure 2 , Figure 34-Figure 38 As shown, step S2 forms a second semiconductor structure directly in contact with the first semiconductor structure on the first semiconductor structure, wherein the second semiconductor structure includes a plurality of memory cells connected to the first peripheral circuit, which may for example include: forming a first dielectric layer 301 on the first semiconductor structure 200; forming a memory cell 402 on the first dielectric layer 301; forming a semiconductor body 411 connected to the memory cell 402 on the memory cell 402, wherein the semiconductor body 411 extends along the z direction.

[0208] Specifically, Fig.34 As shown, in one embodiment of the present application, the first dielectric layer 301 may be formed by one or more thin film deposition processes, and the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. The first dielectric layer 301 may include any suitable dielectric material, such as oxide, nitride, oxynitride or high-k dielectric. For example, the first dielectric layer 301 may include silicon oxide.

[0209] Optionally, the surface of the first dielectric layer 301 is processed by a planarization process using any suitable technology, such as grinding and / or chemical mechanical polishing, so that the processed first dielectric layer 301 has a relatively flat surface, so as to form a storage unit 402 on the flat surface. The structure and preparation process of the storage unit 402 can be prepared according to actual needs using existing conventional processes, and will not be described in detail in this application.

[0210] Alternatively, in some embodiments, taking DRAM as an example, the storage unit 402 may include a capacitor, and a plurality of storage units 402 may be arranged in a two-dimensional array. Alternatively, in some embodiments, taking a PCM element as an example, the storage unit 402 may include a unit having different resistivities in an amorphous phase and a crystalline phase to store a corresponding PCM. For example, a chalcogenide alloy is included. Alternatively, in some embodiments, taking FRAM as an example, the storage unit 402 may include a ferroelectric capacitor. This application is not limited thereto.

[0211] In addition, after forming the memory cell 402, an initial second dielectric spacer 203' covering at least the memory cell 402 may be formed by one or more thin film deposition processes, and the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0212] Optionally, the initial second dielectric spacer layer 203 ′ and the first dielectric spacer layer 202 may be made of the same material. In the case where they are made of the same material, there is no obvious boundary between the two.

[0213] It should be noted that in this article Figure 34-Figure 38 In the present invention, only the number and location of memory cells and peripheral circuits are shown exemplarily, but it can be understood that the memory cells and peripheral circuits shown in the figures and related contents of this article are only shown for the convenience of illustration, and this application is not limited thereto. Those skilled in the art can adjust the memory cells and peripheral circuits according to the concept of the present invention to achieve the same technical effect. In addition, in this article Fig.34 As well as in other figures in Embodiment 2, the cross-section of the intermediate body of the semiconductor device 1000 parallel to the xz plane and the cross-section parallel to the yz plane are respectively arranged on both sides of the dotted line for easy observation.

[0214] like Fig.34 and Fig.35 As shown, after forming the memory cell 402 , a semiconductor body 411 connected to the memory cell 402 may be formed on the memory cell 402 , wherein the semiconductor body 411 extends along the z direction.

[0215] Alternatively, the semiconductor body 411 may be formed by a thin film process. For example, the semiconductor body 411 may be an oxide semiconductor layer including at least one of indium, gallium, or zinc.

[0216] Optionally, a low temperature deposition process is used to form the semiconductor body 411. The process temperature T of the low temperature deposition process may satisfy: 200° C. ≤ T ≤ 300° C. For example, the semiconductor body 411 is formed using a low temperature material IGZO, which has a relatively high carrier mobility and a relatively low leakage current, thereby further saving the use of semiconductor materials, reducing the preparation cost and reducing the overall size of the semiconductor device.

[0217] In addition, if Fig.35 As shown, the single-gate transistor manufacturing process shown in Example 1 is adopted to form the gate structure 412 of the transistor 401. It should be noted that after forming the memory cell 402, the multi-gate transistor or full-ring gate transistor manufacturing process shown in Example 1 can also be adopted to form the transistor 401.

[0218] like Fig.35 and Fig.36 As shown, after the transistor 401 is formed, one or more thin film deposition processes can be used to fill the space between multiple gate structures 412 with a gate structure spacing dielectric layer, or the space remaining in the second opening after the gate structure 412 is formed. The thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. Thin film deposition process or any combination thereof.

[0219] Optionally, the gate structure spacing filling dielectric layer may include any suitable dielectric material, such as oxide, nitride, oxynitride or high-k dielectric. For example, the gate structure spacing filling dielectric layer may include silicon oxide. In addition, when the gate structure spacing filling dielectric layer and the initial second dielectric spacing layer 203' are made of the same material, there is no obvious boundary. After the gate structure spacing filling dielectric layer is formed, the gate structure spacing filling dielectric layer and the initial second dielectric spacing layer 203' remaining in the above step form the second dielectric spacing layer 203.

[0220] like Figure 36-Figure 38 As shown, after forming the gate structure 412, a bit line 500 and a word line 600 connected to the semiconductor body 411 may be formed. Optionally, the preparation process shown in Embodiment 1 may be adopted to form the bit line 500 and the word line 600, which will not be described in detail in this application.

[0221] in addition, Fig.39 It is a schematic diagram of the structure of a storage system 30000 according to one embodiment of the present application.

[0222] like Fig.39 As shown, at least one embodiment of another aspect of the present application further provides a storage system 30000. The storage system 30000 may include a semiconductor device 20000 and a controller 32000. The semiconductor device 20000 may be the same as the semiconductor device described in any embodiment above, and the present application will not repeat it. The semiconductor device 20000 may be a two-dimensional semiconductor device or a three-dimensional semiconductor device, or even a part of a two-dimensional semiconductor device or a part of a three-dimensional semiconductor device. The following will be described by taking a three-dimensional semiconductor device as an example.

[0223] As an option, the three-dimensional semiconductor device may include at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

[0224] The storage system 30000 may include a semiconductor device 20000 and a controller 32000. The semiconductor device 20000 may be the same as the semiconductor device described in any of the above embodiments, and this application will not repeat them. The controller 32000 may control the semiconductor device 20000 through a channel CH, and the semiconductor device 20000 may perform operations based on the control of the controller 32000 in response to a request from a host 31000. The semiconductor device 20000 may receive a command CMD and an address ADDR from the controller 32000 through the channel CH and access an area selected from a memory cell array in response to the address. In other words, the semiconductor device 20000 may perform an internal operation corresponding to the command on the area selected by the address.

[0225] In some embodiments, the three-dimensional storage system can be implemented as a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a storage device of the Personal Computer Memory Card International Association (PCMCIA) card type, a storage device of the peripheral component interconnect (PCI) type, a storage device of the high-speed PCI (PCI-E) type, a compact flash (CF) card, a smart media card or a memory stick, etc. The storage system provided in the present application has the same beneficial effects as the semiconductor device provided in the present application because the semiconductor device provided in the present application is provided, and no further description is given here.

[0226] Although an exemplary method and structure of manufacturing a semiconductor device are described herein, it is understood that one or more features may be omitted, replaced or added from the structure of the semiconductor device. In addition, the materials of each layer exemplified are merely exemplary.

[0227] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by the selected combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other to form a technical solution.

[0228] The above description is only a preferred implementation method of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other.

Claims

1. A semiconductor device, characterized in that: include: a first semiconductor structure; as well as A second semiconductor structure is disposed on one side of the first semiconductor structure along a first direction and directly contacts the first semiconductor structure. Wherein, the second semiconductor structure includes a plurality of memory cells, and the first semiconductor structure includes a first peripheral circuit connected to the plurality of memory cells; as well as In a plane perpendicular to the first direction, at least a portion of the first peripheral circuit is located directly below the plurality of memory cells, wherein the first peripheral circuit includes at least one of a driving structure and a sensing structure.

2. The semiconductor device according to claim 1, wherein The first semiconductor structure further includes a first interconnect structure, wherein the first interconnect structure is located on a side of the first peripheral circuit close to the second semiconductor structure along the first direction and connects the first semiconductor structure and the second semiconductor structure; and The second semiconductor structure further includes a power layer and a second interconnect structure, wherein the second interconnect structure connects the power layer and the first semiconductor structure.

3. The semiconductor device according to claim 2, wherein: The power layer is located at a side of the plurality of memory cells away from the first semiconductor structure along the first direction.

4. The semiconductor device according to claim 1, wherein: The semiconductor structure includes word lines and bit lines connected to the plurality of memory cells; and The driving structure includes a word line driving structure connected to the word line, and the sensing structure includes a bit line sensing amplification structure connected to the bit line.

5. The semiconductor device according to claim 4, wherein: The semiconductor structure further includes a word line contact structure connecting the word line and the word line driving structure, and a bit line contact structure connecting the bit line and the bit line sensing amplification structure. Wherein, at least one of the word line contact structure and the bit line contact structure extends along the first direction.

6. The semiconductor device according to claim 4, wherein: The bit line extends along a second direction, and the word line extends along a third direction, wherein the first direction, the second direction, and the third direction intersect each other, Wherein, in a plane parallel to the second direction and the third direction, the driving structure and the sensing structure are alternately arranged along the second direction or the third direction.

7. The semiconductor device according to claim 4, wherein: The bit line extends along a second direction, and the word line extends along a third direction, wherein the first direction, the second direction, and the third direction intersect each other, Wherein, in a plane parallel to the second direction and the third direction, the plurality of driving structures are symmetrically distributed; and / or The plurality of sensing structures are symmetrically distributed.

8. The semiconductor device according to claim 1, wherein At least one of the plurality of memory cells includes a vertical transistor and a memory cell connected to the vertical transistor, Wherein, along the first direction, the vertical transistor is close to the first semiconductor structure relative to the memory cell.

9. The semiconductor device according to claim 8, wherein: The vertical transistor includes at least one of a gate-all-around transistor, a multi-gate transistor, and a single-gate transistor.

10. The semiconductor device according to claim 8, wherein The vertical transistor includes a thin film transistor.

11. The semiconductor device according to claim 8, wherein The vertical transistor includes a semiconductor body extending along the first direction, wherein the semiconductor body includes an oxide semiconductor layer.

12. A method for preparing a semiconductor device, characterized in that: include: forming a first semiconductor structure on a substrate, wherein the first semiconductor structure comprises a first peripheral circuit, and the first peripheral circuit comprises at least one of a driving structure and a sensing structure; as well as forming a second semiconductor structure directly contacting the first semiconductor structure on the first semiconductor structure, wherein the second semiconductor structure includes a plurality of memory cells connected to the first peripheral circuit, Wherein, in a plane parallel to the substrate, the first peripheral circuit is located directly below the plurality of memory cells.

13. The method according to claim 12, wherein: Forming a second semiconductor structure on the first semiconductor structure and in direct contact with the first semiconductor structure includes: forming a first dielectric layer on the first semiconductor structure; forming a storage unit on the first dielectric layer; forming a semiconductor body connected to the memory cell on the memory cell, The semiconductor body extends along a first direction perpendicular to the substrate.

14. The method according to claim 12, wherein: Forming a second semiconductor structure on the first semiconductor structure and in direct contact with the first semiconductor structure includes: forming a bit line on the first semiconductor structure; forming a semiconductor body and a gate structure connected to the semiconductor body on the bit line, wherein the semiconductor body extends in a first direction perpendicular to the substrate; and A memory cell connected to the semiconductor body is formed on the semiconductor body.

15. The method according to claim 13 or 14, wherein: The semiconductor body is formed by a low temperature deposition process, Wherein, the process temperature T of the low temperature deposition process satisfies: 200℃≤T≤300℃。 16. A semiconductor device, characterized in that: include: a first semiconductor structure; as well as a semiconductor body, arranged on one side of the first semiconductor structure along a first direction, wherein the semiconductor body comprises a first portion and a second portion connected to each other; The first portion extends along the first direction; and The second portion extends along a direction perpendicular to the first direction and directly contacts the first semiconductor structure.

17. The semiconductor device according to claim 16, wherein: The first semiconductor structure includes a first peripheral circuit located directly below the plurality of semiconductor bodies, wherein the first peripheral circuit includes at least one of a driving structure and a sensing structure.

18. The semiconductor device according to claim 17, wherein: The semiconductor structure further includes a first interconnect structure, a power layer, and a second interconnect structure, Wherein, the first interconnect structure is located on a side of the first peripheral circuit close to the semiconductor body along the first direction; The power layer is located at a side of the semiconductor body away from the first semiconductor structure along the first direction; and The second interconnect structure connects the power layer and the first semiconductor structure.

19. The semiconductor device according to claim 16, wherein: The semiconductor structure further includes a gate structure and a bit line, Wherein, the gate structure is located at the first portion and the second portion; and The bit line is located on a side of the second portion away from the first portion, or the bit line is located on a side of the first portion away from the second portion.

20. The semiconductor device according to claim 19, wherein In a second direction intersecting the first direction, a plurality of adjacent gate structures are distributed in a mirror-symmetrical manner along the first direction.

21. The semiconductor device according to claim 16, wherein: In a second direction intersecting the first direction, a plurality of adjacent semiconductor bodies are distributed in a mirror-symmetrical manner along the first direction.

22. The semiconductor device according to claim 19, wherein The semiconductor structure further includes a word line connected to the gate structure and extending along a third direction, wherein the first direction and the third direction intersect each other; and The first semiconductor structure includes a first peripheral circuit, wherein the first peripheral circuit includes at least one of a driving structure and a sensing structure, The driving structure includes a word line driving structure connected to the word line, and the sensing structure includes a bit line sensing amplification structure connected to the bit line.

23. The semiconductor device according to claim 22, wherein: The semiconductor structure further includes a word line contact structure connecting the word line and the word line driving structure, and a bit line contact structure connecting the bit line and the bit line sensing amplification structure. Wherein, at least one of the word line contact structure and the bit line contact structure extends along the first direction.

24. The semiconductor device according to claim 22, wherein: In a plane parallel to the second direction and the third direction, the driving structure and the sensing structure are alternately arranged along the second direction or the third direction, wherein the first direction, the second direction and the third direction intersect each other.

25. The semiconductor device according to claim 22, wherein: In a plane parallel to the second direction and the third direction, the plurality of driving structures are symmetrically distributed; and / or The plurality of sensing structures are symmetrically distributed, Wherein, the first direction, the second direction and the third direction intersect with each other.

26. The semiconductor device according to any one of claims 16 to 25, wherein: The semiconductor body includes an oxide semiconductor layer.

27. A storage system, characterized in that: The storage system comprises a controller and the semiconductor device according to any one of claims 1 to 11 or the semiconductor device according to any one of claims 16 to 26, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

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