One-time programmable memory structure and memory array

Abstract

The invention discloses a one-time programmable memory structure and a memory array. The one-time programmable memory structure includes a semiconductor substrate of a first conductivity type and a fin disposed on the semiconductor substrate. The fin extends along a first direction, the fin comprises a first part and a second part adjacent to the first part, and the first part and the second part have different cross section profiles. The gate extends on the fin along a second direction. The gate partially overlaps the first portion of the fin and partially overlaps the second portion of the fin.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a one-time programmable (OTP) memory structure and a memory array. Background Art

[0002] After a one-time programmable (OTP) memory cell is programmed once, the storage state of the OTP memory cell is determined, and the storage state of the OTP memory cell cannot be changed.

[0003] Basically, OTP memory cells can be divided into fuse OTP memory cells and anti-fuse OTP memory cells. For example, when the anti-fuse OTP memory cell is not programmed, it is in a high impedance storage state; conversely, when the anti-fuse OTP memory cell is programmed, it is in a low impedance storage state. In addition, when the fuse OTP memory cell is not programmed, it is in a low impedance storage state; conversely, when the fuse OTP memory cell is programmed, it is in a high impedance storage state. Summary of the invention

[0004] The main purpose of the present invention is to provide an improved single transistor (1T) one-time programmable (OTP) memory structure and memory array, which is compatible with 14 nanometer or below fin field effect transistor (finFET) manufacturing process and has better programming efficiency.

[0005] On one hand, the present invention provides a one-time programmable memory structure, comprising: a semiconductor substrate having a first conductivity type; a fin disposed on the semiconductor substrate, wherein the fin extends along a first direction, wherein the fin includes a first portion and a second portion adjacent to the first portion, and wherein the first portion and the second portion have different cross-sectional profiles; and a gate extending on the fin along a second direction, wherein the gate partially overlaps the first portion of the fin and partially overlaps the second portion of the fin.

[0006] According to an embodiment of the present invention, the one-time programmable memory structure also includes: a first gate dielectric layer located between the first portion of the fin and the gate; and a second gate dielectric layer located between the second portion of the fin and the gate, wherein the first gate dielectric layer and the second gate dielectric layer have different thicknesses.

[0007] According to an embodiment of the present invention, the first gate dielectric layer is thicker than the second gate dielectric layer.

[0008] According to an embodiment of the present invention, a step difference is formed between the first gate dielectric layer and the second gate dielectric layer.

[0009] According to an embodiment of the present invention, the first gate dielectric layer is an input / output (I / O) oxide layer with a thickness of 25-45 angstroms, and the second gate dielectric layer is a core oxide layer with a thickness of 5-25 angstroms.

[0010] According to an embodiment of the present invention, the first portion of the fin has a first top width and the second portion of the fin has a second top width, wherein the first top width is greater than the second top width.

[0011] According to an embodiment of the present invention, the first portion of the fin has the first conductivity type, and the second portion of the fin has a second conductivity type opposite to the first conductivity type.

[0012] According to an embodiment of the present invention, the first conductivity type is P type and the second conductivity type is N type.

[0013] According to an embodiment of the present invention, the first portion of the fin has a rectangular cross-sectional profile, and wherein the second portion of the fin has a tapered cross-sectional profile and its sidewall surface has at least two different slopes.

[0014] According to an embodiment of the present invention, the gate is a metal gate.

[0015] On the other hand, the present invention provides a one-time programmable memory array, comprising: a semiconductor substrate having a first conductivity type; a plurality of fins arranged on the semiconductor substrate, wherein the plurality of fins extend along a first direction, wherein each of the plurality of fins comprises a first portion and a second portion adjacent to the first portion, and wherein the first portion and the second portion have different cross-sectional profiles; and at least one gate extending along a second direction on the plurality of fins, wherein the at least one gate partially overlaps the first portion and partially overlaps the second portion.

[0016] According to an embodiment of the present invention, the one-time programmable memory array further includes: a first gate dielectric layer located between the first portion and the at least one gate; and a second gate dielectric layer located between the second portion and the at least one gate, wherein the first gate dielectric layer and the second gate dielectric layer have different thicknesses.

[0017] According to an embodiment of the present invention, the first gate dielectric layer is thicker than the second gate dielectric layer.

[0018] According to an embodiment of the present invention, a step difference is formed between the first gate dielectric layer and the second gate dielectric layer.

[0019] According to an embodiment of the present invention, the first gate dielectric layer is an input / output (I / O) oxide layer with a thickness of 25-45 angstroms, and the second gate dielectric layer is a core oxide layer with a thickness of 5-25 angstroms.

[0020] According to an embodiment of the present invention, the first portion has a first top width and the second portion has a second top width, wherein the first top width is greater than the second top width.

[0021] According to an embodiment of the present invention, the first portion has the first conductivity type, and the second portion has a second conductivity type opposite to the first conductivity type.

[0022] According to an embodiment of the present invention, the first conductivity type is P type and the second conductivity type is N type.

[0023] According to an embodiment of the present invention, the first portion of the fin has a rectangular cross-sectional profile, and wherein the second portion of the fin has a tapered cross-sectional profile and its sidewall surface has at least two different slopes.

[0024] According to an embodiment of the present invention, the at least one gate is a metal gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of a one-time programmable memory structure according to an embodiment of the present invention;

[0026] Figure 2 For along Figure 1 A schematic cross-sectional view shown by the midline II';

[0027] Figure 3 For along Figure 1 A schematic cross-sectional view shown by the midline II-II';

[0028] Figure 4 For along Figure 1 A schematic cross-sectional view shown along the median tangent line III-III';

[0029] Figure 5 FIG. 1 is a schematic diagram of a partial layout of a one-time programmable memory array according to another embodiment of the present invention.

[0030] Explanation of symbols

[0031] 1 One-time programmable memory structure

[0032] 100 Semiconductor substrate

[0033] BL1a, BL1b, BL2a, BL2b bit lines

[0034] C1-C4 unit storage cell

[0035] CMD contact strip cutting area

[0036] CT1, CT2 vias

[0037] D1 First direction

[0038] D2 Second direction

[0039] DR Counter-doped capacitor region

[0040] HK High dielectric constant material layer

[0041] FI-F4 Fins

[0042] FP1 Part 1

[0043] FP2 Part 2

[0044] G Gate

[0045] GOX1 First gate dielectric layer

[0046] GOX2 Second gate dielectric layer

[0047] MD1-MD3 contact strip

[0048] MR One-Time Programmable Memory Array

[0049] NR N-type doped region

[0050] S1 First side wall surface

[0051] S2 Second side wall surface

[0052] SH Step Drop

[0053] SP Spacer

[0054] ST Trench Isolation Structure

[0055] w1 first top width

[0056] w2 Second top width

[0057] WL1, WL2 word lines

[0058] θ1, θ2 angle DETAILED DESCRIPTION

[0059] In the following, the details will be described with reference to the accompanying drawings, which also constitute part of the detailed description of the specification and are illustrated in a specific way that the embodiment can be implemented. The following embodiments have been described in sufficient detail to enable a person skilled in the art to implement them.

[0060] Of course, other embodiments may be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be considered as limiting, but rather, the embodiments included therein will be defined by the appended claims.

[0061] See also Figures 1 to 4 ,in, Figure 1 FIG. 1 is a schematic diagram of a one-time programmable memory structure according to an embodiment of the present invention. Figure 2 For along Figure 1 The cross-sectional view shown by the midline I-I', Figure 3 For along Figure 1 The cross-sectional view shown by the midline II-II', Figure 4 For along Figure 1 Schematic cross-sectional view shown by the midline III-III'.

[0062] like Figures 1 to 4 As shown, the one-time programmable memory structure 1 includes a semiconductor substrate 100 of a first conductivity type, for example, the first conductivity type is a P type, and the semiconductor substrate 100 may be a silicon substrate. Fins F1 and F2 are provided on the semiconductor substrate 100, wherein the fins F1 and F2 extend along a first direction D1. According to an embodiment of the present invention, a trench insulating structure ST is further provided on the semiconductor substrate 100, and the fins F1 and F2 protrude from the top surface of the trench insulating structure ST.

[0063] According to the embodiment of the present invention, each of the fins F1 and F2 includes a first portion FP1 and a second portion FP2 adjacent to the first portion FP1. According to the embodiment of the present invention, the first portion FP1 has a first conductivity type, and the second portion FP2 has a second conductivity type opposite to the first conductivity type.

[0064] According to an embodiment of the present invention, the first portion FP1 and the second portion FP2 have different cross-sectional profiles. Figure 2 As shown, for example, the first portion FP1 of the fins F1 and F2 has a rectangular (or nearly rectangular) cross-sectional profile. Figure 3 As shown, for example, the second portions FP2 of the fins F1 and F2 have a pointed tapered cross-sectional profile.

[0065] According to an embodiment of the present invention, Figure 3As shown, the sidewall surface of the second portion FP2 of the fins F1 and F2 has at least two different slopes, for example, a first sidewall surface S1 having a first slope and a second sidewall surface S2 having a second slope, wherein the first slope is less than the second slope. According to an embodiment of the present invention, the first sidewall surface S1 is connected to the second sidewall surface S2. According to an embodiment of the present invention, the first sidewall surface S1 is on the top and the second sidewall surface S2 is on the bottom. According to an embodiment of the present invention, for example, the angle θ1 between the first sidewall surface S1 and the horizontal plane is about 78°, and the angle θ2 between the second sidewall surface S2 and the horizontal plane is about 83°.

[0066] According to an embodiment of the present invention, Figure 2 and Figure 3 As shown, the first portion FP1 of the fins F1 and F2 has a first top width w1 and the second portion FP2 of the fins F1 and F2 has a second top width w2 , wherein the first top width w1 is greater than the second top width w2 .

[0067] like Figure 1 As shown, the semiconductor substrate 100 further includes a counter doping capacitor region DR. A second conductive type dopant, for example, an N-type dopant, is injected into the counter doping capacitor region DR to form an N-type doping region. According to an embodiment of the present invention, the second portion FP2 of the fins F1 and F2 is located in the counter doping capacitor region DR. Therefore, the second portion FP2 of the fins F1 and F2 has a second conductive type, for example, an N-type. For example, Figure 4 As shown, the second portion FP2 of the fins F1 and F2 has an N-type doped region NR.

[0068] According to an embodiment of the present invention, the one-time programmable memory structure 1 further includes a gate G extending along a second direction D2 on the fins F1 and F2, wherein the gate G partially overlaps a first portion FP1 of the fins F1 and F2 and partially overlaps a second portion FP2 of the fins F1 and F2. Figure 1 As shown, the gate G covers the boundary between the first portion FP1 and the second portion FP2.

[0069] According to an embodiment of the present invention, the gate G is, for example, a metal gate. According to an embodiment of the present invention, the gate G may further include a high dielectric constant material layer HK. According to an embodiment of the present invention, Figure 4 As shown, a spacer SP may be disposed on the sidewall of the gate G. The detailed structure of the gate G is the same as the gate structure of a general fin field effect transistor, so it will not be described in detail.

[0070] According to an embodiment of the present invention, the one-time programmable memory structure 1 further comprises a first gate dielectric layer GOX1, located between the first portion FP1 of the fins F1 and F2 and the gate G. According to an embodiment of the present invention, the one-time programmable memory structure 1 further comprises a second gate dielectric layer GOX2, located between the second portion FP2 of the fins F1 and F2 and the gate G, wherein the first gate dielectric layer GOX1 and the second gate dielectric layer GOX2 have different thicknesses. According to an embodiment of the present invention, the first gate dielectric layer GOX1 is thicker than the second gate dielectric layer GOX2.

[0071] According to an embodiment of the present invention, for example, the first gate dielectric layer GOX1 can be an input / output (I / O) oxide layer (formed simultaneously with the gate dielectric layer of the I / O element) and have a thickness of 25 to 45 angstroms, and wherein the second gate dielectric layer can be a core oxide layer (formed simultaneously with the gate dielectric layer of the core logic element) and have a thickness of 5 to 25 angstroms.

[0072] According to an embodiment of the present invention, a step height SH is provided between the first gate dielectric layer GOX1 and the second gate dielectric layer GOX2 having different thicknesses. According to an embodiment of the present invention, the step height SH can generate a corner structure or a sharper corner at the bottom of the gate G, and the corner structure can generate a higher electric field during programming operation, thereby improving programming efficiency.

[0073] See also Figure 5 , which is a schematic diagram of a partial layout of a one-time programmable memory array according to another embodiment of the present invention. To simplify the description, Figure 5 The one-time programmable memory array MR in FIG. 1 only shows a 2×2 memory array including four unit memory cells C1-C4. The four unit memory cells C1-C4 are in a mirror configuration, for example, the unit memory cell C1 and the unit memory cell C2 on its right are mirror-symmetric structures, and the unit memory cell C3 and the unit memory cell C4 on its right are mirror-symmetric structures. Figure 5 The structures of the unit storage cells C1-C4 in Figure 1 to Figure 4 described.

[0074] like Figure 5 As shown, a one-time programmable memory array MR is formed on a semiconductor substrate 100, which has a first conductivity type, for example, a P type. A plurality of fins, for example, fins F1-F4, are arranged on the semiconductor substrate 100, wherein the fins F1-F4 extend along a first direction D1. Each of the fins F1-F4 also includes a first portion FP1 and a second portion FP2 adjacent to the first portion FP1, as shown in FIG. Figures 1 to 4 As shown.

[0075] Likewise, the first portion FP1 and the second portion FP2 have different cross-sectional profiles, the details being similar to those of Figures 1 to 4 According to an embodiment of the present invention, the first portion FP1 has a first conductivity type, for example, P type, and the second portion FP2 has a second conductivity type, for example, N type. According to an embodiment of the present invention, the first portion FP1 has a rectangular cross-sectional profile, as shown in FIG. Figure 2 As shown, the second portion FP2 has a tapered cross-sectional profile and its sidewall surface has at least two different slopes, as shown in FIG. Figure 3 As shown.

[0076] According to an embodiment of the present invention, Figure 2 As shown, for example, the first portion FP1 has a rectangular (or nearly rectangular) cross-sectional profile. Figure 3 As shown, for example, the second portion FP2 has a pointed conical cross-sectional profile.

[0077] According to an embodiment of the present invention, Figure 3 As shown, the sidewall surface of the second portion FP2 has at least two different slopes, for example, a first sidewall surface S1 having a first slope and a second sidewall surface S2 having a second slope, wherein the first slope is smaller than the second slope. According to an embodiment of the present invention, the first sidewall surface S1 directly connects to the second sidewall surface S2. According to an embodiment of the present invention, the first sidewall surface S1 is on top, and the second sidewall surface S2 is below. According to an embodiment of the present invention, for example, an angle θ1 between the first sidewall surface S1 and the horizontal plane is about 78°, and an angle θ2 between the second sidewall surface S2 and the horizontal plane is about 83°.

[0078] According to an embodiment of the present invention, Figure 2 and Figure 3 As shown, the first portion FP1 has a first top width w1 and the second portion FP2 has a second top width w2 , wherein the first top width w1 is greater than the second top width w2 .

[0079] like Figure 5 As shown, the one-time programmable memory array MR further includes a counter doping capacitor region DR. A second conductivity type dopant, for example, an N-type dopant, is injected into the counter doping capacitor region DR to form an N-type doping region. According to an embodiment of the present invention, the second portion FP2 is located in the counter doping capacitor region DR, and therefore, the second portion FP2 has a second conductivity type, for example, an N-type. For example, Figure 4 As shown, the second portion FP2 has an N-type doping region NR.

[0080] According to an embodiment of the present invention, Figure 5As shown, a plurality of contact strips, for example, contact strips MD1-MD3, may be provided along the second direction D2 on the semiconductor substrate 100 to partially electrically connect the fins F1-F4. According to an embodiment of the present invention, the plurality of contact strips may be formed by a zeroth metal layer (or M0 layer). According to an embodiment of the present invention, a contact strip cutting region CMD may be provided along the first direction D1 on the semiconductor substrate 100 to cut off the contact strip MD.

[0081] According to an embodiment of the present invention, Figure 5 As shown, a plurality of word lines (or gates), for example, word lines WL1 and WL2, may be provided on the semiconductor substrate 100, extending on the fins F1-F4 along the second direction D2, wherein the word lines WL1 and WL2 partially overlap the first portion FP1 and partially overlap the second portion FP2. According to an embodiment of the present invention, the word lines WL1 and WL2 are, for example, metal gates.

[0082] According to an embodiment of the present invention, Figure 2 to Figure 4 As shown, the one-time programmable memory array MR further includes a first gate dielectric layer GOX1, located between the first portion FP1 and the gate G, and a second gate dielectric layer GOX2, located between the second portion FP2 and the gate G. The first gate dielectric layer GOX1 and the second gate dielectric layer GOX2 have different thicknesses, for example, the first gate dielectric layer GOX1 is thicker than the second gate dielectric layer GOX2. According to an embodiment of the present invention, the first gate dielectric layer GOX1 may be an input / output oxide layer with a thickness of 25 to 45 angstroms, and the second gate dielectric layer may be a core oxide layer with a thickness of 5 to 25 angstroms. There is a step height SH between the first gate dielectric layer GOX1 and the second gate dielectric layer GOX2 having different thicknesses.

[0083] According to an embodiment of the present invention, the one-time programmable memory array MR further includes a plurality of bit lines, for example, bit lines BL1a, BL1b, BL2a, and BL2b, extending along a first direction D1. According to an embodiment of the present invention, the bit lines BL1a, BL1b, BL2a, and BL2b may be formed in a first metal layer (or M1 layer). For example, in a unit memory cell C1, the bit line BL1a may be electrically connected to a contact band MD1 below via a via CT1, and then transmit a voltage signal to a drain or source of the unit memory cell C1, while the bit line BL1b may be electrically connected to a contact band MD2 below via a via CT2, and then transmit a voltage signal to a doped region of a second portion FP2 of the unit memory cell C1.

[0084] The improved one-time programmable memory structure of the present invention is compatible with the fin field effect transistor (finFET) manufacturing process of 14 nanometers or less and has better programming efficiency. In addition, the one-time programmable memory array of the present invention has better programming efficiency. Through the mirror-symmetric design and the contact band cutting area CMD, it can also have the effect of reducing the unit storage cell area, so that the memory device can have a higher memory density.

[0085] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A one-time programmable memory structure comprising: A semiconductor substrate having a first conductivity type; The fin is disposed on the semiconductor substrate, wherein: The fin extends along a first direction, wherein the fin includes a first portion and a second portion adjacent to the first portion, and further wherein the first portion and the second portion have different cross-sectional profiles; and A gate extends on the fin along a second direction, wherein the gate partially overlaps the first portion of the fin and partially overlaps the second portion of the fin.

2. The one-time programmable memory structure as claimed in claim 1, wherein: Also includes: a first gate dielectric layer disposed between the first portion of the fin and the gate; and The second gate dielectric layer is located between the second portion of the fin and the gate, wherein the first gate dielectric layer and the second gate dielectric layer have different thicknesses.

3. The one-time programmable memory structure as claimed in claim 2, wherein: The first gate dielectric layer is thicker than the second gate dielectric layer.

4. The one-time programmable memory structure as claimed in claim 2, wherein: A step height is formed between the first gate dielectric layer and the second gate dielectric layer.

5. The one-time programmable memory structure as claimed in claim 2, wherein: The first gate dielectric layer is an input / output (I / O) oxide layer with a thickness of 25-45 angstroms, and the second gate dielectric layer is a core oxide layer with a thickness of 5-25 angstroms.

6. The one-time programmable memory structure of claim 1, wherein: The first portion of the fin has a first top width and the second portion of the fin has a second top width, wherein the first top width is greater than the second top width.

7. The one-time programmable memory structure of claim 1, wherein: The first portion of the fin has the first conductivity type, and the second portion of the fin has a second conductivity type opposite to the first conductivity type.

8. The one-time programmable memory structure of claim 7, wherein: The first conductivity type is P type and the second conductivity type is N type.

9. The one-time programmable memory structure of claim 1, wherein: The first portion of the fin has a rectangular cross-sectional profile, and the second portion of the fin has a tapered cross-sectional profile and a sidewall surface thereof has at least two different slopes.

10. The one-time programmable memory structure of claim 1, wherein: The gate is a metal gate.

11. A one-time programmable memory array comprising: A semiconductor substrate having a first conductivity type; A plurality of fins are arranged on the semiconductor substrate, wherein: The plurality of fins extend along a first direction, wherein each of the plurality of fins comprises a first portion and a second portion adjacent to the first portion, and wherein the first portion and the second portion have different cross-sectional profiles; and At least one gate extends on the plurality of fins along a second direction, wherein the at least one gate partially overlaps the first portion and partially overlaps the second portion.

12. The one-time programmable memory array of claim 11, wherein: Also includes: A first gate dielectric layer is located between the first portion and the at least one gate; and The second gate dielectric layer is located between the second portion and the at least one gate, wherein the first gate dielectric layer and the second gate dielectric layer have different thicknesses.

13. The one-time programmable memory array of claim 12, wherein: The first gate dielectric layer is thicker than the second gate dielectric layer.

14. The one-time programmable memory array of claim 12, wherein: A step height is formed between the first gate dielectric layer and the second gate dielectric layer.

15. The one-time programmable memory array of claim 12, wherein: The first gate dielectric layer is an input / output (I / O) oxide layer with a thickness of 25-45 angstroms, and the second gate dielectric layer is a core oxide layer with a thickness of 5-25 angstroms.

16. The one-time programmable memory array of claim 11, wherein: The first portion has a first top width and the second portion has a second top width, wherein the first top width is greater than the second top width.

17. The one-time programmable memory array of claim 11, wherein: The first portion has the first conductivity type, and the second portion has a second conductivity type opposite to the first conductivity type.

18. The one-time programmable memory array of claim 17, wherein: The first conductivity type is P type and the second conductivity type is N type.

19. The one-time programmable memory array of claim 11, wherein: The first portion of the fin has a rectangular cross-sectional profile, and the second portion of the fin has a tapered cross-sectional profile and a sidewall surface thereof has at least two different slopes.

20. The one-time programmable memory array of claim 11, wherein: The at least one gate is a metal gate.

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