Non-volatile memory cell with programmable and erasable single polysilicon layer

Abstract

The invention relates to a nonvolatile memory cell with a programmable and erasable single polycrystalline silicon layer. In a memory cell, a plurality of doped regions are completed using different fabrication processes. The memory cell comprises a selection transistor and a floating gate transistor, and the channel length of the floating gate transistor is smaller than the channel length of the selection transistor. In the invention, the steps of the doping process are modified, so that different parameters and characteristics exist between a plurality of doped regions in the selection transistor and the floating gate transistor, and the channel resistance value of the floating gate transistor is greater than the channel resistance value of the selection transistor.

Description

Technical Field

[0001] The present invention relates to a nonvolatile memory, and in particular to a programmable and erasable single polysilicon layer nonvolatile memory cell. Background Art

[0002] As is known to all, a memory cell of a non-volatile memory includes a memory unit. For example, the memory unit may be a floating gate transistor. The storage state of the memory cell is determined by the amount of charge stored in the floating gate of the floating gate transistor.

[0003] In order to be compatible with the manufacturing process of traditional standard CMOS transistors, single-poly floating gate transistors can be designed in the memory cells of non-volatile memory today. The floating gate transistor can be combined with other electronic devices to form a single-poly nonvolatile memory cell.

[0004] U.S. Patent No. 8,941,167 discloses a variety of erasable programmable single-poly nonvolatile memories. Figure 1A , which shows a top view of a memory cell of a conventional single polysilicon layer non-volatile memory. Figure 1B FIG. 4 is a cross-sectional view of a memory cell of a conventional single polysilicon layer non-volatile memory along the dotted line a1 - a1 . Figure 1C FIG. 4 is a cross-sectional view of a memory cell of a conventional single polysilicon layer non-volatile memory along the dotted line b1 - b2 . Figure 1D FIG. 1 is an equivalent circuit of a memory cell of a conventional single polysilicon layer non-volatile memory.

[0005] like Figures 1A to 1DAs shown, the N-type well region NW includes three p-type doped regions 131, 132, and 133, and two selection gates 134 and a floating gate 136 composed of a polysilicon layer are included on the surface between the three p-type doped regions 131, 132, and 133. In addition, the P-type well region PW includes an n-type doped region 138. The floating gate 136 extends outward through the surface of the isolation structure 139 and is adjacent to the n-type doped region 138. The isolation structure 139 is a shallow trench isolation (STI) structure.

[0006] The conventional memory cell includes: a selection transistor M S , floating gate transistor M F With n-type transistor M n Among them, the selection transistor M S With floating gate transistor M F It is a p-type transistor, fabricated in an N-type well region NW. n Made in P-type well area PW.

[0007] Select transistor M S It is composed of a p-type doped region 131, a p-type doped region 132, a select gate 134 and an N-type well region NW. F The n-type transistor M is composed of a p-type doping region 132, a p-type doping region 133, a floating gate 136 and an N-type well region NW. n It is composed of a floating gate 136 and an assist gate region 135. In addition, the erase gate region 135 includes a P-type well region PW and an n-type doped region 138.

[0008] like Figure 1D As shown, the selection transistor M S The select gate 134 is connected to a select gate voltage V SG , select transistor M S The first drain / source terminal receives the source line voltage V SL , select transistor M S The body terminal receives the N-type well voltage V NW Floating gate transistor M F The first drain / source terminal is connected to the selection transistor M S The second drain / source terminal of the floating gate transistor M F The second drain / source terminal receives the bit line voltage V BL , floating gate transistor M FThe body terminal receives the N-type well voltage V NW .

[0009] The n-type doped region 138 can be regarded as an n-type transistor M n The two drain / source terminals of the n-type transistor M are connected to each other. n The body end receives the P-type well voltage V PW . n-type transistor M n The gate terminal of the n-type transistor M is connected to the floating gate 136. n The two drain / source terminals receive the erase line voltage V EL Furthermore, the n-type transistor M n From the connection relationship of the n-type transistor M n It is equivalent to a metal-oxide-semiconductor capacitor (hereinafter referred to as MOS capacitor).

[0010] From the above description, it can be seen that the conventional memory cell is composed of two transistors M S 、M F It is composed of a capacitor and is called a 2T1C memory cell.

[0011] Furthermore, a suitable bias voltage is provided as the select gate voltage V SG , source line voltage V SL , bit line voltage V BL , Erase line voltage V EL , N-type well voltage V NW , P-type well voltage V PW , non-volatile memory cells can be programmed, erased or read.

[0012] Basically, it is known that during the doping steps of manufacturing this type of memory cell, all the p-type doped regions 131 , 132 , 133 are completed through the same manufacturing process, so the p-type doped regions 131 , 132 , 133 have the same parameters and characteristics.

[0013] Similarly, in other memory cells with different structures disclosed in US Pat. No. 8,941,167, all p-type doped regions are also completed using the same manufacturing process, which will not be repeated here. Summary of the invention

[0014] The present invention relates to a programmable and erasable single polysilicon layer non-volatile memory cell, comprising: an isolation structure formed on a semiconductor substrate, and the isolation structure divides the surface of the semiconductor substrate into a first area and a second area; a first well area formed below the surface of the first area of ​​the semiconductor substrate; a second well area formed below the surface of the second area of ​​the semiconductor substrate; a first gate structure and a second gate structure formed on the surface of the first area, and the first gate structure and the second gate structure divide the surface of the first area into a first merged doping area, a second merged doping area and a third merged doping area; and a fourth merged doping area formed below the surface of the second area and located on one side of the second gate structure; wherein the first merged doping area The doped region is located on a first side of the first gate structure, the second merged doped region is located between a second side of the first gate structure and a first side of the second gate structure, and the third merged doped region is located on a second side of the second gate structure; wherein the second gate structure extends outward through the surface of the isolation structure and to the second region and covers a portion of the second region; wherein the first merged doped region, the first gate structure and the second merged doped region form a selection transistor; the second merged doped region, the second gate structure and the third merged doped region form a floating gate transistor; the second gate structure and the fourth merged doped region form a first metal oxide semiconductor capacitor; and a channel resistance value of the floating gate transistor is greater than a channel resistance value of the selection transistor.

[0015] In order to better understand the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings: BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1A A top view of a memory cell of a conventional single polysilicon layer non-volatile memory;

[0017] Figure 1B is a cross-sectional view of a memory cell of a conventional single polysilicon layer non-volatile memory along a1-a1 dotted line;

[0018] Figure 1C is a cross-sectional view of a memory cell of a conventional single polysilicon layer non-volatile memory along the dotted line b1 - b2;

[0019] Figure 1D is an equivalent circuit of a memory cell of a known single polysilicon layer non-volatile memory;

[0020] FIG. 2A to FIG. 2H The manufacturing process of the memory cell according to the first embodiment of the present invention;

[0021] Fig.2I is an equivalent circuit diagram of a memory cell according to a first embodiment of the present invention;

[0022] Figure 2J to Figure 2M A bias table and an operation diagram of the memory cell in the first embodiment of the present invention for performing programming, erasing and reading operations;

[0023] FIG. 3A to FIG. 3C This is a first modified example of the doping step of the present invention;

[0024] FIG. 4A to FIG. 4C This is a second modified example of the doping step of the present invention;

[0025] FIG. 5A to FIG. 5C This is a third modified example of the doping step of the present invention;

[0026] Figure 6 This is a fourth modified example of the doping step of the present invention;

[0027] FIG. 7A to FIG. 7G The manufacturing process of the memory cell according to the second embodiment of the present invention; and

[0028] Figure 7H FIG. 4 is an equivalent circuit diagram of a memory cell according to a second embodiment of the present invention.

[0029]

Explanation of symbols

[0030] 131, 132, 133: p-type doped regions

[0031] 134: Select gate

[0032] 136: floating gate

[0033] 135: Erase gate region

[0034] 138: n-type doped region

[0035] 139, 202, 702: Isolation structure

[0036] 203, 205, 207, 209, 703, 705: gate dielectric layer

[0037] 213, 215, 217, 219, 713, 715: polysilicon gate layer

[0038] 223, 225, 227, 229, 723, 725: Gate structure

[0039] 240, 250, 740, 750: Mask

[0040] 241, 242, 243, 251, 252, 341, 343, 351, 352, 441, 442, 443, 452, 541, 542, 543, 544, 741, 742, 743, 751, 752: n-type lightly doped drain region

[0041] 248, 258: gap wall

[0042] 261, 262, 263, 264, 761, 762, 763, 764: n-type ion implantation area

[0043] 271, 272, 273, 274, 771, 772, 773, 774: Merged n-type doped regions

[0044] 280:Metal layer

[0045] 561, 562: Counterattack penetration planting area

[0046] 602: p-type channel doping region DETAILED DESCRIPTION

[0047] The present invention proposes a single polysilicon layer non-volatile memory cell. In the memory cell, multiple doping regions are completed using different manufacturing processes. In other words, the present invention modifies the steps of the doping process technology so that the multiple doping regions have different parameters and characteristics, and the channel resistance value of the floating gate transistor is greater than the channel resistance value of the selection transistor. The following is a detailed description.

[0048] Please refer to FIG. 2A to FIG. 2H , which illustrates the manufacturing process of the memory cell according to the first embodiment of the present invention. Fig.2I FIG. 1 is an equivalent circuit diagram of a memory cell according to the first embodiment of the present invention. In the following description, a single polysilicon layer non-volatile memory cell is referred to as a memory cell.

[0049] like Figure 2A As shown, an isolation structure 202 is formed on the semiconductor substrate sub, and region A and region B are defined. That is, the semiconductor substrate sub is covered by the isolation structure 202, and the surface of the semiconductor substrate sub is exposed only in regions A and B. Next, a well region forming step is performed to form a first well region, such as a P-type well region PW, below region A on the surface of the substrate sub. In addition, a second well region can be formed below region B on the surface of the substrate sub. The second well region can be a lightly doped P-type well region LPW, a P-type well region PW, or an N-type well region NW.

[0050] like Figure 2BAs shown, four gate structures 223, 225, 227, and 229 are formed on the surface of the semiconductor substrate sub. The gate structure 223 includes a gate dielectric layer 203 and a polysilicon gate layer 213. The gate structure 225 includes a gate dielectric layer 205 and a polysilicon gate layer 215. The gate structure 227 includes a gate dielectric layer 207 and a polysilicon gate layer 217. The gate structure 229 includes a gate dielectric layer 209 and a polysilicon gate layer 219. The gate dielectric layers 203, 205, 207, and 209 are located between the polysilicon gate layers 213, 215, 217, and 219 and the semiconductor substrate sub.

[0051] The gate structures 223 and 225 are formed above the surface of the A region and divide the surface of the A region into three sub-regions. The gate structure 225 has an L shape, and the extension part of the gate structure 225 extends outward through the surface of the isolation structure 202 and extends above the surface of the B region. Furthermore, the gate structures 227 and 229 are only formed above the isolation structure 202, and are respectively located on two sides of the gate structure 225. In addition, the polysilicon gate layer 215 is the floating gate of the floating gate transistor, and the polysilicon gate layer 213 is the select gate of the select transistor. According to an embodiment of the present invention, the channel length L of the floating gate transistor F Smaller than the channel length L of the select transistor S , that is, L F <L S .

[0052] As we all know, the channel resistance of a transistor is related to the channel length and channel width of the transistor. When the channel width is wider, the channel resistance is smaller; when the channel width is narrower, the channel resistance is larger. When the channel length is shorter, the channel resistance is smaller; when the channel length is longer, the channel resistance is larger. In other words, Figure 2B In the structure, if the n-type doping regions are also completed using the same manufacturing process, the channel resistance value of the floating gate transistor will be smaller than the channel resistance value of the selection transistor.

[0053] According to an embodiment of the present invention, the present invention designs the doping steps of the n-type doping region, changes the concentration distribution of the n-type doping region, and further changes the channel resistance value of the floating gate transistor, so that the channel resistance value of the floating gate transistor is greater than the channel resistance value of the selection transistor. Figure 2B The cd dotted line cross-sectional diagram is used to introduce the detailed process technology of the doping step of the present invention.

[0054] like Figure 2C As shown, the gate structure 225 and its two side regions in region A are first covered by a mask 240 shown by a dotted line, exposing the gate structure 223 and its two side regions, and exposing region B. That is, on the surface between the gate structure 223 and the gate structure 225, only a portion of the surface is covered by the mask 240, and the other portion of the surface is not covered by the mask 240. Next, a first lightly doped drain process (LDD process for short) is performed, and n-type lightly doped drain regions (n-LDD regions) 241, 242, and 243 are formed below the sub surface of the semiconductor substrate not covered by the mask 240. Among them, the n-type lightly doped drain regions 241 and 242 are respectively located below the surface of region A and on two sides of the gate structure 223. The n-type lightly doped drain region 243 is located in region B, below the surface next to the gate structure 225.

[0055] like Figure 2D As shown, after removing the mask 240, the mask 250 shown by the dotted line covers the area B, and covers the gate structure 223 and the areas on both sides of the area A. That is, the area previously covered by the mask 240 is exposed. Then, a second lightly doped drain process is performed, and n-type lightly doped drain regions 251 and 252 are formed on the surface of the semiconductor substrate sub that is not covered by the mask 250. Among them, the n-type lightly doped drain regions 251 and 252 are respectively located below the surface of the area A and on both sides of the gate structure 225.

[0056] For example, the masks 240 and 250 may be photoresists. Furthermore, according to the embodiment of the present invention, the doping concentration of the lightly doped drain regions 251 and 252 is less than the doping concentration of the lightly doped drain regions 241 , 242 , and 243 .

[0057] like Figure 2E As shown, after removing the mask 250, a spacer 248 is formed on the sidewall of the gate structure 223, and a spacer 258 is formed on the sidewall of the gate structure 225. Of course, spacers are also formed on the sidewalls of the other two gate structures 227 and 229 (not shown).

[0058] Then, if Figure 2FAs shown, the two gate structures 223, 225 and the spacers 248, 258 are used as masks to perform an n-type ion implantation process on the substrate sub surface. Therefore, the three sub-regions in the A region that are not covered by the two gate structures 223, 225 and the spacers 248, 258 form three n-type ion implantation regions 261, 262, 263 shown as the diagonal regions. The portion of the B region that is not covered by the gate structure 225 and the spacer 258 forms an n-type ion implantation region 264 shown as the diagonal region. Basically, the doping concentration of the n-type ion implantation regions 261, 262, 263, 264 is the highest, and its doping concentration is greater than the doping concentration of all the lightly doped drain regions 241, 242, 243, 251.

[0059] like Figure 2F As shown, the n-type lightly doped drain region 241 and the n-type ion implanted region 261 form a merged n-doped region 271, which is located below the surface of the first side of the gate structure 223. The n-type lightly doped drain regions 242, 251 and the n-type ion implanted region 262 form a merged n-doped region 272, which is located below the surface between the second side of the gate structure 223 and the first side of the gate structure 225. The n-type lightly doped drain region 252 and the n-type ion implanted region 263 form a merged n-doped region 273, which is located below the surface of the second side of the gate structure 225. Furthermore, the n-type lightly doped drain region 243 and the n-type ion implanted region 264 form a merged n-doped region 274, which is located below the surface on one side of the extension of the gate structure 225. In addition, Figure 2G Then Figure 2F Stereoscopic diagram.

[0060] Therefore, in the A region, the gate structure 223 and the merged n-type doped regions 271 and 272 on its two sides form a select transistor. The gate structure 225 and the merged n-type doped regions 272 and 273 on its two sides form a floating gate transistor. The floating gate transistor and the select transistor are n-type transistors fabricated in the P-type well region PW. That is, the body terminals of the floating gate transistor and the select transistor are connected to the P-type well region PW.

[0061] Furthermore, the n-type doped region 274 in the B region is the erase gate region, and the gate structure 225 extends outward and is adjacent to the erase gate region. Therefore, the erase gate region and the gate structure 225 form an n-type transistor, and the n-type transistor is connected to form a MOS capacitor.

[0062] Then, if Figure 2H As shown, a metal layer 280 is further formed on the polysilicon gate layer 215, and the metal layer 280 is electrically connected to the polysilicon gate layers 217 and 219. Afterwards, a wiring step is performed to complete the memory cell of the present invention. That is, the n-type doping region 271 is connected to the source line SL, the n-type doping region 273 is connected to the bit line BL, the n-type doping region 274 is connected to the erase line EL, the polysilicon gate layer 213 is connected to the select gate line SG, and the metal layer 280 is connected to the auxiliary gate line AG.

[0063] In the memory cell of the present invention, the gate structures 227 and 229 are located on the surface of the isolation structure 202, and the metal layer 280 is located above the gate structure 225. Therefore, the polysilicon gate layer 215 and the polysilicon gate layer 217 form a first polysilicon / polysilicon plate capacitor (poly / poly plate capacitor). The polysilicon gate layer 215 and the polysilicon gate layer 219 form a second polysilicon / polysilicon plate capacitor (poly / poly plate capacitor). The polysilicon gate layer 215 and the metal layer 280 form a metal / polysilicon plate capacitor.

[0064] like Fig.2I As shown, the memory cell of the first embodiment includes a selection transistor M S , a floating gate transistor M F , a MOS capacitor C MOS , a first polysilicon / polysilicon flat panel capacitor C P1 , a metal / polysilicon flat plate capacitor C P2 , a second polysilicon / polysilicon flat panel capacitor C P3 Among them, the first polysilicon / polysilicon flat panel capacitor C P1 , Metal / polysilicon flat capacitor C P2 , the second polysilicon / polysilicon flat panel capacitor C P3 The three capacitors C in parallel can be connected in parallel. P1 , C P2 , C P3 Equivalent to a flat plate capacitor C P Of course, the capacitor C of the memory cell of the first embodiment P It is not limited to three capacitors C P1 , C P2 , C P3 For parallel connection, just have more than one capacitor.

[0065] Select transistor M SThe gate terminal of the transistor M is connected to a selection gate line SG. S A first drain / source terminal of the floating gate transistor M is connected to the source line SL. F The first drain / source terminal is connected to the selection transistor M S The second drain / source terminal of the floating gate transistor M F The second drain / source terminal of is connected to the bit line BL.

[0066] MOS capacitor C MOS The first end of the MOS capacitor C is connected to the floating gate 215. MOS1 The second end of the first polysilicon / polysilicon flat panel capacitor C is connected to the erase line EL. P1 The first end of the first polysilicon / polysilicon plate capacitor C is connected to the floating gate 215. P1 The second end of is connected to the auxiliary gate line AG. The metal / polysilicon plate capacitor C P2 The first end of the metal / polysilicon plate capacitor C is connected to the floating gate 215. P2 The second end of the second polysilicon / polysilicon plate capacitor C is connected to the auxiliary gate line AG. P3 The first end of the second polysilicon / polysilicon plate capacitor C is connected to the floating gate 215. P3 The second end of the plate capacitor C is connected to the auxiliary gate line AG. P The first end of the capacitor C is connected to the floating gate 215. P The second end of is connected to the auxiliary gate line AG.

[0067] From the above description, it can be seen that the memory cell of the first embodiment of the present invention is composed of two transistors M S 、M F With two capacitors C P , C MOS The composition can be called a 2T2C memory cell.

[0068] Please refer to Figure 2J to Figure 2M , which illustrates a bias table and an operation schematic diagram of the memory cell performing programming, erasing and reading operations according to the first embodiment of the present invention.

[0069] During the programming operation (PGM), erasing operation (ERS) and reading operation (Read), the P-type well region PW and the source line SL receive the ground voltage (0V). In addition, the auxiliary gate line voltage V AG Greater than the erase voltage V EE , erase voltage V EE Greater than the programming voltage V PP , programming voltage V PP Greater than the read voltage VR , read the voltage V R is greater than the ground voltage (0V). For example, the auxiliary gate line voltage V AG is 15V, the erase voltage V EE is 12V, programming voltage V PP is 9V, read voltage V R is 5V.

[0070] like Figure 2K As shown, during the programming action, the bit line BL receives the programming voltage V PP , select gate line SG to receive programming voltage V PP The voltage received by the erase line EL can be set between the ground voltage (0V) and the erase voltage V EE The voltage received by the auxiliary gate line AG can be set between the ground voltage (0V) and the auxiliary gate line voltage V AG between.

[0071] During programming, transistor M is selected. S Turn on, a programming current I is generated between the bit line BL and the source line SL P Therefore, when the programming current I P When hot carriers (such as electrons) in the floating gate 215 pass through the channel region corresponding to the floating gate 215 , a channel hot electron injection effect (CHE effect) is generated, so that electrons are injected into the floating gate 215 .

[0072] According to an embodiment of the present invention, since the floating gate transistor M F The channel resistance value is greater than the select transistor M S The channel resistance value, when the programming voltage V PP After being supplied to the bit line BL, the floating gate transistor M F The voltage across the first drain / source terminal and the second drain / source terminal is greater than that of the selection transistor M. S The voltage between the first drain / source terminal and the second drain / source terminal is reduced. Therefore, during the programming operation (PGM), electrons are injected into the floating gate 215 more efficiently.

[0073] like Figure 2L As shown, during the erase operation (ERS), the bit line BL receives the ground voltage (0V), the select gate line SG receives the ground voltage (0V), and the erase line EL receives the erase voltage V EE , the voltage received by the auxiliary gate line AG can be set at the negative auxiliary gate line voltage -V AG Between the ground voltage (0V).

[0074] During the erase operation, transistor M is selected. S At this time, the MOS capacitor C MOS The two ends generate FN tunneling effect, and electrons are ejected from the floating gate 215 to the erase line EL. The voltage received by the auxiliary gate line AG can accelerate the speed of electrons exiting the floating gate 215, so as to improve the erase efficiency.

[0075] like Figure 2M As shown, during the read operation, the bit line BL receives the read voltage V R , the source line SL receives the ground voltage (0V), and the select gate line SG receives the read voltage V R , the erase line EL receives the ground voltage (0V), and the voltage received by the auxiliary gate line AG can be set at the negative auxiliary gate line voltage -V AG and the auxiliary gate line voltage V AG Among them, the voltage received by the auxiliary gate line AG can appropriately adjust the read current I R size.

[0076] In the read operation, the transistor M is selected S Turn on, and a read current I is generated between the bit line BL and the source line SL R . According to the reading current I R The size of can determine the storage state of the memory cell. For example, when electrons are stored in the floating gate 215, the read current I R is very small, almost zero, and the memory cell is considered to be in the first storage state. When no electrons are stored in the floating gate 215, the read current I R Larger, visible memory cell is in the second storage state.

[0077] From the above description, it can be seen that in order to make the floating gate transistor M with a shorter channel length F With a higher channel resistance value, the present invention designs two lightly doped drain process technologies with different doping concentrations. Figure 2F As shown, in the merged n-type doped region 272, near the floating gate transistor M F The lightly doped drain region 251 on the first side of the gate structure 225 has a relatively low doping concentration. F The lightly doped drain region 252 on the second side of the gate structure 225 has a relatively low doping concentration. S The lightly doped drain region 241 on the first side of the gate structure 223 has a higher doping concentration. SThe lightly doped drain region 242 on the second side of the gate structure 223 has a higher doping concentration. According to the embodiment of the present invention, the difference in doping concentration near the channel may affect the floating gate transistor M in the memory cell. F The channel resistance value and the selection transistor M S The channel resistance value makes the floating gate transistor M F The channel resistance value is greater than the select transistor M S The channel resistance value.

[0078] Of course, in addition to the doping steps disclosed in the first embodiment, there are other doping steps that can make the floating gate transistor M with a shorter channel length in the memory cell F It has a higher channel resistance value. The following explains it.

[0079] Please refer to FIG. 3A to FIG. 3C , which illustrates a first modified example of the doping step of the present invention. Basically, Figure 3A The doping step is followed by Figure 2B After the structure.

[0080] like Figure 3A As shown, the mask 340 shown by the dotted line first covers the gate structure 225 and the gate structure 223 in the area A, as well as the two side areas of the gate structure 225, and only exposes the area on one side (right side) of the gate structure 223. Then, the first lightly doped drain process is performed, and n-type lightly doped drain regions 341 and 343 are formed below the surface of the semiconductor substrate sub that is not covered by the mask 340. Among them, the n-type lightly doped drain region 341 is located below the surface of the A area, on one side (right side) of the gate structure 223. The n-type lightly doped drain region 343 is located in the B area, below the surface next to the gate structure 225.

[0081] like Figure 3B As shown, after the mask 340 is removed, the mask 350 shown by the dotted line covers the area on one side (right side) of the gate structure 223 in area A and area B. That is, the area previously covered by the mask 340 is exposed. Then, a second lightly doped drain process is performed, and n-type lightly doped drain regions 351 and 352 are formed on the surface of the semiconductor substrate sub that is not covered by the mask 350. Among them, the n-type lightly doped drain regions 351 and 352 are respectively located below the surface of area A and on two sides of the gate structure 225.

[0082] For example, the masks 340 and 350 may be photoresists. Furthermore, according to the embodiment of the present invention, the doping concentration of the lightly doped drain regions 351 and 352 is less than the doping concentration of the lightly doped drain regions 341 and 243 .

[0083] like Figure 3CAs shown, after the spacers 248 and 258 are manufactured, the two gate structures 223 and 225 and the spacers 248 and 258 are used as masks to perform ion implantation process on the substrate sub surface. Therefore, the three sub-regions in the A region that are not covered by the two gate structures 223 and 225 and the spacers 248 and 258 form three n-type ion implantation regions 261, 262, and 263 shown in the oblique line regions. The portion in the B region that is not covered by the gate structure 225 and the spacers 258 forms an n-type ion implantation region 264 shown in the oblique line region.

[0084] like Figure 3C As shown, the n-type lightly doped drain region 341 and the n-type ion implanted region 261 form a merged n-doped region 271, which is located below the surface of the first side of the gate structure 223. The n-type lightly doped drain region 351 and the n-type ion implanted region 262 form a merged n-doped region 272, which is located below the surface between the second side of the gate structure 223 and the first side of the gate structure 225. The n-type lightly doped drain region 352 and the n-type ion implanted region 263 form a merged n-doped region 273, which is located below the surface of the second side of the gate structure 225. Furthermore, the n-type lightly doped drain region 343 and the n-type ion implanted region 264 form a merged n-doped region 274, which is located below the surface of the extension side of the gate structure 225.

[0085] Compare Figure 2F and Figure 3C From the structure, we can see that Figure 2F The doping concentration of the lightly doped drain region 242 on the left side of the middle gate structure 223 is relatively high. Figure 3C The doping concentration of the lightly doped drain region 351 on the left side of the middle gate structure 223 is relatively low, while the doping concentrations of other regions are the same.

[0086] Figure 3C In the merged n-type doped region 272, near the floating gate transistor M F The lightly doped drain region 351 on the first side of the gate structure 225 has a relatively low doping concentration. F The lightly doped drain region 352 on the second side of the gate structure 225 has a relatively low doping concentration. S The lightly doped drain region 341 on the first side of the gate structure 223 has a higher doping concentration. S The lightly doped drain region 351 on the second side of the gate structure 223 has a lower doping concentration. According to the embodiment of the present invention, the difference in doping concentration near the channel may affect the floating gate transistor M in the memory cell.F The channel resistance value and the selection transistor M S The channel resistance value makes the floating gate transistor M F The channel resistance value is greater than the select transistor M S The channel resistance value.

[0087] In addition, the subsequent memory cell production process can refer to Figure 2G and Figure 2H , and the equivalent circuit is the same as Fig.2I , I will not go into details here.

[0088] Please refer to FIG. 4A to FIG. 4C , which illustrates a second modified example of the doping step of the present invention. Basically, Figure 4A The doping step is followed by Figure 2B Continue with the structure.

[0089] like Figure 4A As shown, the gate structure 225 and one side (left side) area in area A are first covered with a mask 440 shown by a dotted line, exposing the gate structure 223 and two side areas thereof, and exposing area B. Next, a first lightly doped drain process is performed, and n-type lightly doped drain regions 441, 442, and 443 are formed below the surface of the semiconductor substrate sub that is not covered by the mask 440. Among them, the n-type lightly doped drain region 441 is located below the surface of area A, on one side (right side) of the gate structure 223, and the n-type lightly doped drain region 442 is located below the surface of area A, on the other side (left side) of the gate structure 223. The n-type lightly doped drain region 443 is located in area B, below the surface next to the gate structure 225.

[0090] like Figure 4B As shown, after removing the mask 440, the mask 450 shown by the dotted line covers the two side areas of the gate structure 223 in area A and area B. That is, the area previously covered by the mask 440 is exposed. Then, a second lightly doped drain process is performed, and an n-type lightly doped drain region 452 is formed on the surface of the semiconductor substrate sub that is not covered by the mask 450. Among them, the n-type lightly doped drain region 452 is located below the surface of area A, on one side (left side) of the gate structure 225. Among them, the masks 440 and 450 can be photoresists. Furthermore, according to an embodiment of the present invention, the doping concentration of the lightly doped drain region 452 is less than the doping concentration of the lightly doped drain regions 441, 442, and 443.

[0091] Furthermore, after the spacers 248 and 258 are manufactured, Figure 4CAs shown, the two gate structures 223, 225 and the spacers 248, 258 are used as masks to perform ion implantation process on the substrate sub surface. Therefore, the three sub-regions in the A region that are not covered by the two gate structures 223, 225 and the spacers 248, 258 form three n-type ion implantation regions 261, 262, 263 shown in the oblique line regions. The portion of the B region that is not covered by the gate structure 225 and the spacer 258 forms an n-type ion implantation region 264 shown in the oblique line region.

[0092] like Figure 4C As shown, the n-type lightly doped drain region 441 and the n-type ion implanted region 261 form a merged n-doped region 271, which is located below the surface of the first side of the gate structure 223. The n-type lightly doped drain region 442 and the n-type ion implanted region 262 form a merged n-doped region 272, which is located below the surface between the second side of the gate structure 223 and the first side of the gate structure 225. The n-type lightly doped drain region 452 and the n-type ion implanted region 263 form a merged n-doped region 273, which is located below the surface of the second side of the gate structure 225. Furthermore, the n-type lightly doped drain region 443 and the n-type ion implanted region 264 form a merged n-doped region 274, which is located below the surface of the extension side of the gate structure 225.

[0093] Compare Figure 2F and Figure 4C From the structure, we can see that Figure 2F The doping concentration of the lightly doped drain region 251 on the right side of the middle gate structure 225 is relatively low. Figure 4C The doping concentration of the lightly doped drain region 442 on the right side of the middle gate structure 225 is higher, while the doping concentrations of other regions are the same.

[0094] That is to say, Figure 4C In the merged n-type doped region 272, near the floating gate transistor M F The lightly doped drain region 442 on the first side of the gate structure 225 has a higher doping concentration. F The lightly doped drain region 452 on the second side of the gate structure 225 has a relatively low doping concentration. S The lightly doped drain region 441 on the first side of the gate structure 223 has a higher doping concentration. S The lightly doped drain region 442 on the second side of the gate structure 223 has a higher doping concentration. According to the embodiment of the present invention, the difference in doping concentration near the channel may affect the floating gate transistor M in the memory cell. FThe channel resistance value and the selection transistor M S The channel resistance value makes the floating gate transistor M F The channel resistance value is greater than the select transistor M S The channel resistance value.

[0095] In addition, the subsequent memory cell production process can refer to Figure 2G and Figure 2H , and the equivalent circuit is the same as Fig.2I , I will not go into details here.

[0096] As can be seen from the above description, the present invention can control the doping concentration of the lightly doped drain region in the merged n-type doping regions 271, 272, and 273 so that the floating gate transistor M F The channel resistance value is greater than the select transistor M S For example, the merged n-type doping region 271 includes a first n-type lightly doped drain region located on a first side of the gate structure 223. The merged n-type doping region 272 includes a second n-type lightly doped drain region and a third n-type lightly doped drain region, the second n-type lightly doped drain region is located on a second side of the gate structure 223, and the third n-type lightly doped drain region is located on a first side of the gate structure 225. The merged n-type doping region 273 includes a fourth n-type lightly doped drain region located on a second side of the gate structure 225.

[0097] by Figure 2F For example, the doping concentration of the fourth n-type lightly doped drain region 252 is the same as the doping concentration of the third n-type lightly doped drain region 251 , the doping concentration of the second n-type lightly doped drain region 242 is the same as the doping concentration of the first n-type lightly doped drain region 241 , and the doping concentration of the fourth n-type lightly doped drain region 252 is less than the doping concentration of the first n-type lightly doped drain region 241 .

[0098] by Figure 3C For example, the doping concentration of the fourth n-type lightly doped drain region 352 is the same as the doping concentration of the third n-type lightly doped drain region 351 , the doping concentration of the third n-type lightly doped drain region 351 is the same as the doping concentration of the second n-type lightly doped drain region 351 , and the doping concentration of the fourth n-type lightly doped drain region 352 is less than the doping concentration of the first n-type lightly doped drain region 341 .

[0099] by Figure 4C For example, the doping concentration of the third n-type lightly doped drain region 442 is the same as the doping concentration of the second n-type lightly doped drain region 442 , the doping concentration of the second n-type lightly doped drain region 442 is the same as the doping concentration of the first n-type lightly doped drain region 441 , and the doping concentration of the fourth n-type lightly doped drain region 452 is less than the doping concentration of the first n-type lightly doped drain region 441 .

[0100] In addition, in the above description, the lightly doped drain regions 243, 343, 443, and 543 of region B are all completed in the first lightly doped drain process, and their doping concentration is relatively high. Of course, the present invention is not limited to this, and the lightly doped drain region of region B can also be completed using the second lightly doped drain process, and its doping concentration is relatively low. Of course, the order of the above-mentioned second lightly doped drain process can also be exchanged, for example, the doping concentration of the first lightly doped drain process is relatively low, and the doping concentration of the second lightly doped drain process is relatively high.

[0101] Of course, the present invention has other doping steps to achieve the above Figure 2F , Figure 3C and Figure 4C Please refer to FIG. 5A to FIG. 5C , which is a third modified example of the doping step of the present invention. Basically, Figure 5A The doping step is followed by Figure 2B After the structure.

[0102] As shown in FIG. 5A , a lightly doped drain process is performed using the gate structures 223 and 225 as masks. Among them, the n-type lightly doped drain region 541 is located below the surface of the first side of the gate structure 223, the n-type lightly doped drain region 542 is located below the surface of the second side of the gate structure 223 and the first side of the gate structure 225, and the n-type lightly doped drain region 544 is located below the surface of the second side of the gate structure 225. In addition, the n-type lightly doped drain region 543 is located in the B region, below the surface next to the gate structure 225.

[0103] Furthermore, after the spacers 248 and 258 are manufactured, Figure 5B As shown, the two gate structures 223, 225 and the spacers 248, 258 are used as masks to perform an n-type ion implantation process on the substrate sub surface. Therefore, the three sub-regions in the A region that are not covered by the two gate structures 223, 225 and the spacers 248, 258 form three n-type ion implantation regions 261, 262, 263 shown in the oblique line regions. The portion of the B region that is not covered by the gate structure 225 and the spacer 258 forms an n-type ion implantation region 264 shown in the oblique line region.

[0104] Since the lightly doped drain regions 541, 542, 544 on the surface of region A have the same doping concentration, in order to allow the floating gate transistor M F The channel resistance value is large. Figure 5CAs shown, a mask 560 is used to cover the surface of the semiconductor substrate Sub, exposing only the gate structure 225 of region A and part of the surface on both sides. Then, an anti punchthrough implantation process (APT process for short) is performed. Therefore, two APT regions 561 and 562 are formed. Among them, the APT region 561 contacts the n-type lightly doped drain region 542, and the APT region 562 contacts the n-type lightly doped drain region 544. For example, the APT process can be a HALO implantation process or a POCKET implantation process. Since the APT regions 561 and 562 contact the n-type lightly doped drain regions 542 and 544, respectively, a higher resistance and a higher electric field are generated in the n-type lightly doped drain regions 542 and 544. Therefore, the floating gate transistor M F The channel resistance value is greater than the select transistor M S The channel resistance value.

[0105] In addition, after removing the mask 560, you can Figure 2G and Figure 2H The process is to complete the memory cell, and the equivalent circuit is the same as Fig.2I , I will not go into details here.

[0106] FIG. 5A to FIG. 5C The doping step is to design the counter-punch implantation regions 561 and 562 beside the n-type lightly doped drain regions 542 and 544. The present invention can also make various modifications and changes. For example, in the modification example, only a single counter-punch implantation region can be formed to contact the n-type lightly doped drain region 544 on one side of the gate structure 225. Alternatively, only a single counter-punch implantation region can be formed to contact the n-type lightly doped drain region 542 on the other side of the gate structure 225. Alternatively, three counter-punch implantation regions are formed, two of which are in contact with the n-type lightly doped drain regions 542 and 544 on both sides of the gate structure 225, and one counter-punch implantation region is in contact with the n-type lightly doped drain region 542 on one side of the gate structure 223, and no counter-punch implantation region is formed beside the n-type lightly doped drain region 541 on the other side of the gate structure 223. Alternatively, three counter-punch-through implantation regions are formed, two of which are in contact with the n-type lightly doped drain regions 542 and 544 on both sides of the gate structure 225, and one counter-punch-through implantation region is in contact with the n-type lightly doped drain region 541 on one side of the gate structure 223, and no counter-punch-through implantation region is formed next to the n-type lightly doped drain region 542 on the other side of the gate structure 223. In this way, the floating gate transistor M F The channel resistance value is greater than the select transistor M SThe channel resistance value.

[0107] In addition, it should be noted that the conductivity of the counter-penetration implanted region can be an n-type counter-penetration implanted region or a p-type counter-penetration implanted region. Since the p-type counter-penetration implanted region has better characteristics, designing a p-type counter-penetration implanted region is a better choice.

[0108] In practical applications, in order to further improve the floating gate transistor M F The channel resistance value can also be reduced by performing a p-type channel implantation process under the gate structure 225. Figure 6 , which shows a fourth modified example of the inventive doping step. Figure 6 The structure is below the 2F structure, and a p-type channel doping process is further performed.

[0109] exist Figure 2F After the p-type channel doping process is performed under the structure of the gate structure 225, a p-type channel doping region 602 will be formed on the surface of the semiconductor substrate Sub below the gate structure 225. Since the p-type channel doping region 602 and the n-type combined doping regions 272 and 273 have different doping types, the floating gate transistor M can be improved. F Similarly, using the p-type channel doping process, it can also be used in Figure 3C , Figure 4C , Figure 5B or Figure 5C In the structure, a p-type channel doping region 602 is formed on the surface of the semiconductor substrate Sub below the gate structure 225 .

[0110] Please refer to FIG. 7A to FIG. 7G , which illustrates the manufacturing process of the memory cell according to the second embodiment of the present invention. Figure 7H FIG. 4 is an equivalent circuit diagram of a memory cell according to a second embodiment of the present invention.

[0111] like Fig. 7A As shown, an isolation structure 702 is formed on the semiconductor p-type substrate Sub, and region A and region B are defined. Region B is a rectangular region, and region A is composed of two rectangular sub-regions A1 and A2. Next, a first well region, such as a P-type well region PW, is formed below region A on the surface of the semiconductor substrate Sub. In addition, a second well region is formed below region B on the surface of the substrate sub. The second well region may be a lightly doped P-type well region LPW, a P-type well region PW, or an N-type well region NW. In the subsequent manufacturing process, region A will form a floating gate transistor, a selection transistor, and an assist gate region, and region B will form an erase gate region.

[0112] like Figure 7B As shown, two gate oxide layers 703 and 705 are first formed. Afterwards, polysilicon gate layers 713 and 715 are formed to cover the two gate oxide layers 703 and 705 respectively, and two gate structures 723 and 725 are formed. Among them, the two gate structures 723 and 725 are formed on the surface of the A region, and the A region is divided into three sub-regions. Specifically, the two gate structures 723 and 725 are both formed on the surface of the A1 region. The left side of the gate structure 723 is the first sub-region, the right side of the gate structure 723 and the left side of the gate structure 725 are the second sub-region, and the right side of the gate structure 725 (including the A2 sub-region) is the third sub-region. In other words, the third sub-region is an L-shaped sub-region.

[0113] Furthermore, the branch of the gate structure 725 extending outward through the surface of the isolation structure 702 includes two extension branches (extension segments). The first extension branch of the gate structure 725 extends to the B region and covers a portion of the B region. The second extension branch of the gate structure 725 extends to the A2 sub-region in the A region and covers a portion of the A2 sub-region. According to an embodiment of the present invention, the polysilicon gate layer 715 of the gate structure 725 is the floating gate (floating gate) of the floating gate transistor. The polysilicon gate layer 713 in the other gate structure 723 is the selection gate (select gate) of the selection transistor. According to an embodiment of the present invention, the channel length L of the floating gate transistor F Smaller than the channel length L of the select transistor S , that is, L F <L S .

[0114] Next, the doping region forming step is performed. In the following description, the cross-sectional view of the doping step of the present invention is introduced with reference to the dashed line ef.

[0115] like Figure 7CAs shown, the mask 740 shown by the dotted line first covers the gate structure 725 and its two side regions in area A, and exposes the gate structure 723 and its two side regions, and exposes area B. That is to say, on the surface between the gate structure 723 and the gate structure 725, only a part of the surface is covered by the mask 740, and the other part of the surface is not covered by the mask 740. Then, the first lightly doped drain process is performed, and n-type lightly doped drain regions (n-LDD regions) 741, 742, and 743 are formed below the surface of the semiconductor substrate sub that is not covered by the mask 740. Among them, the n-type lightly doped drain regions 741 and 742 are respectively located below the surface of area A and on two sides of the gate structure 723. The n-type lightly doped drain region 743 is located in area B, below the surface next to the gate structure 725.

[0116] like Fig.7D As shown, after removing the mask 740, the mask 750 shown by the dotted line covers the gate structure 723 and its two side areas in area A, and covers area B. That is, the area previously covered by the mask 740 is exposed. Then, a second lightly doped drain process is performed, and n-type lightly doped drain regions 751 and 752 are formed on the surface of the semiconductor substrate sub that is not covered by the mask 750. Among them, the n-type lightly doped drain regions 751 and 752 are respectively located below the surface of area A and on two sides of the gate structure 725.

[0117] For example, the masks 740 and 750 may be photoresists. Furthermore, according to the embodiment of the present invention, the doping concentration of the lightly doped drain regions 751 and 752 is less than the doping concentration of the lightly doped drain regions 741 , 742 , and 743 .

[0118] After removing the mask 750, as Fig. 7E As shown, a spacer 748 is formed on the sidewall of the gate structure 723, and a spacer 758 is formed on the sidewall of the gate structure 725. Next, an n-type ion implantation process is performed on the substrate sub surface using the two gate structures 723, 725 and the spacers 748, 758 as a mask. Therefore, the three sub-regions in the A region that are not covered by the two gate structures 723, 725 and the spacers 748, 758 form three n-type ion implantation regions 761, 762, 763 shown as the oblique line regions. The portion of the B region that is not covered by the gate structure 725 and the spacer 758 forms an n-type ion implantation region 764 shown as the oblique line region. Basically, the doping concentration of the n-type ion implantation regions 761, 762, 763, 764 is the highest, and its doping concentration is greater than the doping concentration of all the lightly doped drain regions 741, 742, 743, 751, 752.

[0119] like Fig. 7E As shown, the n-type lightly doped drain region 741 and the n-type ion implanted region 761 form a merged n-type doped region 771, which is located below the surface of the first side of the gate structure 723. The n-type lightly doped drain regions 742, 751 and the n-type ion implanted region 762 form a merged n-type doped region 772, which is located below the surface between the second side of the gate structure 723 and the first side of the gate structure 725. The n-type lightly doped drain region 752 and the n-type ion implanted region 763 form a merged n-type doped region 773, which is located below the surface of the second side of the gate structure 725. Furthermore, the n-type lightly doped drain region 743 and the n-type ion implanted region 764 form a merged n-type doped region 774, which is located below the surface on one side of the extension of the gate structure 225. In addition, Figure 7F Then Fig. 7E Stereoscopic diagram.

[0120] Therefore, in the A region, the gate structure 723 and the n-type doped regions 771 and 772 on its two sides form a selection transistor. The gate structure 725 and the n-type doped regions 772 and 773 on its two sides form a floating gate transistor. The floating gate transistor and the selection transistor are n-type transistors fabricated in the P-type well region PW. That is, the body terminals of the floating gate transistor and the selection transistor are connected to the P-type well region PW.

[0121] Furthermore, in addition to serving as a drain / source terminal of the floating gate transistor, the n-type doped region 773 can also serve as an auxiliary gate region. That is, the second extension branch of the gate structure 725 extends outward and is adjacent to the auxiliary gate region. Therefore, the auxiliary gate region and the gate structure 725 form an n-type transistor, and the n-type transistor is connected to form a MOS capacitor.

[0122] In addition, the n-type doped region 774 in the B region is the erase gate region, and the first extension branch of the gate structure 725 extends outward and is adjacent to the erase gate region. Therefore, the erase gate region and the gate structure 725 form an n-type transistor, and the n-type transistor is connected to form another MOS capacitor.

[0123] like Figure 7G As shown, the wiring step is performed to complete the memory cell of the second embodiment of the present invention. That is, the n-type doping region 771 is connected to the source line SL, the n-type doping region 773 is connected to the bit line BL, the n-type doping region 774 is connected to the erase line EL, and the polysilicon gate layer 713 is connected to the select gate line SG.

[0124] like Figure 7H As shown, the memory cell includes a selection transistor M S , a floating gate transistor M F , a first MOS capacitor C EG, a second MOS capacitor C AG .

[0125] Select transistor M S The gate terminal of the transistor M is connected to a select gate line SG. S A first drain / source terminal of the floating gate transistor M is connected to the source line SL. F The first drain / source terminal is connected to the selection transistor M S The second drain / source terminal of the floating gate transistor M F The second drain / source terminal of the first MOS capacitor C is connected to the bit line BL. EG The first end of the first MOS capacitor C is connected to the floating gate 715. EG The second end of the second MOS capacitor C is connected to the erase line EL. AG The first end of the second MOS capacitor C is connected to the floating gate 715. AG The second end of is connected to line BL.

[0126] From the above description, it can be seen that the memory cell of the second embodiment of the present invention is composed of two transistors M S 、M F With two capacitors C EG , C AG The composition can be called a 2T2C memory cell.

[0127] Furthermore, providing appropriate bias voltage to the memory cell of the second embodiment can perform programming operation (PGM), erasing operation (ERS) and reading operation (Read). For example, the memory cell of the second embodiment does not include auxiliary gate line AG, so Figure 2J After the bias voltage of the auxiliary gate line AG in the bias voltage table is ignored, the memory cell of the second embodiment can be applied. The detailed operation is similar to the memory cell of the first embodiment, and will not be described again.

[0128] Depend on Fig. 7E As can be seen from the memory cell of the second embodiment, in the merged n-type doped region 772, the region near the floating gate transistor M F The lightly doped drain region 751 on the first side of the gate structure 725 has a relatively low doping concentration. F The lightly doped drain region 752 on the second side of the gate structure 725 has a relatively low doping concentration. S The lightly doped drain region 741 on the first side of the gate structure 723 has a higher doping concentration. SThe lightly doped drain region 742 on the second side of the gate structure 723 has a higher doping concentration. That is, due to the difference in doping concentration near the channel, the floating gate transistor M in the memory cell may be affected. F The channel resistance value and the selection transistor M S The channel resistance value makes the floating gate transistor M F The channel resistance value is greater than the select transistor M S The channel resistance value.

[0129] Similarly, in addition to the doping step disclosed in the second embodiment, the modified example of the doping step disclosed in the first embodiment can also be applied to the second embodiment. That is, the present invention can also be FIG. 3A to FIG. 3C The first modified example, FIG. 4A to FIG. 4C The second modified example, FIG. 5A to FIG. 5C The third modification example or Figure 6 The fourth modification example of the present invention is applied to the memory cell of the second embodiment. F The channel resistance value is greater than the select transistor M S The channel resistance value of the transistor is 0.04V, and the detailed process technology will not be described in detail.

[0130] Furthermore, in the first and second embodiments of the present invention, the floating gate transistor M of the memory cell F With the selection transistor M S The n-type transistor is used as an example for explanation, that is, the lightly doped drain region and the merged doped region are n-type lightly doped drain regions and merged n-type doped regions. Of course, the present invention is not limited to this. The floating gate transistor M of the memory cell of the present invention F With the selection transistor M S It can also be a p-type transistor. In this case, the lightly doped drain region and the combined doped region are p-type lightly doped drain regions and combined p-type doped regions, which are formed in the N-type well region NW. Similarly, the metal oxide semiconductor capacitor C MOS Transistor, C EG , C AG It can also be composed of p-type transistors.

[0131] Furthermore, the first embodiment and the second embodiment of the present invention are both described using 2T2C memory cells as examples. In fact, the present invention can also be applied to 2T1C memory cells. For example, in Fig.2I In the first embodiment of the memory cell, the plate capacitor C is deleted. P1 , C P2 , C P3 The design becomes a 2T1C memory cell, and the present invention can also be applied to this 2T1C memory cell. Figure 7HIn the second embodiment of the memory cell, the MOS capacitor C is deleted AG The design becomes a 2T1C memory cell, and the present invention can also be applied to this 2T1C memory cell.

[0132] In summary, although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope defined in the attached claims.

Claims

1. A programmable and erasable single polysilicon layer non-volatile memory cell, comprising: An isolation structure is formed on a semiconductor substrate, and the isolation structure divides the surface of the semiconductor substrate into a first area and a second area; A first well region is formed below the surface of the first region of the semiconductor substrate; A second well region is formed below the surface of the second region of the semiconductor substrate; A first gate structure and a second gate structure are formed on the surface of the first region, and the first gate structure and the second gate structure divide the surface of the first region into a first combined doping region, a second combined doping region and a third combined doping region; as well as A fourth combined doped region is formed below the surface of the second region and is located on one side of the second gate structure; The first merged doping region is located on the first side of the first gate structure, the second merged doping region is located between the second side of the first gate structure and the first side of the second gate structure, and the third merged doping region is located on the second side of the second gate structure; Wherein, the second gate structure passes through the isolation structure surface and extends outward to the second region and covers a portion of the second region; Wherein, the first merged doping region, the first gate structure and the second merged doping region form a selection transistor; the second merged doping region, the second gate structure and the third merged doping region form a floating gate transistor; the second gate structure and the fourth merged doping region form a first metal oxide semiconductor capacitor; and the channel resistance value of the floating gate transistor is greater than the channel resistance value of the selection transistor.

2. The single polysilicon layer non-volatile memory cell as described in claim 1, wherein the first merged doping region includes a first ion implantation region and a first lightly doped drain region, the second merged doping region includes a second ion implantation region, a second lightly doped drain region and a third lightly doped drain region, the third merged doping region includes a third ion implantation region and a fourth lightly doped drain region; and, the first lightly doped drain region is located on the first side of the first gate structure, the second lightly doped drain region is located on the second side of the first gate structure, the third lightly doped drain region is located on the first side of the second gate structure, and the fourth lightly doped drain region is located on the second side of the second gate structure.

3. The single polysilicon layer non-volatile memory cell as described in claim 2, wherein the doping concentration of the first lightly doped drain region is equal to the doping concentration of the second lightly doped drain region, the doping concentration of the third lightly doped drain region is equal to the doping concentration of the fourth doped drain region, and the doping concentration of the fourth doped drain region is less than the doping concentration of the first doped drain region.

4. The single polysilicon layer non-volatile memory cell as described in claim 2, wherein the doping concentration of the fourth lightly doped drain region, the doping concentration of the third lightly doped drain region and the doping concentration of the second doped drain region are the same, and the doping concentration of the fourth doped drain region is less than the doping concentration of the first doped drain region.

5. The single polysilicon layer non-volatile memory cell as described in claim 2, wherein the doping concentration of the first lightly doped drain region, the doping concentration of the second lightly doped drain region and the doping concentration of the third doped drain region are the same, and the doping concentration of the fourth doped drain region is less than the doping concentration of the first doped drain region. 6 . The single polysilicon layer non-volatile memory cell as claimed in claim 2 , further comprising a first punch-back implanted region contacting the fourth lightly doped drain region. 7 . The single polysilicon layer nonvolatile memory cell as claimed in claim 2 , further comprising a first back punch-back implanted region contacting the third lightly doped drain region. 8 . The single polysilicon layer nonvolatile memory cell as claimed in claim 2 , further comprising a first counter-implantation implantation region contacting the fourth lightly doped drain region, and a second counter-implantation implantation region contacting the third lightly doped drain region.

9. The single polysilicon layer nonvolatile memory cell as claimed in claim 2, further comprising a first counter-implantation region contacting the fourth lightly doped drain region, a second counter-implantation region contacting the third lightly doped drain region, and a third counter-implantation region contacting the second lightly doped drain region.

10. The single polysilicon layer nonvolatile memory cell as claimed in claim 2, further comprising a first counter-implantation region contacting the fourth lightly doped drain region, a second counter-implantation region contacting the third lightly doped drain region, and a third counter-implantation region contacting the first lightly doped drain region. 11 . The single polysilicon layer non-volatile memory cell as claimed in claim 2 , further comprising a channel doping region located on the surface of the semiconductor substrate below the second gate structure, and the channel doping region and the second merged doping region have different doping types.

12. The single polysilicon layer nonvolatile memory cell as claimed in claim 1, further comprising a third gate structure formed on one side of the isolation structure and located at the second gate structure, the third gate structure and the second gate structure forming a first polysilicon / polysilicon planar capacitor.

13. The single polysilicon layer non-volatile memory cell as described in claim 12 further includes a fourth gate structure formed on the other side of the isolation structure located at the second gate structure, the fourth gate structure and the second gate structure form a second polysilicon / polysilicon flat panel capacitor, and the second polysilicon / polysilicon flat panel capacitor is connected in parallel with the first polysilicon / polysilicon flat panel capacitor.

14. The single polysilicon layer non-volatile memory cell as described in claim 12 further includes a metal layer formed above the second gate structure, the metal layer and the second gate structure form a metal / polysilicon flat plate capacitor, and the metal / polysilicon flat plate capacitor is connected in parallel with the first polysilicon / polysilicon flat plate capacitor.

15. The single polysilicon layer non-volatile memory cell as described in claim 12, wherein the third gate structure is connected to the auxiliary gate line, the first gate structure is connected to the selection gate line, the first merged doped region is connected to the source line, the third merged doped region is connected to the bit line, and the fourth merged doped region is connected to the erase line.

16. A single polysilicon layer non-volatile memory cell as described in claim 15, wherein during a programming action, the source line receives a ground voltage, the select gate line receives a programming voltage, the bit line receives the programming voltage, the erase line receives a first voltage range between the ground voltage and the erase voltage, the auxiliary gate receives a second voltage range between the ground voltage and the auxiliary gate voltage, the auxiliary gate voltage is greater than the erase voltage, the erase voltage is greater than the programming voltage, and the programming voltage is greater than the ground voltage.

17. A single polysilicon layer non-volatile memory cell as described in claim 15, wherein during an erase operation, the source line receives a ground voltage, the select gate line receives the ground voltage, the bit line receives the ground voltage, the erase line receives an erase voltage, the auxiliary gate receives a voltage range between a negative auxiliary gate voltage and the ground voltage, the auxiliary voltage is greater than the erase voltage, and the erase voltage is greater than the ground voltage.

18. A single polysilicon layer non-volatile memory cell as described in claim 15, wherein during a reading operation, the source line receives a ground voltage, the select gate line receives a read voltage, the bit line receives the read voltage, the erase line receives the ground voltage, the auxiliary gate receives a voltage range between a negative auxiliary gate voltage and a positive auxiliary gate voltage, the auxiliary gate voltage is greater than the read voltage, and the read voltage is greater than the ground voltage.

19. A single polysilicon layer non-volatile memory cell as described in claim 1, wherein the second gate structure includes an extension portion extending from the isolation structure surface to the third merged doping region, and the extension portion of the second gate structure and the third merged doping region form a second metal oxide semiconductor capacitor; wherein the first gate structure is connected to the selection gate line, the first merged doping region is connected to the source line, the third merged doping region is connected to the bit line, and the fourth merged doping region is connected to the erase line.

20. The single polysilicon layer nonvolatile memory cell of claim 1, wherein a channel length of the floating gate transistor is smaller than a channel length of the select transistor.

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