Forming method of memory device and memory device

Abstract

The invention provides a forming method of a memory device and the memory device. The forming method comprises the steps of providing a semiconductor substrate; a spin-orbit torque layer and a magnetic tunnel junction are sequentially formed on one side of the semiconductor substrate, so that the spin-orbit torque layer is located between the magnetic tunnel junction and the semiconductor substrate, and the side, away from the semiconductor substrate, of the spin-orbit torque layer is provided with an exposed area which is not covered by the magnetic tunnel junction; forming a first insulating dielectric layer on one side, far away from the semiconductor substrate, of the spin-orbit torque layer, so that the first insulating dielectric layer covers the exposed region and the magnetic tunnel junction; removing the part, covering the side wall of the magnetic tunnel junction, in the first insulating dielectric layer; the part, covering the exposed area, in the first insulating dielectric layer is thinned to form a target insulating dielectric layer, the target insulating dielectric layer covers the exposed area, and the side wall of a tunneling barrier layer of the magnetic tunnel junction is completely exposed. According to the invention, the problem of poor reliability of the memory device caused by metal backwash is solved.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a method for forming a memory device and a memory device. Background Art

[0002] With the rapid development of electronic technology, non-volatile memory has become the focus of research. Non-volatile memory has the characteristics of high density, fast reading and writing, and ultra-long working life, and has broad market application prospects. Among them, the magnetic random access memory (SOT-MRAM) based on spin-orbit-torque is a three-terminal device. Through the bottom heavy metal orbital layer (spin-orbit torque layer) to provide spin polarized current and combined with the auxiliary effect of STT spin current, the device flip speed can be as high as sub-ns, and the energy consumption of MRAM devices is further reduced, making it more suitable for fast SRAM cache replacement. In the manufacturing process of this magnetic random access memory, the magnetic tunnel junction (MTJ) etching process is the key to determine whether SOT-MRAM can be mass-produced. There are many etching problems generated in the etching process, such as damage and short circuit. These problems affect the morphology uniformity at the least, and will lead to performance degradation and yield deterioration in severe cases. It is a difficult problem that must be overcome and a practical problem that must be solved.

[0003] For example, in the SOT-MRAM etching process based on the TP architecture, the etching process is greatly challenged by the limitation of the bottom heavy metal track layer (spin-orbit torque layer). First, the heavy metal track electrode is too close to the tunneling barrier layer (dielectric layer, MgO), which causes the metal backsplashed in the MTJ etching process to produce secondary deposition (re-dep) and easily adhere to the tunneling barrier layer (dielectric layer, MgO) in the magnetic tunnel junction, resulting in short. Secondly, since the heavy metal track layer cannot be disconnected, the over-etching amount (OE) is greatly limited, which in turn reduces the ability and space to eliminate the secondary deposition (re-dep) metal. Summary of the invention

[0004] The main purpose of the present invention is to provide a method for forming a memory device and a memory device, so as to solve the problem of poor reliability of the memory device caused by metal backsplash in the prior art.

[0005] In order to achieve the above-mentioned purpose, according to one aspect of the present invention, a method for forming a memory device is provided, the forming method comprising: providing a semiconductor substrate; sequentially forming a spin-orbit torque layer and a magnetic tunnel junction on one side of the semiconductor substrate, so that the spin-orbit torque layer is located between the magnetic tunnel junction and the semiconductor substrate, and the side of the spin-orbit torque layer away from the semiconductor substrate has an exposed area not covered by the magnetic tunnel junction; forming a first insulating dielectric layer on the side of the spin-orbit torque layer away from the semiconductor substrate, so that the first insulating dielectric layer covers the exposed area and the magnetic tunnel junction; removing a portion of the first insulating dielectric layer covering the side wall of the magnetic tunnel junction; thinning a portion of the first insulating dielectric layer covering the exposed area to form a target insulating dielectric layer, the target insulating dielectric layer covers the exposed area, and the side wall of the tunnel barrier layer of the magnetic tunnel junction is completely exposed.

[0006] Furthermore, the step of forming a magnetic tunnel junction includes: covering a magnetic thin film functional layer and a hard mask layer on a side of the spin-orbit torque layer away from the semiconductor substrate, the hard mask layer being located on a side of the magnetic thin film functional layer away from the spin-orbit torque layer; and etching the magnetic thin film functional layer using emission spectra of the hard mask layer and the magnetic thin film functional layer to form a magnetic tunnel junction.

[0007] Furthermore, the thickness of the first insulating dielectric layer in a direction perpendicular to the spin-orbit torque layer is greater than the thickness of the magnetic tunnel junction.

[0008] Furthermore, the step of forming a first insulating dielectric layer includes: forming the first insulating dielectric layer using a chemical vapor deposition process, the first insulating dielectric layer having a step structure, the step structure including a first part and a second part having an angle, the first part covering the exposed area, and the second part covering the side wall of the magnetic tunnel junction.

[0009] Furthermore, the first part has a first thickness in the first direction, the second part has a second thickness in the second direction, and the ratio of the second thickness to the first thickness is greater than 0 and less than 0.7, wherein the first direction is a direction perpendicular to the spin-orbit torque layer, and the second direction is a direction perpendicular to the first direction.

[0010] Furthermore, the portion of the side wall of the magnetic tunnel junction in the first insulating dielectric layer is removed, including: using a dry etching process to etch the first insulating dielectric layer to remove the portion of the side wall of the magnetic tunnel junction in the first insulating dielectric layer, wherein the angle between the incident direction of the ion beam in the dry etching and the first direction is controlled to be 70° to 90°, and the first direction is a direction perpendicular to the spin-orbit torque layer.

[0011] Furthermore, the step of forming a target insulating dielectric layer includes: using a dry etching process to etch the first insulating dielectric layer to form a target insulating dielectric layer, wherein the angle between the ion beam incident direction in the dry etching process and the first direction is controlled to be 20° to 60°, and the first direction is the direction perpendicular to the spin-orbit torque layer.

[0012] Furthermore, the process of etching the magnetic thin film functional layer is selected from any one of ion beam etching, reactive ion etching, cyclotron resonance plasma etching and inductively coupled plasma etching.

[0013] Furthermore, the thickness of the first insulating dielectric layer is 10-30 nm.

[0014] According to another aspect of the present invention, a memory device is provided. The memory device is prepared by the above-mentioned memory device formation method, and the memory device includes: a semiconductor substrate having a first surface; a spin-orbit torque layer located on the first surface; a magnetic tunnel junction located on a side of the spin-orbit torque layer away from the semiconductor substrate, so that the spin-orbit torque layer is located between the magnetic tunnel junction and the semiconductor substrate, and the side of the spin-orbit torque layer away from the semiconductor substrate has an exposed area not covered by the magnetic tunnel junction; and a target insulating dielectric layer covering the exposed area.

[0015] The technical solution of the present invention is applied to provide a method for forming a memory device, wherein two removal steps are adopted in the process of removing the first insulating dielectric layer covering the exposed area of ​​the spin-orbit torque layer and the side wall of the magnetic tunnel junction, and the main removal objects are divided in the two removal steps, that is, in the step of removing the first insulating dielectric layer for the first time, the part covering the side wall of the magnetic tunnel junction is selected to be removed, so that in this step, part of the metal secondarily deposited on the side wall of the magnetic tunnel junction is first removed, and then in the step of removing the first insulating dielectric layer for the second time, the part covering the exposed area of ​​the spin-orbit torque layer is selected to be removed, and since the part covering the exposed area of ​​the spin-orbit torque layer also covers the exposed area of ​​the magnetic tunnel junction, the exposed area of ​​the magnetic tunnel junction is removed. The invention covers part of the side wall of the magnetic tunnel junction, so that in the process of removing the part of the exposed area covering the spin-orbit torque layer, the metal deposited on the side wall of the tunnel barrier layer in the magnetic tunnel junction can be further eliminated. At the same time, in the process of secondary removal of the secondary deposited backsplashed metal (the metal sputtered on the side wall of the tunnel barrier layer during the etching process to form the magnetic tunnel junction), the part of the exposed area covering the spin-orbit torque layer is only thinned but not completely removed. Therefore, when the secondary deposited backsplashed metal is removed, the metal of the spin-orbit torque layer is prevented from being splashed back onto the side wall of the tunnel barrier layer of the magnetic tunnel junction. Therefore, the present application solves the technical problem of poor reliability of the storage device caused by metal backsplashing. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the accompanying drawings:

[0017] Figure 1 A schematic diagram of the cross-sectional structure of a substrate after forming a first insulating dielectric layer in a method for forming a memory device according to an embodiment of the present invention is shown;

[0018] Figure 2 Shows the removal of Figure 1 A schematic diagram of the cross-sectional structure of the substrate behind the first insulating dielectric layer covering the side wall of the magnetic tunnel junction in the structure shown;

[0019] Figure 3 Shows the thinning Figure 2 A schematic diagram of the cross-sectional structure of the substrate behind the first insulating dielectric layer covering the exposed area in the structure shown;

[0020] Figure 4 A schematic cross-sectional structure diagram of a substrate after a first insulating dielectric layer is formed in a method for forming a memory device according to another embodiment of the present invention is shown;

[0021] Figure 5 A schematic cross-sectional structure diagram of a substrate after forming a first insulating dielectric layer in a method for forming a memory device according to yet another embodiment of the present invention is shown.

[0022] The above drawings include the following reference numerals:

[0023] 100, bottom metal interconnect structure; 10, spin-orbit torque layer; 201, free layer; 202, tunneling barrier layer; 203, reference layer; 20, magnetic tunnel junction; 30, hard mask layer; 40, first insulating dielectric layer; 50, target insulating dielectric layer. DETAILED DESCRIPTION

[0024] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0025] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0026] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the present invention described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0027] As mentioned in the background technology, in the SOT-MRAM etching process based on the TP architecture, the etching process is greatly challenged by the limitation of the bottom heavy metal track layer (spin-orbit torque layer). First, the heavy metal track electrode is too close to the tunneling barrier layer (dielectric layer, MgO). Since the metal splashed back in the MTJ etching process will produce secondary deposition (re-dep) and easily adhere to the tunneling barrier layer (dielectric layer, MgO) in the magnetic tunnel junction, the device will be short. Secondly, since the heavy metal track layer cannot be disconnected, the over-etching amount (OE) is greatly limited, which in turn reduces the ability and space to eliminate the secondary deposition (re-dep) metal, making the reliability of the storage device poor. Therefore, in order to solve the technical problem of poor reliability of the storage device caused by metal splashing, the present application proposes a method for forming a storage device and a storage device.

[0028] In some optional embodiments, a method for forming a memory device is provided, the method comprising: providing a semiconductor substrate; sequentially forming a spin-orbit torque layer 10 and a magnetic tunnel junction 20 on one side of the semiconductor substrate, so that the spin-orbit torque layer 10 is located between the magnetic tunnel junction 20 and the semiconductor substrate, and a side of the spin-orbit torque layer 10 away from the semiconductor substrate has an exposed area not covered by the magnetic tunnel junction 20; forming a first insulating dielectric layer 40 on a side of the spin-orbit torque layer 10 away from the semiconductor substrate, so that the first insulating dielectric layer 40 covers the exposed area and the magnetic tunnel junction 20, as shown in FIG. Figure 1 As shown; removing the first insulating dielectric layer 40 covering the side wall of the magnetic tunnel junction 20, as shown Figure 2 As shown; thinning the portion of the first insulating dielectric layer 40 covering the exposed area to form a target insulating dielectric layer 50, the target insulating dielectric layer 50 covers the exposed area, and the side wall of the tunnel barrier layer 202 of the magnetic tunnel junction 20 is completely exposed, as shown Figure 3 shown.

[0029] Specifically, Figure 1 As shown, the semiconductor substrate may include a plurality of bottom metal interconnect structures 100 spaced apart, and each bottom metal interconnect structure 100 has an exposed surface, and the spin-orbit torque layer 10 covers the exposed surface of each bottom metal interconnect structure 100, so that the plurality of bottom metal interconnect structures 100 are electrically connected to the spin-orbit torque layer 10. An insulating dielectric layer may be included between any two adjacent bottom metal interconnect structures 100, and optionally, the height of the insulating dielectric layer in the vertical direction is flush with the height of the bottom metal interconnect structure 100 in the vertical reverse direction, and the vertical direction is perpendicular to the direction in which any two bottom metal interconnect structures 100 are spaced apart.

[0030] Optionally, the surface of the semiconductor substrate covered by the spin-orbit torque layer 10 may include multiple exposed areas of multiple bottom metal interconnect structures 100. Optionally, the horizontal dimension of each bottom metal interconnect structure 100 may be 150-250 nm.

[0031] Optionally, the surface of one side of the semiconductor substrate covered by the spin-orbit torque layer 10 may also include an exposed area of ​​the insulating dielectric layer between any two adjacent bottom metal interconnect structures 100. After forming the above-mentioned bottom metal interconnect structure 100, an insulating material layer (not shown in the figure) may be deposited on one side of the bottom metal interconnect structure 100, so that the insulating material layer completely covers the above-mentioned multiple bottom metal interconnect structures 100, and then the above-mentioned insulating material may be planarized to expose the surface of the bottom metal interconnect structure 100.

[0032] Specifically, Figures 1 to 3 As shown, the magnetic tunnel junction 20 may include a stacked free layer 201, a tunneling barrier layer 202 and a reference layer 203, wherein the free layer 201 is in contact with the spin-orbit torque layer 10. Optionally, a hard mask layer 30 may be further included on the side of the reference layer 203 away from the tunneling barrier layer 202. Optionally, the thickness of the hard mask layer 30 may be 80 to 200 nm. Optionally, the material of the hard mask layer 30 may include but is not limited to tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN) and tungsten (W). Optionally, the hard mask layer 30 may also be a composite layer structure of metal and oxide.

[0033] Optionally, the magnetic tunnel junction 20 may include but is not limited to a single-layer barrier structure or a double-layer barrier structure. For example, the single-layer barrier structure may include a stacked free layer 201, a tunneling barrier layer 202, and a reference layer 203, and the double-layer barrier structure may include a stacked free layer 201, a tunneling barrier layer 202, a reference layer 203, and an oxide layer.

[0034] Specifically, Figures 1 to 3 As shown, the spin-orbit torque layer 10 is located between the semiconductor substrate and the magnetic tunnel junction 20, that is, the spin-orbit torque layer 10 can have a first vertical projection on the semiconductor substrate, and the magnetic tunnel junction 20 can have a second vertical projection on the semiconductor substrate, then the second vertical projection is located in the first vertical projection, and the area of ​​the first vertical projection is larger than the area of ​​the second vertical projection, so it can be understood that the spin-orbit torque layer 10 also includes an exposed area on the side surface away from the semiconductor substrate, and the exposed area is the portion of the surface of the spin-orbit torque layer 10 on the side surface away from the semiconductor substrate that is not covered by the magnetic tunnel junction 20.

[0035] Specifically, Figure 1 As shown, an insulating dielectric material can be deposited on the side of the spin-orbit torque layer 10 away from the semiconductor substrate to form a first insulating dielectric layer 40. The first insulating dielectric layer 40 can cover the exposed area in the surface of the side of the spin-orbit torque layer 10 away from the semiconductor substrate, all the side walls of the magnetic tunnel junction 20, and the side surface of the magnetic tunnel junction 20 away from the spin-orbit torque layer 10. Therefore, the first insulating dielectric layer 40 covers the above-mentioned exposed area and all the side walls of the tunnel barrier layer 202 in the above-mentioned magnetic tunnel junction 20. Optionally, the material of the first insulating dielectric layer 40 can include but is not limited to silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN) and silicon carbonitride (SiCN). Optionally, the above-mentioned insulating dielectric material can be deposited by chemical vapor deposition (PECVD), and the deposition temperature of the deposition process can be 200-300°C.

[0036] Specifically, the first insulating dielectric layer 40 may include a portion covering the above-mentioned exposed area of ​​the spin-orbit torque layer 10 and a portion covering the side wall of the magnetic tunnel junction 20. It can be understood that the portion of the first insulating dielectric layer 40 covering the side wall of the magnetic tunnel junction 20 can be located on the side of the portion of the first insulating dielectric layer 40 covering the above-mentioned exposed area of ​​the spin-orbit torque layer 10 away from the spin-orbit torque layer 10, so that in the direction perpendicular to the spin-orbit torque layer 10, the height of the portion of the first insulating dielectric layer 40 covering the side wall of the magnetic tunnel junction 20 above the portion of the first insulating dielectric layer 40 covering the above-mentioned exposed area of ​​the spin-orbit torque layer 10 will change with the change of the thickness of the portion of the first insulating dielectric layer 40 covering the above-mentioned exposed area of ​​the spin-orbit torque layer 10.

[0037] Exemplarily, the portion of the exposed area in the first insulating dielectric layer 40 covering the spin-orbit torque layer 10 may have a first extension height in a direction perpendicular to the spin-orbit torque layer 10, and the first extension height may be higher than the maximum height of the tunneling barrier layer 202 of the magnetic tunnel junction 20 from the spin-orbit torque layer 10, and the first extension height may also be lower than the maximum height of the tunneling barrier layer 202 of the magnetic tunnel junction 20 from the spin-orbit torque layer 10 and higher than the minimum height of the tunneling barrier layer 202 of the magnetic tunnel junction 20 from the spin-orbit torque layer 10.

[0038] Specifically, in a specific exemplary embodiment, in the case where the first extension height is higher than the maximum height of the tunneling barrier layer 202 of the magnetic tunnel junction 20 from the spin-orbit torque layer 10, it can be considered that the portion of the first insulating dielectric layer 40 covering the side wall of the magnetic tunnel junction 20 and the portion of the first insulating dielectric layer 40 covering the exposed area of ​​the spin-orbit torque layer 10 are the same portion, so that the removal of the portion of the first insulating dielectric layer 40 covering the side wall of the magnetic tunnel junction 20 can be considered as a first thinning of the portion of the first insulating dielectric layer 40 covering the exposed area of ​​the spin-orbit torque layer 10, such as Figure 2 shown.

[0039] Furthermore, in the above example, after removing the portion of the first insulating dielectric layer 40 covering the side wall of the magnetic tunnel junction 20 (i.e., the above first thinning), the remaining portion of the above exposed area covering the spin-orbit torque layer 10 may have a second extension height, and the second extension height may be higher than the minimum height of the tunneling barrier layer 202 of the magnetic tunnel junction 20 from the spin-orbit torque layer 10 and lower than the maximum height of the tunneling barrier layer 202 of the magnetic tunnel junction 20 from the spin-orbit torque layer 10; or the second extension height may still be higher than the maximum height of the tunneling barrier layer 202 of the magnetic tunnel junction 20 from the spin-orbit torque layer 10, but lower than the above first extension height, such as Figure 2 Then, the first insulating dielectric layer 40 remaining after the first thinning can be thinned for the second time, so that after the target insulating dielectric layer 50 is formed, the sidewall of the tunnel barrier layer 202 in the magnetic tunnel junction 20 is completely exposed and the target insulating dielectric layer 50 covers the exposed area, as shown in FIG. Figure 3 shown.

[0040] Specifically, in another specific exemplary embodiment, the first extension height is lower than the maximum height of the tunneling barrier layer 202 of the magnetic tunnel junction 20 from the spin-orbit torque layer 10 and higher than the minimum height of the tunneling barrier layer 202 of the magnetic tunnel junction 20 from the spin-orbit torque layer 10, so that part of the sidewall of the tunneling barrier layer 202 of the magnetic tunnel junction 20 can be covered by the part of the first insulating dielectric layer 40 covering the sidewall of the magnetic tunnel junction 20, and another part of the sidewall of the tunneling barrier layer 202 of the magnetic tunnel junction 20 can be covered by the part of the first insulating dielectric layer 40 covering the above-mentioned exposed area of ​​the spin-orbit torque layer 10. Therefore, after removing the part of the first insulating dielectric layer 40 covering the above-mentioned magnetic tunnel junction 20, part of the sidewall of the tunneling barrier layer 202 can still be covered by the part of the first insulating dielectric layer 40 covering the above-mentioned exposed area of ​​the spin-orbit torque layer 10. Furthermore, the portion of the first insulating dielectric layer 40 covering the exposed area of ​​the spin-orbit torque layer 10 can be thinned, so that after forming the target insulating dielectric layer 50, the sidewall of the tunneling barrier layer 202 in the magnetic tunnel junction 20 is completely exposed and the target insulating dielectric layer 50 covers the exposed area.

[0041] That is, the formation method of the above-mentioned memory device adopted in the present application adopts two removal steps in the process of removing the first insulating dielectric layer 40 covering the exposed area of ​​the spin-orbit torque layer 10 and the side wall of the magnetic tunnel junction 20, and the main removal objects are divided in the two removal steps, that is, in the step of removing the first insulating dielectric layer 40 for the first time, the part covering the side wall of the magnetic tunnel junction 20 is selected to be removed, so that in this step, part of the metal secondarily deposited on the side wall of the magnetic tunnel junction 20 is first removed, and then in the step of removing the first insulating dielectric layer 40 for the second time, the part covering the exposed area of ​​the spin-orbit torque layer 10 is selected to be removed, and because the part covering the exposed area of ​​the spin-orbit torque layer 10 is also covered by the magnetic tunnel junction, the exposed area of ​​the magnetic tunnel junction 20 is removed. The exposed area of ​​the magnetic tunnel junction 20 is partially removed by the thinning method, and the metal deposited on the side wall of the tunnel barrier layer 202 in the magnetic tunnel junction 20 can be further eliminated in the process of removing the part of the exposed area covering the spin-orbit torque layer 10. At the same time, since the part of the exposed area covering the spin-orbit torque layer 10 is only thinned but not completely removed in the process of secondary removal of the secondary deposited backsplashed metal (the metal sputtered on the side wall of the tunnel barrier layer 202 in the process of etching to form the magnetic tunnel junction 20), the metal of the spin-orbit torque layer 10 is avoided from being splashed back onto the side wall of the tunnel barrier layer 202 of the magnetic tunnel junction 20 when the secondary deposited backsplashed metal is removed. Therefore, the present application solves the technical problem of poor reliability of the storage device caused by metal backsplashing.

[0042] The exemplary embodiments of the method for forming a memory device provided according to the present invention will be described in more detail below. However, these exemplary embodiments can be implemented in a variety of different forms and should not be construed as being limited to the embodiments set forth herein. It should be understood that these embodiments are provided to make the disclosure of this application thorough and complete, and to fully convey the conception of these exemplary embodiments to those of ordinary skill in the art.

[0043] In some optional embodiments, in order to protect the above-mentioned storage device, the above-mentioned formation method may also include forming a dielectric protection layer on the side of the target insulating dielectric layer away from the semiconductor substrate, and the dielectric protection layer may cover the sidewalls and upper surface of the above-mentioned target insulating dielectric layer and the magnetic tunnel junction, and the upper surface is the surface of the side of the magnetic tunnel junction away from the spin-orbit torque layer. Optionally, the material of the dielectric protection layer may include but is not limited to silicon nitride (SiN), silicon carbonitride (SiCN) and silicon oxycarbide (SiOC). Optionally, the precursor or reactant of the above-mentioned dielectric protection layer may include but is not limited to methane silicon (SiH4), hexamethylcyclotrisilazane (C6H 21 N3Si3) or trimethylsilane (C3H 10 Alternatively, the dielectric protection layer may be formed by using a PECVD process or an atomic layer deposition process (ALD).

[0044] In some optional embodiments, in order to form a magnetic tunnel junction on the side of the spin-orbit torque layer away from the semiconductor substrate and prevent over-etching from damaging the spin-orbit torque layer during the formation of the magnetic tunnel junction, the steps of forming the magnetic tunnel junction include: covering the side of the spin-orbit torque layer away from the semiconductor substrate with a magnetic thin film functional layer and a hard mask layer, wherein the hard mask layer is located on the side of the magnetic thin film functional layer away from the spin-orbit torque layer; etching the magnetic thin film functional layer using the emission spectra of the hard mask layer and the magnetic thin film functional layer to form the magnetic tunnel junction.

[0045] The magnetic thin film functional layer may include a first ferromagnetic layer, an oxide layer and a second ferromagnetic layer, wherein the first ferromagnetic layer is used to form a free layer of a magnetic tunnel junction, the oxide layer is used to form a tunneling barrier layer of the magnetic tunnel junction, and the second ferromagnetic layer is used to form a reference layer of the magnetic tunnel junction. Optionally, after forming the magnetic thin film functional layer, a spectrometer or other spectral analysis equipment may be used to record the initial emission spectrum of the material corresponding to the magnetic thin film functional layer.

[0046] Specifically, the hard mask layer has a preset pattern, which is used to prevent part of the magnetic thin film functional layer from being removed, so that the part of the magnetic thin film functional layer that is not removed forms a magnetic tunnel junction, and in the process of removing part of the magnetic thin film functional layer using the hard mask layer, the emission spectrum of the magnetic thin film functional layer can be recorded periodically or continuously, so that the initial light emission spectrum and the spectrum during the etching process can be compared to calculate the intensity change of the spectral line, and then the etching depth of the magnetic thin film functional layer can be determined according to the intensity change of the spectral line, thereby avoiding over-etching of the magnetic thin film functional layer to damage the spin-orbit torque layer, and achieving the purpose of accurately controlling the etching stop position.

[0047] Optionally, the etching process for etching the magnetic thin film functional layer to form the magnetic tunnel junction may be selected from any one of ion beam etching, reactive ion etching, cyclotron resonance plasma etching and inductively coupled plasma etching.

[0048] Alternatively, if Figure 1 As shown, the first insulating dielectric layer 40 can be formed by a chemical vapor deposition process. In some optional embodiments, in order to make the first insulating dielectric layer 40 cover the exposed area of ​​the spin-orbit torque layer 10 and the side wall of the magnetic tunnel junction 20, the thickness of the first insulating dielectric layer 40 in a direction perpendicular to the spin-orbit torque layer 10 is greater than the thickness of the magnetic tunnel junction 20.

[0049] Specifically, Figure 1 As shown, the semiconductor substrate includes a bottom metal interconnect structure 100, a spin-orbit torque track layer covers the bottom metal interconnect structure 100, a magnetic tunnel junction 20 is located on the above-mentioned spin-orbit torque track layer, and the magnetic tunnel junction 20 may include a stacked free layer 201, a tunneling barrier layer 202, a reference layer 203 and a hard mask layer 30, and then a thicker insulating material layer can be deposited on the side of the spin-orbit torque track layer away from the bottom metal interconnect structure 100, and the insulating material layer completely covers the magnetic tunnel junction 20 and the spin-orbit torque layer 10, and then the insulating material layer can be flattened by chemical flattening, thereby forming a first insulating dielectric layer 40.

[0050] The first insulating dielectric layer 40 can then be etched at an angle perpendicular to the spin-orbit torque layer 10, so that a portion of the first insulating dielectric layer 40 covering the sidewall of the magnetic tunnel junction 20 is removed, while a portion of the first insulating dielectric layer 40 covering the exposed area of ​​the spin-orbit torque layer 10 is retained, such as Figure 2 shown.

[0051] Then, the etching angle and etching energy can be changed to thin the part of the first insulating dielectric layer 40 covering the exposed area of ​​the spin-orbit torque layer 10, so that the entire side wall of the tunneling barrier layer 202 is completely exposed, and the purpose of secondary cleaning of the back-splashed metal on the side wall of the tunneling barrier layer 202 is achieved. It should be noted that at this time, the exposed area of ​​the spin-orbit torque layer 10 is still covered by part of the first insulating dielectric layer 40, such as Figure 3 shown.

[0052] Optionally, in some other optional embodiments, in order to make the first insulating dielectric layer 40 cover the exposed area of ​​the spin-orbit torque layer 10 and the sidewall of the magnetic tunnel junction 20, the step of forming the first insulating dielectric layer 40 includes: forming the first insulating dielectric layer 40 by a chemical vapor deposition process, wherein the first insulating dielectric layer 40 has a step structure, wherein the step structure includes a first portion and a second portion having an angle, wherein the first portion covers the exposed area, and the second portion covers the sidewall of the magnetic tunnel junction 20, such as Figure 4 and Figure 5 shown.

[0053] Specifically, the step coverage of the film growth (the ratio of the thickness of the first insulating dielectric layer 40 in the direction perpendicular to the sidewall to the thickness of the first insulating dielectric layer 40 in the direction perpendicular to the spin-orbit torque layer 10) can be adjusted during the deposition and growth of the first insulating dielectric layer 40, so that the thickness of the portion of the first insulating dielectric layer 40 covering the sidewall of the magnetic tunnel junction 20 is thinner, while the thickness of the portion of the first insulating dielectric layer 40 covering the exposed area of ​​the spin-orbit torque layer 10 is thicker. Optionally, the ratio of the thickness of the first insulating dielectric layer 40 in the direction perpendicular to the sidewall to the thickness of the first insulating dielectric layer 40 in the direction perpendicular to the spin-orbit torque layer 10 can also be less than 0.4, such as Figure 4 As shown, the etching process of the first insulating dielectric layer 40 on the sidewall can be saved in the subsequent etching process of the sidewall, and the first insulating dielectric layer 40 covering the exposed area of ​​the spin-orbit torque layer 10 can be directly thinned until the entire sidewall of the tunnel barrier layer 202 is exposed.

[0054] Optionally, in some embodiments, in order to make the exposed area of ​​the spin-orbit torque layer 10 still covered by the first insulating dielectric layer 40 after removing the portion of the first insulating dielectric layer 40 covering the sidewall of the magnetic tunnel junction 20, the first portion is made to have a first thickness in the first direction, the second portion is made to have a second thickness in the second direction, and the ratio of the second thickness to the first thickness is greater than 0 and less than 0.7, such as Figure 5 As shown, the first direction A is a direction perpendicular to the spin-orbit torque layer 10, and the second direction B is a direction perpendicular to the first direction.

[0055] In some optional embodiments, the removing of the portion of the first insulating dielectric layer 40 covering the sidewall of the magnetic tunnel junction 20 includes: etching the first insulating dielectric layer 40 using a dry etching process to remove the portion of the first insulating dielectric layer 40 covering the sidewall of the magnetic tunnel junction 20, such as Figure 2 As shown, the angle between the incident direction of the ion beam in the dry etching and the first direction is controlled to be 70° to 90°, and the first direction is a direction perpendicular to the spin-orbit torque layer 10 .

[0056] In the above embodiment, the above dry etching may include but is not limited to ion beam etching, reactive ion etching, cyclotron resonance plasma etching or inductively coupled plasma etching, that is, ion beam etching, reactive ion etching, cyclotron resonance plasma etching or inductively coupled plasma etching may be used to etch the portion of the first insulating dielectric layer 40 covering the entire side wall of the tunneling barrier layer 202 in the magnetic tunnel junction 20.

[0057] Specifically, the first direction is the direction perpendicular to the spin-orbit torque layer 10. When etching the portion of the first insulating dielectric layer 40 covering the side wall of the magnetic tunnel junction 20, the stage in the ion etching reaction chamber can be controlled to rotate at a first preset angle, so that the incident angle between the incident direction of the ion beam and the first direction is 70° to 90°. This allows the faster lateral etching feature to be utilized to first remove the portion of the first insulating dielectric layer 40 covering the side wall of the magnetic tunnel junction 20, while the exposed area of ​​the spin-orbit torque layer 10 is also covered with the portion of the first insulating dielectric layer 40 that has not been etched by the ion beam.

[0058] In some optional embodiments, the step of forming the target insulating dielectric layer 50 includes: etching the first insulating dielectric layer 40 using a dry etching process to form the target insulating dielectric layer 50, such as Figure 3 As shown, the angle between the ion beam incident direction in the dry etching process and the first direction is controlled to be 20° to 60°, and the first direction is a direction perpendicular to the spin-orbit torque layer 10 .

[0059] Similarly, the dry etching in the above-mentioned embodiment may also include but is not limited to ion beam etching, reactive ion etching, cyclotron resonance plasma etching or inductively coupled plasma etching, that is, ion beam etching, reactive ion etching, cyclotron resonance plasma etching or inductively coupled plasma etching may be used to etch the exposed area of ​​the first insulating dielectric layer 40 covering the spin-orbit torque layer 10.

[0060] Specifically, when etching the exposed area of ​​the first insulating dielectric layer 40 covering the spin-orbit torque layer 10, the stage in the ion etching reaction chamber can be controlled to rotate by a second preset angle, so that the incident angle between the incident direction of the ion beam and the first direction is 20° to 60°, thereby further removing the exposed area of ​​the first insulating dielectric layer 40 covering the spin-orbit torque layer 10. It should be noted that, if Figure 3 As shown, in this step, in order to prevent the metal of the spin-orbit torque layer 10 from splashing back to the side wall of the tunneling barrier layer 202 of the magnetic tunnel junction 20, the portion covering the exposed area of ​​the spin-orbit torque layer 10 can be thinned, so that after the side wall of the tunneling barrier layer 202 is completely exposed, the exposed area of ​​the spin-orbit torque layer 10 is still covered by a portion of the first insulating dielectric layer 40, and the portion of the first insulating dielectric layer 40 is the above-mentioned target insulating dielectric layer 50. Optionally, the energy of the ion beam in the etching step can be less than the ion beam energy of removing the portion of the first insulating dielectric layer 40 covering the side wall of the tunneling barrier layer 202. Optionally, in order to increase the cleaning time of the tunneling barrier layer 202 on the basis of thinning the portion of the first insulating dielectric layer 40 covering the exposed area, the selectivity can also be adjusted by ion beam etching or reactive ion etching, so that the cleaning process window for cleaning the tunneling barrier layer 202 can be further increased.

[0061] Optionally, in order to ensure that after removing part of the first insulating dielectric layer, the remaining target insulating dielectric layer still covers the exposed area of ​​the spin-orbit torque layer, the thickness of the first insulating dielectric layer may be 10-30 nm.

[0062] According to another aspect of the present invention, a memory device is provided, which is prepared by the above-mentioned memory device formation method, and the above-mentioned memory device comprises: a semiconductor substrate having a first surface; a spin-orbit torque layer located on the above-mentioned first surface; a magnetic tunnel junction located on a side of the above-mentioned spin-orbit torque layer away from the above-mentioned semiconductor substrate, so that the above-mentioned spin-orbit torque layer is located between the above-mentioned magnetic tunnel junction and the above-mentioned semiconductor substrate, and the side of the above-mentioned spin-orbit torque layer away from the above-mentioned semiconductor substrate has an exposed area not covered by the above-mentioned magnetic tunnel junction; and a target insulating dielectric layer covering the above-mentioned exposed area.

[0063] In the above embodiment, since the memory device is manufactured by the above memory device forming method, there is no secondary deposited metal on the sidewall of the tunnel barrier layer of the magnetic tunnel junction, thereby preventing the memory device from short circuiting and improving the reliability of the memory device.

[0064] From the above description, it can be seen that the above embodiments of the present invention achieve the following technical effects:

[0065] 1) Since two removal steps are adopted in the process of removing the first insulating dielectric layer covering the exposed area of ​​the spin-orbit torque layer and the side wall of the magnetic tunnel junction, and the main removal objects are divided in the two removal steps, that is, in the step of removing the first insulating dielectric layer for the first time, the portion covering the side wall of the magnetic tunnel junction is selected to be removed, so that in this step, part of the metal secondarily deposited on the side wall of the magnetic tunnel junction is first removed, and then in the step of removing the first insulating dielectric layer for the second time, the portion covering the exposed area of ​​the spin-orbit torque layer is selected to be removed, and since the portion covering the exposed area of ​​the spin-orbit torque layer also covers part of the side wall of the magnetic tunnel junction, in the process of removing the portion covering the exposed area of ​​the spin-orbit torque layer, the metal secondarily deposited on the side wall of the tunnel barrier layer in the magnetic tunnel junction can be further eliminated,

[0066] 2) During the secondary removal of the secondary deposited backsplashed metal (the metal sputtered on the side wall of the tunneling barrier layer during the etching process to form the magnetic tunnel junction), the exposed area covering the spin-orbit torque layer is only thinned but not completely removed. Thus, when the secondary deposited backsplashed metal is secondary removed, the metal of the spin-orbit torque layer is prevented from splashing back onto the side wall of the tunneling barrier layer of the magnetic tunnel junction. Therefore, the present application solves the technical problem of poor reliability of the storage device due to metal splashing.

[0067] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for forming a memory device, characterized in that: The forming method comprises: providing a semiconductor substrate; A spin-orbit torque layer and a magnetic tunnel junction are sequentially formed on one side of the semiconductor substrate, so that the spin-orbit torque layer is located between the magnetic tunnel junction and the semiconductor substrate, and a side of the spin-orbit torque layer away from the semiconductor substrate has an exposed area not covered by the magnetic tunnel junction; forming a first insulating dielectric layer on a side of the spin-orbit torque layer away from the semiconductor substrate, so that the first insulating dielectric layer covers the exposed area and the magnetic tunnel junction; removing a portion of the first insulating dielectric layer that covers a side wall of the magnetic tunnel junction; The portion of the first insulating dielectric layer covering the exposed area is thinned to form a target insulating dielectric layer, wherein the target insulating dielectric layer covers the exposed area and completely exposes the sidewall of the tunnel barrier layer of the magnetic tunnel junction.

2. The forming method according to claim 1, characterized in that: The steps of forming the magnetic tunnel junction include: A magnetic film functional layer and a hard mask layer are covered on a side of the spin-orbit torque layer away from the semiconductor substrate, wherein the hard mask layer is located on a side of the magnetic film functional layer away from the spin-orbit torque layer; The magnetic thin film functional layer is etched using the emission spectra of the hard mask layer and the magnetic thin film functional layer to form the magnetic tunnel junction.

3. The forming method according to claim 1, characterized in that: The thickness of the first insulating dielectric layer in a direction perpendicular to the spin-orbit torque layer is greater than the thickness of the magnetic tunnel junction.

4. The forming method according to claim 1, characterized in that: The step of forming the first insulating dielectric layer comprises: The first insulating dielectric layer is formed by chemical vapor deposition process. The first insulating dielectric layer has a step structure. The step structure includes a first part and a second part with an angle. The first part covers the exposed area, and the second part covers the sidewall of the magnetic tunnel junction.

5. The forming method according to claim 4, characterized in that: The first part has a first thickness in a first direction, the second part has a second thickness in a second direction, and a ratio of the second thickness to the first thickness is greater than 0 and less than 0.7, wherein the first direction is a direction perpendicular to the spin-orbit torque layer, and the second direction is a direction perpendicular to the first direction.

6. The forming method according to any one of claims 1 to 5, characterized in that: The removing of the portion of the first insulating dielectric layer covering the sidewall of the magnetic tunnel junction comprises: The first insulating dielectric layer is etched by dry etching to remove a portion of the first insulating dielectric layer covering the side wall of the magnetic tunnel junction. The angle between the incident direction of the ion beam in the dry etching and the first direction is controlled to be 70° to 90°, and the first direction is a direction perpendicular to the spin-orbit moment layer.

7. The forming method according to any one of claims 1 to 5, characterized in that: The step of forming the target insulating dielectric layer comprises: The first insulating dielectric layer is etched by dry etching to form the target insulating dielectric layer. The angle between the incident direction of the ion beam in the dry etching process and the first direction is controlled to be 20° to 60°, and the first direction is a direction perpendicular to the spin-orbit moment layer.

8. The forming method according to claim 2, characterized in that: The process for etching the magnetic thin film functional layer is selected from any one of ion beam etching, reactive ion etching, cyclotron resonance plasma etching and inductively coupled plasma etching.

9. The forming method according to any one of claims 1 to 5, characterized in that: The thickness of the first insulating dielectric layer is 10-30 nm.

10. A memory device, the memory device being prepared by the method for forming a memory device according to any one of claims 1 to 9, characterized in that: The storage device comprises: A semiconductor substrate having a first surface; A spin-orbit torque layer located on the first surface; A magnetic tunnel junction is located on a side of the spin-orbit torque layer away from the semiconductor substrate, so that the spin-orbit torque layer is located between the magnetic tunnel junction and the semiconductor substrate, and the side of the spin-orbit torque layer away from the semiconductor substrate has an exposed area not covered by the magnetic tunnel junction; The target insulating dielectric layer covers the exposed area.

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