A high-voltage BJT device using SiC BCD technology and its fabrication method

Abstract

The application relates to a high-voltage BJT device applying a SiC BCD process and a preparation method thereof, and the high-voltage BJT device comprises a drift region, a collector region extending from the surface of the drift region to the inside of the drift region, a collector electrode located on the collector region, a current guide layer located on the drift region and spaced apart from the collector region, a JTE-GR terminal junction extending from the surface of the drift region to the inside of the drift region and located between the collector region and the current guide layer, a base region located on the current guide layer, a base region ohmic contact region extending from the surface of the base region to the inside of the base region, a base electrode located on the base region ohmic contact region, an emitter region located on the base region and spaced apart from the base region ohmic contact region, an emitter electrode located on the emitter region, and the base electrode is located between the emitter electrode and the collector electrode. The embodiment of the application combines the advantages of the JTE terminal and the GR terminal, so that the terminal junction can bear higher blocking voltage, and the sensitivity of the terminal junction to the concentration is reduced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a high-voltage BJT device using SiC BCD technology and its fabrication method. Background Technology

[0002] With the development of microelectronics technology, high-voltage integrated circuits (HVICs) are becoming increasingly important in various high-voltage, high-power applications. Among these applications, lateral high-voltage SiC bipolar junction transistors (BJTs) have attracted significant attention due to their superior performance. As a third-generation semiconductor material, SiC possesses a wider bandgap, higher breakdown electric field, higher thermal conductivity, higher electron saturation velocity, and radiation resistance, giving it significant advantages in high-temperature, high-frequency, and radiation-resistant high-power devices.

[0003] SiC BJTs possess advantages such as high breakdown voltage, low on-resistance, high switching frequency, and high-temperature reliability. However, to further enhance SiC BJT performance, especially in high-voltage integrated circuit applications, termination design is crucial. Currently, some common termination design techniques include Junction Termination Extension (JTE) and Floating Field Limiting Rings (FFLRs). The JTE structure, by adding a highly doped buffer layer at the junction termination, can effectively modulate the surface electric field of the device, thereby increasing the breakdown voltage. The FFLR structure, by forming a field limiting ring at the junction termination, can further modulate the surface electric field, increasing the breakdown voltage. However, both of these termination structures suffer from high charge sensitivity and the appearance of electric field peaks. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a high-voltage BJT device using SiC BCD technology and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] This invention provides a high-voltage BJT device using SiC BCD technology, comprising:

[0006] Drift zone;

[0007] The collector region extends from the surface of the drift region into the interior of the drift region;

[0008] The collector is located on the collector region;

[0009] A current-guiding layer is located on the drift region and spaced apart from the current-collecting region;

[0010] The JTE-GR terminal junction extends from the surface of the drift region to the interior of the drift region and is located between the collector region and the current-conducting layer, wherein the JTE-GR terminal junction is formed by alternating distribution of GR terminal regions and JTE terminal regions and the GR terminal regions are located outside the JTE terminal regions;

[0011] The base region is located on the flow guide layer;

[0012] The base region ohmic contact area extends from the surface of the base region to the interior of the base region;

[0013] The base is located on the ohmic contact region of the base region;

[0014] The transmitting region is located on the base region and is spaced apart from the ohmic contact region of the base region;

[0015] An emitter is located on the emitter region, and the base is located between the emitter and the collector.

[0016] In one embodiment of the present invention, the JTE-GR terminal junction includes a plurality of GR terminal regions and a plurality of JTE terminal regions, wherein,

[0017] The plurality of GR terminal areas are spaced apart; the plurality of JTE terminal areas are distributed between two adjacent GR terminal areas and are in contact with the GR terminal areas;

[0018] The doping concentration of the GR terminal region is greater than that of the JTE terminal region, and the depth of the GR terminal region is greater than that of the JTE terminal region.

[0019] In one embodiment of the present invention, the drift region is an N-type drift region, the guide layer is a P-type guide layer, the base region is a P-type base region, and the emission region is an N-type emission region.

[0020] In one embodiment of the present invention, an N-type ohmic contact is formed between the collector electrode and the collector region;

[0021] A P-type ohmic contact is formed between the base and the ohmic contact region of the base region;

[0022] An N-type ohmic contact is formed between the emitter and the emitter region.

[0023] In one embodiment of the invention, a RESURF region and a substrate are further included, wherein,

[0024] The RESURF region is located on the surface of the drift region away from the collector region;

[0025] The substrate is located on the surface of the RESURF region away from the drift region.

[0026] In one embodiment of the present invention, the RESURF region is a P-type epitaxial layer.

[0027] Another embodiment of the present invention provides a method for fabricating a high-voltage BJT device using SiC BCD technology, comprising the following steps:

[0028] A guide layer and a base region are sequentially grown on the drift region, and an emission region is grown on the base region;

[0029] Ion implantation is performed in the base region to form a base region ohmic contact region that is spaced apart from the emitter region;

[0030] Ion implantation is performed in the drift region to form a JTE-GR terminal junction spaced apart from the flow guide layer;

[0031] Ion implantation is performed in the drift region to form a collector region spaced apart from the JTE-GR terminal junction, wherein the JTE-GR terminal junction is located between the collector region and the current-carrying layer;

[0032] Metals are fabricated on the emitter region, the ohmic contact region of the base region, and the collector region to form the emitter, base, and collector.

[0033] In one embodiment of the present invention, ion implantation is performed in the drift region to form a JTE-GR terminal junction spaced apart from the flux layer, including:

[0034] The first ion implantation is performed in the drift region to form a plurality of GR terminal regions spaced apart.

[0035] A second ion implantation is performed between two adjacent GR terminal regions to form a plurality of JTE terminal regions in contact with the GR terminal regions, wherein the doping concentration of the GR terminal regions is greater than that of the JTE terminal regions, and the depth of the GR terminal regions is greater than that of the JTE terminal regions.

[0036] In one embodiment of the present invention, before forming the emitter, base, and collector electrodes by fabricating metal on the emitter region, the base ohmic contact region, and the collector region, the method further includes the following step:

[0037] A contact metal is deposited on the ohmic contact region of the base region to form a P-type ohmic contact;

[0038] Contact metal is deposited on the emitter region and the collector region to form an N-type ohmic contact.

[0039] In one embodiment of the present invention, before sequentially growing the guiding layer and the base region on the drift region, the method further includes the following step:

[0040] The RESURF region and the drift region are epitaxially grown sequentially on the substrate.

[0041] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0042] 1. In this invention, a JTE-GR terminal junction is provided in the drift region between the collector region and the current-conducting layer, and the GR terminal junction is located at both ends of the JTE terminal junction. The GR terminal junction can effectively adjust the end electric field of the JTE terminal junction. This JTE-GR terminal junction combines the advantages of JTE and GR terminals, so that the terminal junction can withstand higher blocking voltage while reducing the sensitivity of the terminal junction to concentration, solving the problem of strong electric field peak and improving the stability of the terminal junction.

[0043] 2. The present invention provides a RESURF region on the back side of the drift region, which reduces the surface electric field of the device and thereby improves the breakdown voltage of the device. Attached Figure Description

[0044] Figure 1 A schematic diagram of a high-voltage BJT device using SiC BCD technology is provided for an embodiment of the present invention;

[0045] Figures 2a-2g This is a schematic flowchart illustrating a method for fabricating a high-voltage BJT device using SiC BCD technology, as provided in an embodiment of the present invention. Detailed Implementation

[0046] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0047] Example 1

[0048] Please see Figure 1 , Figure 1 This is a schematic diagram of a high-voltage BJT device using SiC BCD technology, provided as an embodiment of the present invention. The high-voltage BJT device has a lateral BJT structure, including: a drift region 3; a collector region 4 extending from the surface of the drift region 3 to its interior; a collector 5 located on the collector region 4; a current-conducting layer 7 located on the drift region 3 and spaced apart from the collector region 4; a JTE-GR termination junction 6 extending from the surface of the drift region 3 to its interior and located between the collector region 4 and the current-conducting layer 7, wherein the JTE-GR termination junction is formed by alternating GR termination regions and JTE termination regions, with the GR termination region located outside the JTE termination region; a base region 8 located on the current-conducting layer 7; a base ohmic contact region 9 extending from the surface of the base region 8 to its interior; a base 10 located on the base ohmic contact region 9; an emitter region 11 located on the base region 8 and spaced apart from the base ohmic contact region 9; and an emitter 12 located on the emitter region 11, with the base 10 located between the emitter 12 and the collector 5.

[0049] Specifically, in the vertical direction, the high-voltage BJT device includes, from bottom to top: a drift region 3, a current-conducting layer 7 and a base region 8 epitaxially grown sequentially on one side surface of the drift region 3, and an emitter region 11 epitaxially grown on one side surface of the base region 8; in the planar direction, a current-collecting region 4 and a JTE-GR terminal junction 6 are formed by ion implantation on the surface of the drift region 3, and the JTE-GR terminal junction 6 is spaced between the current-conducting layer 7 and the current-collecting region 4; a base region ohmic contact region 9 is formed by ion implantation on the surface of the base region 8, and the base region ohmic contact region 9 is spaced apart from the emitter region 11; and the emitter 12, the base 10, and the collector 5 are arranged sequentially in the horizontal direction.

[0050] Specifically, the JTE-GR terminal junction 6 is formed by alternating distribution of junction termination extension (JTE) terminal regions and guard ring (GR) terminal regions, with the GR terminal regions located outside the JTE terminal regions to form a GR ring that surrounds the JTE terminal regions. That is, the two ends of the JTE-GR terminal junction 6 are GR terminal regions, and the JTE terminal regions and GR terminal regions are alternately distributed between the two GR terminal regions.

[0051] In this embodiment, a JTE-GR termination junction is set in the drift region between the collector region and the current-conducting layer, and the GR termination region is located at both ends of the JTE termination region. The GR termination region can effectively adjust the end electric field of the JTE termination region. This JTE-GR termination junction combines the advantages of JTE termination and GR termination, so that the termination junction can withstand higher blocking voltage while reducing the sensitivity of the termination junction to concentration. While maintaining a high breakdown voltage, it can solve the problem of electric field peak to a certain extent and improve the stability of the termination junction.

[0052] In one specific embodiment, the JTE-GR terminal junction 6 includes a plurality of GR terminal regions 61 and a plurality of JTE terminal regions 62, wherein the plurality of GR terminal regions 61 are spaced apart; the plurality of JTE terminal regions 62 are distributed between two adjacent GR terminal regions 61 and are in contact with the GR terminal regions 61; the doping concentration of the GR terminal regions 61 is greater than the doping concentration of the JTE terminal regions 62, and the depth of the GR terminal regions 61 is greater than the depth of the JTE terminal regions 62.

[0053] Specifically, both the GR terminal regions 61 and the JTE terminal regions 62 are P-type doped regions, and the doping concentration of the GR terminal regions 61 is greater than that of the JTE terminal regions 62. That is, the GR terminal regions 61 are P+ implanted regions, and the JTE terminal regions 62 are P- implanted regions. Furthermore, the ion implantation depth of the GR terminal regions 61 is greater than that of the JTE terminal regions 62, forming terminal junctions with alternating high and low depths.

[0054] Compared to the traditional JTE termination junction structure, this embodiment combines the advantages of JTE and GR terminations, improving the stability of the termination junction. Traditional JTE termination junctions are prone to electric field peaks at both ends. However, in the JTE-GR termination junction structure of this embodiment, when the concentration of the first P-type region (i.e., the JTE termination junction) is low, the JTE front end is depleted. However, the GR portion in the JTE-GR termination, being highly doped, is not depleted. Therefore, the high concentration of the GR termination junction can effectively regulate the electric field distribution in the depletion region of the JTE termination junction, to some extent avoiding the possibility of breakdown at the JTE termination junction front end. Conversely, when the JTE concentration is high, electric field peaks are prone to appear at the ends of the JTE termination junction. However, the GR termination junction allows the depletion layer to extend outwards, optimizing the electric field distribution and sharing the voltage of the JTE portion.

[0055] In one specific embodiment, the drift region 3 is an N-type drift region, the guide layer 7 is a P-type guide layer, the base region 8 is a P-type base region, and the emission region 11 is an N-type emission region.

[0056] In one specific embodiment, an N-type ohmic contact is formed between the collector 5 and the collector region 4; a P-type ohmic contact is formed between the base 10 and the base region ohmic contact region 9; and an N-type ohmic contact is formed between the emitter 12 and the emitter region 11.

[0057] It is understood that an N-type ohmic contact metal is deposited between the collector 5 and the collector region 4, a P-type ohmic contact metal is deposited between the base 10 and the base region ohmic contact region 9, and an N-type ohmic contact metal is deposited between the emitter 12 and the emitter region 11.

[0058] In one specific embodiment, the high-voltage BJT device further includes a RESURF region 2 and a substrate 1, wherein the RESURF region 2 is located on the surface of the drift region 3 away from the collector region 4; and the substrate 1 is located on the surface of the RESURF region 2 away from the drift region 3.

[0059] Specifically, RESURF region 2 is a P-type epitaxial layer.

[0060] In this embodiment, a RESURF region is provided on the back side of the drift region, which reduces the surface electric field of the device and thereby improves the breakdown voltage of the device.

[0061] Example 2

[0062] Please see Figures 2a-2g , Figures 2a-2g This is a schematic flowchart illustrating a method for fabricating a high-voltage BJT device using SiC BCD technology, as provided in an embodiment of the present invention.

[0063] The fabrication method of the high-voltage BJT device using SiC BCD technology in this embodiment includes the following steps:

[0064] S1. Sequentially epitaxially grow RESURF region 2 and drift region 3 on substrate 1, as follows: Figure 2a As shown.

[0065] First, prepare a SiC single crystal substrate 1.

[0066] Then, the SiC single crystal substrate 1 undergoes fine processing, including cutting, grinding, and polishing, to obtain a flat and defect-free surface. Before growing the epitaxial layer, the substrate surface needs to be thoroughly cleaned to remove the oxide layer and impurities, ensuring good adhesion between the epitaxial layer and the substrate 1.

[0067] Next, RESURF region 2 is epitaxially grown using MOCVD, with P-type epitaxial doping occurring simultaneously. Then, drift region 3 is epitaxially grown on RESURF region 2, with N-type epitaxial doping occurring simultaneously. Both RESURF region 2 and drift region 3 are made of SiC. The doping concentration in SiC is controlled by precisely controlling the gas flow rate and reaction chamber conditions to precisely control the molar flow rate of the dopant entering the reaction chamber. RESURF region 2 is P-type doped, and titanium tetrachloride (TiCl4) can be used as the P-type dopant. Drift region 3 is an N-type doped region, and nitrogen (N2) can be used as the N-type dopant.

[0068] S2. A guiding layer 7 and a base region 8 are sequentially grown on the drift region 3, and an emission region 11 is grown on the base region 8, as follows: Figure 2b As shown.

[0069] Specifically, using MOCVD technology, a conductive layer 7 and a base region 8 are sequentially epitaxially grown on drift region 3, with P-type epitaxial doping occurring simultaneously. Then, an emitter region 11 is epitaxially grown on base region 8, with N-type epitaxial doping occurring simultaneously. The materials of the conductive layer 7, base region 8, and emitter region 11 all include SiC. By controlling the gas flow rate and reaction chamber conditions, the molar flow rate of the dopant entering the reaction chamber is precisely controlled, thereby controlling the doping concentration in SiC. The conductive layer 7 is a P-type conductive layer, and the base region 8 is a P-type base region, which can utilize titanium tetrachloride (TiCl4) as the P-type dopant. The emitter region 11 is an N-type emitter region, which can utilize nitrogen (N2) as the N-type dopant.

[0070] S3. Ion implantation is performed in the base region 8 to form a base region ohmic contact region 9 spaced apart from the emitter region 11, such as... Figure 2c As shown.

[0071] Specifically, a layer of metal or other material is deposited on the wafer surface as an ion implantation barrier layer. Then, the window pattern for ion implantation of the P-type base region 8 is obtained by photolithography using a mask. Next, the excess mask barrier material is etched away to form the ion implantation barrier window. Then, ion implantation is performed, using aluminum (Al) as the donor element for the P-type region to form a P-type base region ohmic contact region 9 with a high doping concentration, which facilitates the formation of ohmic contacts and reduces contact resistance.

[0072] S4. Ion implantation is performed in drift region 3 to form JTE-GR terminal junction 6 spaced apart from the guide layer 7. Specifically, this includes:

[0073] S41. Perform the first ion implantation in drift region 3 to form several GR terminal regions 61 spaced apart, such as... Figure 2d As shown.

[0074] Specifically, a metal or other material is deposited on the wafer surface as an ion implantation barrier layer. Then, the window pattern for ion implantation of the drift region 3 is obtained by photolithography using a mask. Next, the excess mask barrier material is etched away to form the first ion implantation barrier window. Then, ion implantation is performed, using aluminum (Al) as the donor element of the P-type region to form a heavily doped GR terminal region 61.

[0075] S42. A second ion implantation is performed between two adjacent GR terminal regions 61 to form several JTE terminal regions 62 in contact with the GR terminal regions 61. The doping concentration of the GR terminal regions 61 is greater than the doping concentration of the JTE terminal regions 62, and the depth of the GR terminal regions 61 is greater than the depth of the JTE terminal regions 62. Figure 2e As shown.

[0076] Specifically, a metal or other material is deposited on the wafer surface as an ion implantation barrier layer. Then, the window pattern for ion implantation of the drift region 3 is obtained by photolithography using a mask. Next, the excess mask barrier material is etched away to form a second ion implantation barrier window. Then, ion implantation is performed, using aluminum (Al) as the donor element for the P-type region to form a lightly doped and shallow JTE terminal region 62. The GR terminal region 61 and the JTE terminal region 62 form a JTE-GR terminal junction 6 with different implantation depths and alternating spacing.

[0077] S5. Ion implantation is performed in drift region 3 to form a collector region 4 spaced apart from the JTE-GR terminal junction 6, wherein the JTE-GR terminal junction 6 is located between the collector region 4 and the current-carrying layer 7, as shown below. Figure 2f As shown.

[0078] Specifically, a layer of metal or other material is deposited on the wafer surface as an ion implantation barrier layer. Then, the window pattern for ion implantation of collector region 4 is obtained by photolithography using a mask. Next, the excess mask barrier material is etched away to form the ion implantation barrier window. Then, ion implantation is performed, using phosphorus (P) as the donor element for the N-type region to form N-type collector region 4.

[0079] Furthermore, after ion implantation, the high-energy implanted ions create many tiny defects in the crystal, and the implanted atoms do not occupy appropriate lattice positions, resulting in high resistance in the implanted region. For SiC wafers undergoing ion implantation, high-temperature (typically above 1700°C) activation annealing in an inert gas atmosphere forms low-resistance P-type and N-type regions.

[0080] S6. Metal is fabricated on the emitter region 11, the ohmic contact region 9 of the base region, and the collector region 4 to form the emitter 12, the base 10, and the collector 5, as shown below. Figure 2g As shown.

[0081] First, contact metal is deposited on the base ohmic contact region 9 to form a P-type ohmic contact. Specifically, the front-side P-type ohmic contact window pattern is first transferred on the base ohmic contact region 9 using photolithography with a mask. Then, excess sacrificial oxide layer is etched away to form the P-type ohmic contact window. Next, contact metal is deposited on the wafer surface. Then, photoresist and excess metal are removed by a lift-off process. The wafer is then cleaned and dried, and metallization annealing is performed to form the P-type ohmic contact on the base ohmic contact region 9.

[0082] Then, contact metal is deposited on emitter region 11 and collector region 4 to form N-type ohmic contacts. Specifically, firstly, the front-side N-type ohmic contact window pattern is transferred on emitter region 11 and collector region 4 using photolithography with a mask. Then, excess sacrificial oxide layer and passivation layer are etched away to form N-type ohmic contact windows. Next, contact metal is deposited on the wafer surface. Then, photoresist and excess metal are removed by a lift-off process. Then, the wafer is cleaned and dried, and metallization annealing is performed to form N-type ohmic contacts on emitter region 11 and collector region 4.

[0083] Next, a layer of metal (e.g., Al) is deposited on the front side of the wafer. Then, the electrode patterns of the front emitter 12, base 10, and collector 5 are obtained by photolithography using a mask. The electrodes of the emitter 12, base 10, and collector 5 are then separated by etching to form the outermost metal electrode of the device.

[0084] Finally, the photoresist is removed and the device surface is cleaned to complete the device fabrication.

[0085] The high-voltage BJT device in this embodiment uses a JTE-GR termination junction, which can solve the problem of electric field peak to a certain extent while maintaining a high breakdown voltage, thus improving the stability of the termination junction.

[0086] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A high-voltage BJT device using SiC BCD technology, characterized in that, include: Drift zone; The collector region extends from the surface of the drift region into the interior of the drift region; The collector electrode is located on the collector region; A current-guiding layer is located on the drift region and spaced apart from the current-collecting region; A JTE-GR terminal junction extends from the surface of the drift region into the interior of the drift region and is located between the collector region and the current-conducting layer. The JTE-GR terminal junction includes several alternately distributed equipotential ring terminal regions and several junction terminal extension terminal regions. The equipotential ring terminal regions are spaced apart. The several junction terminal extension terminal regions are distributed between adjacent equipotential ring terminal regions and in contact with them, with the equipotential ring terminal regions located outside the junction terminal extension terminal regions, such that both ends of the JTE-GR terminal junction are equipotential ring terminal regions. The doping concentration of the equipotential ring terminal regions is greater than the doping concentration of the junction terminal extension terminal regions, and the depth of the equipotential ring terminal regions is greater than the depth of the junction terminal extension terminal regions. The base region is located on the flow guide layer; The base region ohmic contact area extends from the surface of the base region to the interior of the base region; The base is located on the ohmic contact region of the base region; The transmitting region is located on the base region and is spaced apart from the ohmic contact region of the base region; An emitter is located on the emitter region, and the base is located between the emitter and the collector.

2. The high-voltage BJT device using SiC BCD technology according to claim 1, characterized in that, The drift region is an N-type drift region, the guide layer is a P-type guide layer, the base region is a P-type base region, and the emission region is an N-type emission region.

3. The high-voltage BJT device using SiC BCD technology according to claim 1, characterized in that, An N-type ohmic contact is formed between the collector electrode and the collector region; A P-type ohmic contact is formed between the base and the ohmic contact region of the base region; An N-type ohmic contact is formed between the emitter and the emitter region.

4. The high-voltage BJT device using SiC BCD technology according to claim 1, characterized in that, It also includes the RESURF region and the substrate, wherein, The RESURF region is located on the surface of the drift region away from the collector region; The substrate is located on the surface of the RESURF region away from the drift region.

5. The high-voltage BJT device using SiC BCD technology according to claim 4, characterized in that, The RESURF region is a P-type epitaxial layer.

6. A method for fabricating a high-voltage BJT device using SiC BCD technology, characterized in that, Including the following steps: A guide layer and a base region are sequentially grown on the drift region, and an emission region is grown on the base region; Ion implantation is performed in the base region to form a base region ohmic contact region that is spaced apart from the emitter region; Ion implantation is performed in the drift region to form a JTE-GR terminal junction spaced apart from the current-carrying layer. The JTE-GR terminal junction includes several alternately distributed equipotential ring terminal regions and several junction terminal extension terminal regions. The equipotential ring terminal regions are spaced apart. The several junction terminal extension terminal regions are distributed between adjacent equipotential ring terminal regions and in contact with them, with the equipotential ring terminal regions located outside the junction terminal extension terminal regions, such that both ends of the JTE-GR terminal junction are equipotential ring terminal regions. The doping concentration of the equipotential ring terminal regions is greater than the doping concentration of the junction terminal extension terminal regions, and the depth of the equipotential ring terminal regions is greater than the depth of the junction terminal extension terminal regions. Ion implantation is performed in the drift region to form a collector region spaced apart from the JTE-GR terminal junction, wherein the JTE-GR terminal junction is located between the collector region and the current-carrying layer; Metals are fabricated on the emitter region, the ohmic contact region of the base region, and the collector region to form the emitter, base, and collector.

7. The method for fabricating a high-voltage BJT device using SiC BCD technology according to claim 6, characterized in that, Ion implantation is performed in the drift region to form a JTE-GR terminal junction spaced apart from the flux layer, including: The first ion implantation is performed in the drift region to form a plurality of spaced equipotential ring terminal regions; A second ion implantation is performed between two adjacent equipotential ring terminal regions to form several junction-terminated extended terminal regions that are in contact with the equipotential ring terminal regions.

8. The method for fabricating a high-voltage BJT device using SiC BCD technology according to claim 6, characterized in that, Before fabricating metal on the emitter region, the base ohmic contact region, and the collector region to form the emitter, base, and collector, the method further includes the following steps: A contact metal is deposited on the ohmic contact region of the base region to form a P-type ohmic contact; Contact metal is deposited on the emitter region and the collector region to form an N-type ohmic contact.

9. The method for fabricating a high-voltage BJT device using SiC BCD technology according to claim 6, characterized in that, Before sequentially growing the guide layer and base region on the drift region, the following steps are also included: The RESURF region and the drift region are epitaxially grown sequentially on the substrate.

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