Nanotube junctionless field effect transistor

Abstract

A nanotube junctionless field effect transistor comprises: a nanotube structure, the nanotube structure comprising an inner surface, an outer surface and a central plane, the central plane being located between the inner surface and the outer surface; in the extending direction of the nanotube structure, the nanotube structure comprises a channel region, Gaussian ring regions and source and drain doped regions, the Gaussian ring regions are located on the two sides of the channel region, and the source and drain doped regions are located on the sides, away from the channel region, of the Gaussian ring regions; the doping ion concentration in the Gaussian ring region is gradually increased from the inner surface to the central surface and from the outer surface to the central surface; and the gate structures are positioned on the inner surface and the outer surface of the channel region. The performance of the nanotube junction-free field effect transistor is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a nanotube junctionless field effect transistor. Background Art

[0002] As the size of planar metal-oxide-semiconductor field-effect transistors (MOSFETs) shrinks, the devices suffer from serious short channel effects (SCEs) and static power consumption caused by leakage current continues to increase. In order to overcome the short channel effect, various advanced 3D MOSFET architectures have been proposed, such as fin field effect transistors and ring-gate transistors. The nanotube junctionless field effect transistor (NT-JLFET) in the ring-gate transistor architecture has been proposed as the best device architecture for the final scaling of field effect transistors, due to its superior gate control capability. The inner gate and the outer gate jointly control the opening and closing of the nanotube junctionless field effect transistor. In addition, junctionless devices not only reduce thermal budgets and manufacturing complexity, but also suffer from less short channel effects.

[0003] However, the performance of nanotube junctionless field-effect transistors needs to be continuously improved. Summary of the invention

[0004] The technical problem solved by the present invention is to provide a nanotube junctionless field effect transistor, thereby improving the performance of the nanotube junctionless field effect transistor.

[0005] An embodiment of the present invention provides a nanotube junctionless field effect transistor, comprising: a nanotube structure, the nanotube structure comprising an inner surface, an outer surface and a center plane, the center plane being located between the inner surface and the outer surface; along the extension direction of the nanotube structure, the nanotube structure comprising a channel region, a Gaussian ring region and a source-drain doped region, the Gaussian ring region being located on both sides of the channel region, and the source-drain doped region being located on a side of each Gaussian ring region away from the channel region; the doping ion concentration in the Gaussian ring region gradually increases along the inner surface to the center plane, and along the outer surface to the center plane; and a gate structure being located on the inner surface and the outer surface of the channel region.

[0006] Optionally, the Gaussian ring region includes a central region and gradient regions located on both sides of the central region, the central region includes the central plane; along the direction from the inner surface to the central region, and along the direction from the outer surface to the central region, the doping ion concentration in the gradient region gradually increases.

[0007] Optionally, the doping ion concentration in the central region is the same as the doping ion concentration in the source and drain doping regions.

[0008] Optionally, along the extension direction of the nanotube structure, the channel region has a first length, and the gate structure has a second length, and the second length is greater than the first length.

[0009] Optionally, the difference between the second length and the first length ranges from 1 nanometer to 3 nanometers.

[0010] Optionally, it further includes: an electric contact layer located on one side of the outer surface of the nanotube structure, and along the extension direction of the nanotube structure, the electric contact layer is located on both sides of the gate structure.

[0011] Optionally, the electrical contact layer is in electrical contact with a portion of the source and drain doped regions.

[0012] Optionally, the gate structure includes: a gate dielectric layer located on the inner surface and the outer surface of the channel region; and a gate layer located on the gate dielectric layer.

[0013] Optionally, it further includes: a dielectric structure, wherein the dielectric structure is located on the inner surface and the outer surface of the nanotube structure, and along the extension direction of the nanotube structure, the dielectric structure is located on both sides of the gate structure.

[0014] Optionally, it further includes: a gate extension layer located in the dielectric structure on one side of the inner surface, the gate extension layer being electrically connected to the gate structure.

[0015] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0016] In the nanotube junctionless field effect transistor of the technical solution of the present invention, by setting Gaussian ring regions, the Gaussian ring regions are located on both sides of the channel region, the source and drain doping regions are located on the side of each Gaussian ring region away from the channel region, and the doping ion concentration in the Gaussian ring region gradually increases along the inner surface to the central surface, and along the outer surface to the central surface. Thus, the turn-off current can be reduced, the threshold voltage can be increased, the threshold voltage roll-off effect can be overcome, and the effective gate control capability can be improved without affecting the on-current.

[0017] Furthermore, the channel region has a first length, and the gate structure has a second length, which is greater than the first length. The gate structure and the Gaussian ring region have an overlapping length range, which can increase the barrier height from the source doping region to the channel region and the barrier height from the drain doping region to the channel region while keeping the threshold voltage from being too large and avoiding hindering the opening of the device, thereby increasing the effective channel length. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 and Figure 2 is a schematic diagram of the structure of a nanotube junctionless field effect transistor in one embodiment;

[0019] Figure 3 is a schematic diagram of the principle of generating off current in a nanotube junctionless field effect transistor in an off state in one embodiment;

[0020] Figures 4 to 8 Schematic diagram of the structure of a nanotube junctionless field effect transistor in an embodiment of the present invention. DETAILED DESCRIPTION

[0021] As described in the background art, the performance of nanotube junctionless field effect transistors needs to be continuously improved, which will be described in detail below with reference to the accompanying drawings.

[0022] Figure 1 and Figure 2 Schematic diagram of the structure of a nanotube junctionless field effect transistor in one embodiment.

[0023] Please refer to Figure 1 and Figure 2 , Figure 1 A three-dimensional diagram of a nanotube junctionless field effect transistor. Figure 2 for Figure 1 Schematic diagram of the cross-sectional structure of the nanotube junctionless field effect transistor along the section line AA1 direction, the nanotube junctionless field effect transistor comprises: a nanotube structure 100, the nanotube structure 100 comprises an inner surface P1 and an outer surface P2, along the extension direction of the nanotube structure 100, the nanotube structure 100 comprises a channel region 101 and a source doping region 104 and a drain doping region 102 located on both sides of the channel region 101; a gate structure 103 located on the inner surface P1 and the outer surface P2 of the channel region 101; a gate structure 103 located on the outer surface P2 of the nanotube structure 100; 2, the first electrical contact layer 110 and the second electrical contact layer 105, the first electrical contact layer 110 is in electrical contact with part of the source doped region 104, and the second electrical contact layer 105 is in electrical contact with part of the drain doped region 102; a dielectric structure 106, the dielectric structure 106 is located on the inner surface P1 and the outer surface P2 of the nanotube structure 100, and the gate structure 103 is located in the dielectric structure 106; a gate extension layer 108 is located in the dielectric structure 106, and the gate extension layer 108 is electrically connected to the gate structure 103.

[0024] The gate structure 103 includes: a gate dielectric layer located on the inner surface P1 and the outer surface P2 of the channel region 101; and a gate layer 121 located on the gate dielectric layer 120. The material of the gate dielectric layer 120 includes silicon dioxide, the material of the gate layer 121 includes titanium nitride, and the material of the electrical contact layer 105 includes metal tungsten.

[0025] In the nanotube junctionless field effect transistor, the doping type of the channel region 101, the source doping region 104 and the drain doping region 102 are all N-type, and the doping concentration is 1×10 19 cm -3 . Continue to refer to Figure 2 , the work function of the gate structure 103 is set to 5.1eV. The gate structure 103 has a higher work function, which causes the gate dielectric layer to repel electrons and gather holes, forming a hole inversion layer. The hole inversion layer presents a triangle with the length of the gate structure 103 as the base. The inversion layers formed by the gate structure 103 on the inner surface P1 and the outer surface P2 of the channel region 101 overlap, turning off the nanotube junctionless field effect transistor. When a positive voltage is applied to the gate structure 103, the thickness of the hole inversion layer formed by the gate structure 103 on the inner surface P1 and the outer surface P2 decreases, forming an electron path in the channel region 101, turning on the nanotube junctionless field effect transistor. Therefore, the transmission path of the on-current is in the center of the channel region 101 (3nm to 5nm below the gate dielectric layer).

[0026] Please refer to Figure 3 , Figure 3 yes Figure 1 and Figure 2 The off-state current I of the nanotube junctionless field effect transistor in the off state off Schematic diagram of the generated principle, the shutdown current I off The principles of generation include: Figure 2 From the BB1 ​​line in the figure (BB1 is located 1nm below the gate dielectric layer), in the off state of the nanotube junctionless field effect transistor (drain-source voltage V DS =1.0V, gate-source V GS =0.0V), holes gather below the channel region 101. According to the quantum mechanical effect, the point with the highest hole concentration in the channel region 101 is located 1nm below the gate dielectric layer, with a concentration close to 10 19 cm -3 , and the electron concentration in the drain doping region 102 is 10 19 cm -3 This results in a very small depletion region width of the PN junction at the channel-drain interface, which causes the conduction band in the drain doped region 102 to be quite close to the valence band in the channel region 101. Figure 3As shown. The proximity of the energy bands causes the electrons in the channel region 101 to tunnel to the drain through longitudinal band-to-band tunneling (L-BTBT), resulting in an increase in the off current I OFF The farther away from the gate dielectric layer, the lower the hole concentration, the wider the depletion region width of the PN junction, and the smaller the off current caused by longitudinal band-to-band tunneling. Therefore, the leakage path of the off current is mainly located 1nm below the gate dielectric layer.

[0027] In order to solve the above problems, the common practice is: (1) by adjusting the gate layer 121 and the gate dielectric layer 120 to adjust the energy band of the nanotube junctionless field effect transistor in the off state, thereby increasing the tunneling width, suppressing the longitudinal band-to-band tunneling, and reducing the off current. The material of the gate layer 121 is a material with a small work function, and the material of the gate dielectric layer 120 is a material with a low dielectric constant to reduce the electric field at the channel-drain interface and alleviate the band bending. However, when the channel length is 10nm, the off current of the nanotube junctionless field effect transistor is only reduced by one order of magnitude, but the threshold voltage is sharply reduced.

[0028] (2) Using the valence band discontinuity of the heterojunction to increase the tunneling width of the nanotube junctionless field effect transistor, for example, by using Si 1-x Ge x (x is the molar component) material, the channel region uses Si material, and a heterojunction is formed at the source / drain-channel interface. However, when the channel length of the nanotube junctionless field effect transistor is gradually reduced from 20nm, the presence of the heterojunction will cause the threshold voltage to decrease sharply, making the nanotube junctionless field effect transistor ineffective.

[0029] (3) Using intrinsic pockets to increase the tunneling width of the nanotube junctionless field effect transistor and reduce the off-state current, the intrinsic pocket is a region of length L inserted into the source / drain region near the channel of the nanotube junctionless field effect transistor, and its doping concentration is 10 15 cm -3 The intrinsic pocket has a low doping concentration and high resistance, but this will cause a significant drop in the on-current.

[0030] In order to solve the above problems, the technical solution of the present invention provides a nanotube junctionless field effect transistor, by setting Gaussian ring regions, the Gaussian ring regions are located on both sides of the channel region, the source and drain doping regions are located on the side of each Gaussian ring region away from the channel region, and the doping ion concentration in the Gaussian ring region gradually increases along the inner surface to the central surface, and along the outer surface to the central surface. Thus, the turn-off current can be reduced, the threshold voltage can be increased, the threshold voltage roll-off effect can be overcome, and the effective gate control capability is improved without affecting the on-current, and the effective gate length is increased.

[0031] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0032] Figures 4 to 8 Schematic diagram of the structure of a nanotube junctionless field effect transistor in an embodiment of the present invention.

[0033] Please refer to Figure 4 and Figure 8 , Figure 4 A three-dimensional diagram of a nanotube junctionless field effect transistor. Figure 5 for Figure 4 Schematic diagram of the cross-sectional structure of the nanotube junctionless field effect transistor along the section line AA1. Figure 6 is a top view of the first side S1 of the nanotube junctionless field effect transistor, Figure 7 is a top view of the first side S2 of the nanotube junctionless field effect transistor, Figure 8 for Figure 5 A magnified schematic diagram of the middle Gaussian ring region. The nanotube junctionless field effect transistor may include:

[0034] A nanotube structure 200, the nanotube structure 200 may include an inner surface P1, an outer surface P2 and a center plane (not shown), the center plane being located between the inner surface and the outer surface; along the extension direction of the nanotube structure 200, the nanotube structure 200 may include a channel region 201, a Gaussian ring region 202 and a source-drain doped region, the Gaussian ring region 202 being located on both sides of the channel region 201, and the source-drain doped region being located on a side of each Gaussian ring region 202 away from the channel region 201; along the direction from the inner surface P1 to the center plane, and along the direction from the outer surface P2 to the center plane, the doping ion concentration in the Gaussian ring region 202 gradually increases.

[0035] The gate structure 204 is located on the inner surface P1 and the outer surface P2 of the channel region 201 .

[0036] The cross-sectional shape of the nanotube structure 200 may include a circular ring or an elliptical ring.

[0037] In this embodiment, the cross-sectional shape of the nanotube structure 200 may include a circular ring.

[0038] In this embodiment, the source-drain doping region may include a source doping region 213 and a drain doping region 203. The channel region 201, the source doping region 213 and the drain doping region 203 may have the same conductivity type and the same doping ion concentration.

[0039] In the above embodiment, the doping ion concentrations of the channel region 201 , the source doping region 213 and the drain doping region 203 are the same, which can reduce the short channel effect of the nanotube junctionless field effect transistor.

[0040] In this embodiment, the conductivity type of the doped ions in the channel region 201 , the source doped region 213 , and the drain doped region 203 is N-type, and the N-type ions may include phosphorus ions, arsenic ions, antimony ions, and the like.

[0041] In this embodiment, the doping ion concentration in the channel region 201, the source doping region 213 and the drain doping region 203 may be 1×10 19 cm -3 .

[0042] In one embodiment, when the cross-sectional shape of the nanotube structure 200 is a circular ring, the center plane is distributed concentrically with the inner surface and the outer surface, and the distances between the center plane and the inner surface and the outer surface are equal.

[0043] In another embodiment, when the cross-sectional shape of the nanotube structure 200 is an elliptical ring, the cross-sectional shape of the center plane may also be an elliptical ring, and the distances between the center plane and the inner surface and the outer surface are equal.

[0044] Please refer to Figure 8 In this embodiment, the Gaussian ring region 202 may include a central region C1 and a gradient region C2 located on both sides of the central region C1, and the central region C1 may include the central plane; along the direction from the inner surface P1 to the central region C1, and along the direction from the outer surface P2 to the central region C1, the doping ion concentration in the gradient region C2 gradually increases.

[0045] In a specific embodiment, the doping ion concentration in the gradient region C2 presents a Gaussian distribution, and the Gaussian distribution means that the doping ion concentration in the gradient region C2 gradually increases along the direction from the inner surface P1 to the central region C1 and along the direction from the outer surface P2 to the central region C1.

[0046] In this embodiment, the doping ion concentration of the surface P2 / P1 of the gradient region C2 farthest from the central region C1 is 10 15 cm -3 The doping ion concentration of the gradient region C2 close to the innermost part of the central region C1 is 10 19 cm -3 .

[0047] In this embodiment, the doping ion concentration in the central region C1 is the same as the doping ion concentration in the source-drain doping region. The central region C1 of the Gaussian ring region 202 is a current path for conducting current, and the doping ion concentration in the central region C1 is the same as the doping ion concentration in the source-drain doping region, so that the on-resistance of the on-current transmission path remains unchanged and does not affect the on-current.

[0048] In this embodiment, along the extension direction of the nanotube structure 200 , the channel region 201 has a first length L1 , and the gate structure 204 has a second length L2 , and the second length L2 is greater than the first length L1 .

[0049] In this embodiment, the first length L1 ranges from 10 nanometers to 20 nanometers.

[0050] In this embodiment, the gate structure 204 may include: a gate dielectric layer 220 located on the inner surface P1 and the outer surface P2 of the channel region 201 ; and a gate layer 221 located on the gate dielectric layer 220 .

[0051] In this embodiment, the material of the gate dielectric layer 220 may include silicon dioxide, and the material of the gate layer 221 may include titanium nitride.

[0052] In this embodiment, along the extension direction of the nanotube structure, the gate structure 204 can also extend to contact the inner surface P1 and the outer surface P2 corresponding to the Gaussian ring region 202. That is, the gate structure 204 has an overlapping area with the Gaussian ring region 202, thereby increasing the barrier height from the source doping region 213 to the channel region 201 and the barrier height from the drain doping region 203 to the channel region 201, thereby increasing the effective channel length.

[0053] In one embodiment, the gate structure may contact the inner surface P1 and the outer surface P2 corresponding to the Gaussian ring region 202 on either side of the channel region, or may contact the inner surface P1 and the outer surface P2 corresponding to the Gaussian ring region 202 on both sides of the channel region at the same time. That is, the gate structure 204 has an overlapping area with the Gaussian ring region 202 on either side or both sides of the channel region.

[0054] In one embodiment, when the gate structure contacts the inner surface P1 and the outer surface P2 corresponding to the Gaussian ring region 202 on both sides of the channel region at the same time, the contact lengths on both sides may be equal or unequal. Figure 5 The length L3 of the contact between the gate structure and the Gaussian ring regions on both sides of the channel region may be equal or unequal.

[0055] In another embodiment, the length L3 of the gate structure 204 located on the inner surface P1 and the outer surface P2 of the Gaussian ring region 202 ranges from 1 nanometer to 3 nanometers, that is, the gate structure 204 has an overlapping length L3 on each surface of the Gaussian ring region 202 .

[0056] In this embodiment, the length L3 of the gate structure 204 at the inner surface P1 and the outer surface P2 of the Gaussian ring region 202 is in the range of 2 nanometers.

[0057] In the above embodiment, the gate structure 204 and the Gaussian ring region 202 have an overlapping length range of L3, which can increase the barrier height from the source doping region 213 to the channel region 201 and the barrier height from the drain doping region 203 to the channel region 201 while maintaining the threshold voltage not being too large and avoiding hindering the opening of the device, thereby increasing the effective channel length.

[0058] In this embodiment, the nanotube junctionless field effect transistor may further include: an electrical contact layer (not shown) located on one side of the outer surface P2 of the nanotube structure 200 , and the electrical contact layer is located on both sides of the gate structure 204 along the extension direction of the nanotube structure 200 .

[0059] In this embodiment, the electrical contact layer may be in electrical contact with a portion of the source / drain doped regions.

[0060] In this embodiment, the electrical contact layer may include a first electrical contact layer 215 and a second electrical contact layer 205 . The first electrical contact layer 215 is in electrical contact with the source doping region 213 , and the second electrical contact layer 205 is in electrical contact with the drain doping region 203 .

[0061] In this embodiment, the material of the electrical contact layer may include metal, and the metal may include tungsten.

[0062] In this embodiment, the nanotube junctionless field effect transistor may further include: a dielectric structure 206, wherein the dielectric structure 206 is located on the inner surface P1 and the outer surface P2 of the nanotube structure 200, and along the extension direction of the nanotube structure 200, the dielectric structure 206 is located on both sides of the inner surface P1 and the outer surface P2 of the gate structure 204.

[0063] In this embodiment, the dielectric structure 206 is located on the inner surface P1 and the outer surface P2 of the nanotube structure 200 , that is, the dielectric structure 206 fills the interior of the nanotube structure 200 and covers the outer surface P2 of the nanotube structure 200 .

[0064] In this embodiment, the material of the dielectric structure 206 may include silicon dioxide.

[0065] In this embodiment, the nanotube junctionless field effect transistor may further include: a gate extension layer 207 located in the dielectric structure 206 on one side of the inner surface P1 , and the gate extension layer 207 is electrically connected to the gate structure 204 .

[0066] In this embodiment, the gate extension layer 207 is located in the dielectric structure 206 on the inner surface P1 side of the nanotube structure 200 , and the gate extension layer 207 is located at one end of the drain doping region 203 .

[0067] In one embodiment, the material of the gate extension layer 207 may include metal or metal nitride; the metal may include: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride may include a combination of one or more of tantalum nitride and titanium nitride.

[0068] In this embodiment, in the nanotube junctionless field effect transistor, a Gaussian ring region 202 is provided between the source doping region 213 and the channel region 201, and between the drain doping region 203 and the channel region 201. The doping ion concentration in the Gaussian ring region 202 gradually increases along the direction from the inner surface P1 to the central region C1, and along the direction from the outer surface P2 to the central region C1. Thus, the off current I OFF , increasing the threshold voltage, overcoming the threshold voltage roll-off effect, improving the effective gate control capability without affecting the on-current, and increasing the effective gate length.

[0069] Specifically, please combine Figure 5 Analysis of the nanotube junctionless field effect transistor along the trend line BB1.

[0070] First, when the nanotube junctionless field effect transistor is in the off state, holes will gather under the gate dielectric layer, and the holes and electrons will form a PN junction. The introduction of the Gaussian ring increases the depletion layer width of the PN junction at the interface between the source doping region 213 and the channel region 201, and the drain doping region 203 and the channel region 201, so that the electric field at the interface is reduced. The reduction of the electric field alleviates the bending of the energy band, increases the tunneling width of the lateral band to band tunneling (L-BTBT), reduces the off current IOFF, and reduces the static power consumption.

[0071] Secondly, at the interface between the source doping region 213 and the channel region 201, and the drain doping region 203 and the channel region 201, the Gaussian ring region 202 and the gate structure have an overlapping length L3. Within the length L3, since the ion doping concentration of the inner surface P1 and the outer surface P2 of the Gaussian ring region 202 far away from the central region C1 is low, the barrier height from the source doping region 213 to the channel region 201, and the drain doping region 203 to the channel region 201 is increased. The increased barrier height can effectively overcome the threshold voltage roll-off effect, and also reduce the turn-off current IOFF .

[0072] Again, the resistance in the Gaussian ring region 202 is high (the electron doping concentration is about 10 15 cm -3 ) is located on the surface of the silicon channel, and the doping ion concentration gradually increases from the inner surface P1 and the outer surface P2 to the central area C1, that is, the resistance decreases from the inner surface P1 and the outer surface P2 to the central area C1. The transmission path of the on-current is located in the central area C1, so the gradual change area C2 of the Gaussian ring area 202 has almost no effect on the on-current.

[0073] Again, the Gaussian ring region 202 prevents the electrons in the channel region 201 from tunneling to the drain doping region 203 through lateral band-to-band tunneling (L-BTBT), thereby increasing the electron concentration in the channel region 201. The increased electron concentration reduces the hole concentration. The reduced hole concentration weakens the shielding effect of the holes in the channel region 201 on the control capability of the gate structure 204, thereby improving the effective gate control capability. The subthreshold swing and the drain-induced barrier lowering (DIBL) effect are reduced.

[0074] Finally, the overlapping length L3 of the Gaussian ring region 202 and the gate structure 204 further increases the barrier height. The length of the PN junction depletion region at the interface between the source doping region 213 and the channel region 201 and the drain doping region 203 and the channel region 201 increases, which alleviates the degree of band bending. The increase in barrier height and the reduction in band bending increase the effective gate length. When the length of the channel region 201 is shorter, the Gaussian ring region 202 reduces the turn-off current I OFF , the effect of reducing the short channel effect is more significant.

[0075] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A nanotube junctionless field effect transistor, characterized in that: include: A nanotube structure, the nanotube structure comprising an inner surface, an outer surface and a center surface, the center surface being located between the inner surface and the outer surface; Along the extension direction of the nanotube structure, the nanotube structure includes a channel region, a Gaussian ring region and a source-drain doping region, the Gaussian ring region is located at both sides of the channel region, and the source-drain doping region is located at a side of each Gaussian ring region away from the channel region; along the inner surface to the central surface, and along the outer surface to the central surface, the doping ion concentration in the Gaussian ring region gradually increases; A gate structure is located on the inner surface and the outer surface of the channel region.

2. The nanotube junctionless field effect transistor according to claim 1, characterized in that: The Gaussian ring region includes a central region and gradient regions located on both sides of the central region, and the central region includes the central plane; The doping ion concentration in the gradient region gradually increases along the direction from the inner surface to the central region and along the direction from the outer surface to the central region.

3. The nanotube junctionless field effect transistor according to claim 2, characterized in that: The doping ion concentration in the central region is the same as the doping ion concentration in the source and drain doping regions.

4. The nanotube junctionless field effect transistor according to claim 1, wherein: Along the extension direction of the nanotube structure, the channel region has a first length, and the gate structure has a second length, and the second length is greater than the first length.

5. The nanotube junctionless field effect transistor according to claim 4, characterized in that: The difference between the second length and the first length ranges from 1 nanometer to 3 nanometers.

6. The nanotube junctionless field effect transistor according to claim 1, wherein: Also includes: The electrical contact layer is located on one side of the outer surface of the nanotube structure. Along the extension direction of the nanotube structure, the electrical contact layer is located on both sides of the gate structure.

7. The nanotube junctionless field effect transistor according to claim 6, characterized in that: The electrical contact layer is in electrical contact with a portion of the source / drain doped regions.

8. The nanotube junctionless field effect transistor according to claim 1, wherein: The gate structure comprises: a gate dielectric layer located on the inner surface and the outer surface of the channel region; and a gate layer located on the gate dielectric layer.

9. The nanotube junctionless field effect transistor according to claim 1, wherein: Also includes: A dielectric structure is located on the inner surface and the outer surface of the nanotube structure, and along the extension direction of the nanotube structure, the dielectric structure is located on both sides of the gate structure.

10. The nanotube junctionless field effect transistor according to claim 9, characterized in that: Also includes: A gate extension layer is located in the dielectric structure on one side of the inner surface, and the gate extension layer is electrically connected to the gate structure.

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