Semiconductor structure and forming method thereof

Abstract

Semiconductor structures and methods of forming the same are provided. The semiconductor structure includes a plurality of first nanostructures over the substrate and a plurality of second nanostructures adjacent to the first nanostructures. The semiconductor structure includes a protective layer over the first nanostructure and a first gate structure formed on the first nanostructure. The semiconductor structure includes a second gate structure formed on the second nanostructure. The semiconductor structure includes a first dielectric wall between the first gate structure and the second gate structure, and a top surface of the first dielectric wall is higher than a top surface of the protective layer.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. Background Art

[0002] The electronics industry is experiencing a growing demand for smaller and faster electronic devices that can implement a greater number of increasingly complex and sophisticated functions. Therefore, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance and low-power integrated circuits (ICs). To date, these goals have been achieved to a large extent by reducing the size of semiconductor ICs (e.g., minimum component size) and thereby improving production efficiency and reducing associated costs. However, such miniaturization introduces greater complexity into the semiconductor manufacturing process. Therefore, achieving continued progress in semiconductor ICs and devices requires similar progress in semiconductor manufacturing processes and technologies.

[0003] Recently, multi-gate devices have been introduced in an attempt to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short channel effects (SCEs). However, the fabrication and integration of multi-gate devices can be challenging. Summary of the invention

[0004] Some embodiments of the present application provide a semiconductor structure, including: a plurality of first nanostructures located above a substrate; a plurality of second nanostructures adjacent to the first nanostructures; a protective layer located above the first nanostructures; a first gate structure formed on the first nanostructures; a second gate structure formed on the second nanostructures; and a first dielectric wall located between the first gate structure and the second gate structure, wherein a top surface of the first dielectric wall is higher than a top surface of the protective layer.

[0005] Other embodiments of the present application provide a semiconductor structure, including: a plurality of first nanostructures located above a substrate; a plurality of second nanostructures adjacent to the first nanostructures; a first protective layer located above the first nanostructures; a first gate structure formed on the first nanostructures and the second nanostructures; and a first dielectric wall located between the first nanostructures and the second nanostructures, wherein a top surface of the first gate structure is higher than a top surface of the first dielectric wall.

[0006] Some other embodiments of the present application provide a method for forming a semiconductor structure, comprising: forming a first fin structure and a second fin structure respectively above a substrate, wherein the first fin structure includes a first semiconductor material layer and a second semiconductor material layer alternately stacked, and the second fin structure includes a first semiconductor material layer and a second semiconductor material layer alternately stacked; forming a first protective layer on the first fin structure, and forming a second protective layer on the second fin structure; forming a dummy gate structure across the first fin structure and the second fin structure; forming a first spacer layer and a second spacer layer on the sidewall surface of the dummy gate structure; removing a portion of the dummy gate structure to expose the first spacer layer; removing a portion of the first spacer layer to expose a portion of the second spacer layer; removing a portion of the first semiconductor material layer to form a first nanostructure and a second nanostructure; forming a gate dielectric layer on the first nanostructure and the second nanostructure, wherein the gate dielectric layer is located on the first spacer layer and the second spacer layer; forming a gate electrode layer on the gate dielectric layer; removing a portion of the gate electrode layer; removing a portion of the gate dielectric layer to expose the second spacer layer; and forming a dielectric wall between the first nanostructure and the second nanostructure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figures 1A to 1Z A perspective view illustrating an intermediate stage in forming a semiconductor structure in accordance with some embodiments.

[0009] Figure 1ZA to Figure 1ZB A perspective view illustrating an intermediate stage in forming a semiconductor structure in accordance with some embodiments.

[0010] Figure 1B-T shows a schematic top view of an intermediate dielectric stage of a semiconductor structure according to some embodiments, and Figure 1B-T The box A1 shown in corresponds to Figure 1B The structure shown in .

[0011] Figure 1F-T shows a schematic top view of an intermediate dielectric stage of a semiconductor structure according to some embodiments, and Figure 1F-T The box A1 shown in corresponds to Figure 1F The structure shown in .

[0012] Figure 1M-Tshows a schematic top view of an intermediate dielectric stage of a semiconductor structure according to some embodiments, and Figure 1M-T The box B1 shown in Figure 1M The structure shown in .

[0013] Figure 2 According to some embodiments, Figure 1ZB The cross-sectional view of the semiconductor structure shown by line BB' in FIG.

[0014] Figure 3 According to some embodiments, Figure 1ZB The cross-sectional representation of the semiconductor structure shown by line CC' in FIG.

[0015] FIG. 4A to FIG. 4B A cross-sectional representation of a semiconductor structure is shown in accordance with some embodiments.

[0016] FIG. 5A to FIG. 5B A cross-sectional representation of a semiconductor structure is shown in accordance with some embodiments.

[0017] FIG. 6A to FIG. 6B A cross-sectional representation of a semiconductor structure is shown in accordance with some embodiments.

[0018] Figure 7 A cross-sectional representation of a semiconductor structure is shown in accordance with some embodiments.

[0019] Figure 8 A cross-sectional representation of a semiconductor structure is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0021] Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, the same reference numerals are used to represent the same elements. It should be understood that additional operations may be provided before, during, and after the method, and that some of the described operations may be replaced or eliminated for other embodiments of the method.

[0022] The all-around gate (GAA) transistor structure described below can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, smaller spacing than that obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed above a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0023] The fins described below can be patterned by any suitable method. For example, the fins can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, a pitch that is smaller than that obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins.

[0024] Embodiments of semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a first nanostructure and a second nanostructure formed above a substrate. A protective layer is formed on the first nanostructure and the second nanostructure to protect the first nanostructure and the second nanostructure. A gate structure is formed on the nanostructure, and a first spacer layer and a second spacer layer are formed on opposite sidewall surfaces of the gate structure. A dielectric wall is located between the first nanostructure and the second nanostructure. Because a portion of the gate electrode layer of the gate structure is replaced with the dielectric wall, the area of ​​the gate electrode layer is reduced. Undesirable capacitance between the gate structure and the S / D contact structure of the semiconductor structure is reduced. In addition, due to the protection of the protective layer, each of the nanostructures has substantially the same thickness. When the uniformity of the thickness of each of the nanostructures is improved, the performance of the semiconductor structure is improved. A source / drain (S / D) structure or S / D region may refer to a source or a drain, individually or collectively depending on the context.

[0025] Figures 1A to 1ZB A perspective view is shown of an intermediate stage in forming a semiconductor structure 100 a , in accordance with some embodiments.

[0026] like Figure 1AAs shown in , a first semiconductor material layer 106 and a second semiconductor material layer 108 are formed over a substrate 102 along a first direction (e.g., an x-axis). Next, a protective layer 110 and a hard mask layer 112 are formed on the stack of the first semiconductor material layer 106 and the second semiconductor material layer 108. The second semiconductor material layer 108 includes a top second semiconductor material layer 108T. The thickness of the top second semiconductor material layer 108T is less than the thickness of the other second semiconductor material layers 108. Figure 1R In the step of removing the second semiconductor material layer 108T from the top, the second semiconductor material layer 108T will be removed together with the first semiconductor material layer 106 because the thickness of the second semiconductor material layer 108T from the top is very small.

[0027] The substrate 102 may be a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, the substrate 102 may include an elemental semiconductor material, a compound semiconductor material, and / or an alloy semiconductor material. The elemental semiconductor material may include, but is not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. The compound semiconductor material may include, but is not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. The alloy semiconductor material may include, but is not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0028] In some embodiments, the first semiconductor material layer 106 and the second semiconductor material layer 108 are alternately stacked above the substrate 102. In some embodiments, the first semiconductor material layer 106 and the second semiconductor material layer 108 are made of different semiconductor materials. In some embodiments, the first semiconductor layer 106 is made of silicon germanium (SiGe), and the second semiconductor layer 108 is made of silicon (Si).

[0029] In some embodiments, the first semiconductor layer 106 and the second semiconductor layer 108 independently include silicon (Si), germanium (Ge), silicon germanium (SiGe), indium arsenide (InAs), indium gallium arsenide (InGaAs), indium antimonide (InSb), or another suitable material.

[0030] The first semiconductor layer 106 and the second semiconductor layer 108 are made of different materials having different lattice constants. In some embodiments, the first semiconductor layer 106 is made of silicon (Si), and the second semiconductor layer 108 is made of silicon germanium (SiGe).

[0031] In some embodiments, each of the first semiconductor layers 106 has a thickness in a range from about 3 nm to about 8 nm. In some embodiments, each of the second semiconductor layers 108 has a thickness in a range from about 3 nm to about 8 nm. In some embodiments, the topmost second semiconductor material layer 108T has a thickness in a range from about 1 nm to about 2 nm.

[0032] It should be noted that although four first semiconductor material layers 106 and four second semiconductor material layers 108 are formed, the semiconductor structure may include more or less first semiconductor material layers 106 and second semiconductor material layers 108. For example, the semiconductor structure may include two to five of the first semiconductor material layers 106 and second semiconductor material layers.

[0033] The first semiconductor material layer 106 and the second semiconductor material layer 108 can be formed by using low pressure chemical vapor deposition (LPCVD), an epitaxial growth process, another suitable method, or a combination thereof. In some embodiments, the epitaxial growth process includes molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE).

[0034] The protective layer 110 has a high etching selectivity relative to the first semiconductor material layer 106. When the first semiconductor material layer 106 is removed, Figure 1R The protective layer 110 will not be removed in the step of. In some embodiments, the protective layer 110 is made of silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN) and another applicable material. The protective layer 110 can be formed by thermal oxidation or chemical vapor deposition (CVD), such as low temperature chemical vapor deposition (LPCVD) or plasma enhanced CVD (PECVD). In some embodiments, the protective layer 110 has a thickness in the range from about 2 nm to about 20 nm. In some embodiments, the thickness of the protective layer 110 is greater than the thickness of the first semiconductor material layer 106 and the thickness of the second semiconductor material layer 108.

[0035] In some embodiments, the hard mask layer 112 is made of silicon nitride (SiN) and is formed by chemical vapor deposition (CVD), such as low temperature chemical vapor deposition (LPCVD) or plasma enhanced CVD (PECVD).

[0036] Afterwards, if Figure 1BAs shown in , according to some embodiments, the hard mask layer 112 is patterned to form a patterned hard mask layer 112, and then the protection layer 110 is patterned by using the patterned hard mask layer 112 as a mask. According to some embodiments, after patterning the protection layer 110, the semiconductor material stack is patterned to form the fin structure 104a / 104b / 104c. In some embodiments, the fin structure 104a / 104b / 104c includes a base fin structure 105 and a semiconductor material stack of a first semiconductor material layer 106 and a second semiconductor material layer 108.

[0037] Figure 1B-T shows a schematic top view of an intermediate dielectric stage of a semiconductor structure 100a according to some embodiments, and Figure 1B-T The box A1 shown in corresponds to Figure 1B The structure shown in .

[0038] The hard mask layer 112 and the protective layer 110 are patterned by a patterning process. The patterning process includes a photolithography process and an etching process. The photolithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing photoresist, rinsing and drying (e.g., hard baking). The etching process includes a dry etching process or a wet etching process.

[0039] Afterwards, if Figure 1C As shown in FIG. 1 , according to some embodiments, after forming the fin structures 104a / 104b / 104c, an isolation material 115 is formed on the hard mask layer 112 and the protection layer 110. Next, a planarization process is performed on the isolation material 115 until the hard mask layer 112 is exposed. Therefore, the top surface of the isolation material 115 is substantially coplanar with the top surface of the hard mask layer 112. In some embodiments, the planarization process includes a CMP process.

[0040] In some embodiments, the isolation material 115 is made of silicon oxide, silicon nitride, silicon oxynitride (SiON), another suitable insulating material, or a combination thereof. In some embodiments, the isolation material 115 is formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), another suitable method, or a combination thereof.

[0041] Next, if Figure 1D As shown in FIG. 1 , according to some embodiments, the hard mask layer 112 is removed to expose the protection layer 110. In some embodiments, the hard mask layer 112 is removed by an etching process, such as dry etching or wet etching.

[0042] Afterwards, if Figure 1EAs shown in FIG. 1 , according to some embodiments, after removing the hard mask layer 112, the top of the isolation material 115 is removed to form an isolation structure 116. The top surface of the isolation structure 116 is lower than the top surface of the fin structure 104a / 104b / 104c.

[0043] In accordance with some embodiments, the isolation structure 116 is configured to electrically isolate active regions (eg, fin structures 104 a / 104 b / 104 c ) of the semiconductor structure 100 a and is also referred to as a shallow trench isolation (STI) feature.

[0044] In some embodiments, the isolation structure 116 is made of silicon oxide, silicon nitride, silicon oxynitride (SiON), another suitable insulating material, or a combination thereof. In some embodiments, a dielectric liner (not shown) is formed before forming the isolation structure 116, and the dielectric liner is made of silicon nitride, and the isolation structure formed over the dielectric liner is made of silicon oxide.

[0045] like Figure 1F As shown in FIG. 1 , according to some embodiments, after forming the isolation structure 116, a dummy gate structure 118 is formed across the fin structures 104a / 104b / 104c and extends over the isolation structure 116. The dummy gate structure 118 can be used to define the source / drain (S / D) region and the channel region of the resulting semiconductor structure 100a. The dummy gate structure 118 is formed along the Y axis.

[0046] Figure 1F-T shows a schematic top view of an intermediate dielectric stage of a semiconductor structure 100a according to some embodiments, and Figure 1F-T The box A1 shown in corresponds to Figure 1F The structure shown in .

[0047] In some embodiments, the dummy gate structure 118 includes a dummy gate dielectric layer 120 and a dummy gate electrode layer 122. In some embodiments, the dummy gate dielectric layer 120 is made of one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride (SiON), HfO2, HfZrO, HfSiO, HfTiO, HfAlO, or a combination thereof. In some embodiments, the dummy gate dielectric layer 120 is formed using thermal oxidation, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), another suitable method, or a combination thereof.

[0048] In some embodiments, the dummy gate electrode layer 122 includes polysilicon (poly-Si), polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal or a combination thereof. In some embodiments, the dummy gate electrode layer 122 is formed using chemical vapor deposition (CVD), physical vapor deposition (PVD) or a combination thereof.

[0049] The formation of the dummy gate structure 118 may include conformally forming a dielectric material as a dummy gate dielectric layer 120. Thereafter, a conductive material may be formed over the dielectric material as a dummy gate electrode layer 122, and a hard mask layer (not shown) may be formed over the conductive material. Next, the dielectric material and the conductive material may be patterned through the hard mask layer (not shown) to form the dummy gate structure 118.

[0050] like Figure 1G As shown in , according to some embodiments, after forming the dummy gate structure 118, a first gate spacer layer 126 and a second gate spacer layer 128 are formed along opposite sidewalls of the dummy gate structure 118 and opposite sidewalls of the source / drain regions of the fin structures 104a / 104b / 104c to cover opposite sidewalls of the dummy gate structure 118 and opposite sidewalls of the source / drain regions of the fin structures 104a / 104b / 104c.

[0051] The first gate spacer layer 126 and the second gate spacer layer 128 may be configured to separate the source / drain (S / D) structure from the dummy gate structure 118 and support the dummy gate structure 118. The first gate spacer layer 126 and the second gate spacer layer 128 may be configured to limit the lateral growth of the subsequently formed source / drain structure and support the fin structure 104a / 104b / 104c.

[0052] The first gate spacer layer 126 and the second gate spacer layer 128 are made of different materials. The second gate spacer layer 128 has a high etching selectivity with respect to the first gate spacer layer 126. When the first gate spacer layer 126 is removed by the etching process, the second gate spacer layer 128 is not removed by the etching process.

[0053] In some embodiments, the first gate spacer layer 126 is made of a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and / or combinations thereof. In some embodiments, the second gate spacer layer 128 is made of a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and / or combinations thereof.

[0054] In some embodiments, the first gate spacer layer 126 has a thickness in a range from about 1 nm to about 5 nm. In some embodiments, the second gate spacer layer 128 has a thickness in a range from about 1 nm to about 5 nm.

[0055] The formation of the first gate spacer layer 126 and the second gate spacer layer 128 may include: conformally depositing a dielectric material covering the dummy gate structure 118, the protective layer 110, the fin structure 104a / 104b / 104c and the isolation structure 116 above the substrate 102; and performing an anisotropic etching process, such as dry plasma etching, to remove the dielectric layer covering the top surface of the dummy gate structure 118, the protective layer 110 and the portion of the isolation structure 116.

[0056] Next, if Figure 1H As shown in FIG. 1 , according to some embodiments, after forming the first gate spacer layer 126 and the second gate spacer layer 128, the source / drain (S / D) region of the fin structure 104a / 104b / 104c is recessed to form a source / drain (S / D) groove 130. More specifically, according to some embodiments, the first semiconductor material layer 106 and the second semiconductor material layer 108 not covered by the dummy gate structure 118, the first gate spacer layer 126 and the second gate spacer layer 128 are removed.

[0057] In some embodiments, the fin structures 104a / 104b / 104c are recessed by performing an etching process. The etching process may be an anisotropic etching process, such as dry plasma etching, and the dummy gate structure 118, the first gate spacer layer 126, and the second gate spacer layer 128 are used as etching masks during the etching process. In some embodiments, the first gate spacer layer 126 and the second gate spacer layer 128 in the S / D region are also recessed to form a lowered first gate spacer layer 126 and a lowered second gate spacer layer 128.

[0058] Afterwards, if Fig. 1I As shown in FIG. 1 , the first semiconductor material layer 106 exposed by the S / D recess 130 is laterally recessed to form a notch 132 in accordance with some embodiments.

[0059] In some embodiments, an etching process is performed on the semiconductor structure 100a to cause the first semiconductor material layer 106 of the fin structure 104a / 104b / 104c to be laterally recessed from the source / drain recess 130. In some embodiments, during the etching process, the first semiconductor material layer 106 has a greater etching rate (or etching amount) than the second semiconductor material layer 108, thereby forming a notch 132 between adjacent second semiconductor material layers 108. In some embodiments, the etching process is an isotropic etching, such as dry chemical etching, remote plasma etching, wet chemical etching, another suitable technique, and / or a combination thereof.

[0060] Afterwards, if Figure 1JAs shown in FIG. 1 , according to some embodiments, an inner spacer layer 134 is formed in the notch 132 between the second semiconductor material layers 108. In some embodiments, the inner spacer layer 134 and the protection layer 110 are made of different materials because the protection layer 110 and the inner spacer layer 134 are made in different steps.

[0061] According to some embodiments, the internal spacer layer 134 is configured to separate source / drain structures and gate structures formed in subsequent fabrication processes.

[0062] In some embodiments, the inner spacer layer 134 is made of a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or a combination thereof. In some embodiments, the inner spacer layer 134 is formed by a deposition process, such as a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, another applicable process, or a combination thereof.

[0063] Next, if Figure 1K As shown in FIG. 1 , according to some embodiments, after forming the inner spacer 134, a source / drain (S / D) structure 136 is formed in the source / drain (S / D) recess 130. The topmost surface of the protection layer 110 is higher than the topmost surface of the S / D structure 136. In addition, the bottommost surface of the protection layer 110 is higher than the topmost surface of the source / drain structure 136.

[0064] In some embodiments, the S / D structure 136 is formed using an epitaxial growth process, such as molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), vapor phase epitaxy (VPE), another suitable epitaxial growth process, or a combination thereof. In some embodiments, the S / D structure 136 is made of any suitable material, such as Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, SiC, SiCP, or a combination thereof.

[0065] In some embodiments, the S / D structure 136 is doped in situ during the epitaxial growth process. For example, the S / D structure 136 can be epitaxially grown SiGe doped with boron (B). For example, the S / D structure 136 can be epitaxially grown Si doped with carbon to form a silicon:carbon (Si:C) source / drain component, doped with phosphorus to form a silicon:phosphorus (Si:P) source / drain component, or doped with carbon and phosphorus to form a silicon carbon phosphorus (SiCP) source / drain component. In some embodiments, after the epitaxial growth process, the S / D structure 136 is doped in one or more implantation processes.

[0066] Afterwards, if Figure 1LAs shown in FIG. 1 , after forming the S / D structure 136 , an etch stop layer 138 is conformally formed to cover the S / D structure 136 , and an interlayer dielectric (ILD) layer 140 is formed over the contact etch stop layer 138 , according to some embodiments.

[0067] In some embodiments, the etch stop layer 138 is made of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, another suitable dielectric material, or a combination thereof. The dielectric material for the etch stop layer 138 can be conformally deposited over the semiconductor structure by performing chemical vapor deposition (CVD), ALD, other application methods, or a combination thereof. In some embodiments, the etch stop layer 138 has a thickness in a range from about 1 nm to about 5 nm.

[0068] The ILD layer 140 may include multiple layers made of a variety of dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG) and / or other applicable low-k dielectric materials. The ILD layer 140 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other applicable processes.

[0069] According to some embodiments, after depositing the etch stop layer 138 and the ILD layer 140, a planarization process such as a CMP or an etch-back process may be performed until the gate electrode layer 120 of the dummy gate structure 118 is exposed, such as Figure 1L as shown in .

[0070] Figures 1M to 1ZB The semiconductor structure 100a according to some embodiments is shown along Figure 1L The line AA′ in FIG. 1 is a perspective view of the dummy gate structure 118 . Figure 1M-T shows a schematic top view of an intermediate dielectric stage of a semiconductor structure 100a according to some embodiments, and Figure 1M-T The box B1 shown in Figure 1M The structure shown in .

[0071] like Figure 1M As shown in FIG. 1 , a dummy gate structure 118 including a dummy gate dielectric layer 120 and a dummy gate electrode layer 122 is formed on the fin structure 104 a / 104 b / 104 c in accordance with some embodiments.

[0072] Next, if Figure 1N As shown in , according to some embodiments, a portion of the dummy gate structure 118 is removed to form a trench 141. More specifically, a top portion of the dummy gate electrode layer 122 and a portion of the dummy gate dielectric layer 120 are removed by using the protection layer 110 as an etch stop layer. In addition, a portion of the protection layer 110 may be removed. In some other embodiments, the protection layer 110 is not removed.

[0073] When removing part of the dummy gate electrode layer 122, the fin structure 104a / 104b / 104c protected by the protective layer 110 is not removed. Therefore, the top surface of the isolation structure 116 is exposed. In addition, the sidewall surface of the fin structure 104a / 104b / 104c is exposed. Because the protective layer 110 protects the underlying layer, the groove 141 is formed in a self-aligned manner. If there is no protective layer on the fin structure 104a / 104b / 104c, the fin structure 104a / 104b / 104c may be damaged due to the overlay offset (misalignment) of the lithography during the etching process for forming the groove 141. The overlay offset (misalignment) is solved by forming the protective layer 110.

[0074] Afterwards, if Fig.1O As shown in FIG. 1 , according to some embodiments, a liner layer 143 and a filling layer 144 are filled into the trench 141. The dielectric wall 142 is formed by the liner layer 143 and the filling layer 144. The liner layer 143 is in direct contact with the protection layer 110, the first semiconductor layer 106 and the second semiconductor layer 108 of the fin structure 104a / 104b / 104c.

[0075] It should be noted that the dielectric wall 142 is located between two adjacent fin structures, in particular, between the fin structure 104a and the fin structure 104b. In addition, the dielectric wall 142 penetrates the protective layer 110. The protective layer 110 is in direct contact with the liner layer 143 of the dielectric wall 142. The dielectric wall 142 has a top portion and a bottom portion, and the top portion is wider than the bottom portion. The dielectric wall 142 has a T-shaped structure. Because a portion of the protective layer 110 is removed, as shown in FIG. Figure 1N As shown in FIG. 1 , a portion of the dielectric wall 142 is embedded in the protective layer 110 .

[0076] In some embodiments, the liner layer 143 is made of silicon oxide (SiO), silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), or an applicable material. In some embodiments, the liner layer 143 is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other applicable processes.

[0077] In some embodiments, the filling layer 144 is made of silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), or a combination thereof. In some embodiments, the filling layer 144 is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other applicable processes.

[0078] Next, if Figure 1PAs shown in FIG. 1 , according to some embodiments, another portion of the dummy gate electrode layer 122 of the dummy gate structure 118 is removed to form a trench 147 . Therefore, a portion of the first gate spacer layer 126 is exposed by the trench 147 .

[0079] More specifically, a portion of the gate electrode layer 122 is removed by the removal process. Therefore, a portion of the dummy gate dielectric layer 120 is exposed. It should be noted that when removing a portion of the dummy gate structure 118, the dielectric wall 142 including the liner layer 143 and the filling layer 144 is not removed.

[0080] The removal process may include one or more etching processes. For example, when the dummy gate electrode layer 122 is polysilicon, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution may be used to selectively remove the dummy gate electrode layer 122 .

[0081] Afterwards, if Figure 1Q As shown in , according to some embodiments, the exposed first gate spacer layer 126 is removed to expose a portion of the second gate spacer layer 128. After the removal process, the outer sidewall surface of the first gate spacer layer 126 is substantially flush with the outer sidewall surface of the dummy gate dielectric layer 122. In some embodiments, the exposed first gate spacer layer 126 is removed by an etching process, such as a dry etching process or a wet etching process.

[0082] Next, if Figure 1R As shown in FIG. 1 , according to some embodiments, the exposed dummy gate dielectric layer 120 is removed. Thereafter, according to some embodiments, the first semiconductor material layer 106 is removed to form a nanostructure 108 ′ with the second semiconductor material layer 108 .

[0083] The topmost second semiconductor material layer 108T will be removed together with the first semiconductor material layer 106 because the thickness of the topmost second semiconductor material layer 108T is less than that of the other second semiconductor material layers 108. Therefore, the top surface, bottom surface and sidewall surface of the protection layer 110 are exposed. The dummy gate dielectric layer 120 can be removed using plasma dry etching, dry chemical etching and / or wet etching.

[0084] It should be noted that when the first semiconductor material layer 106 is removed, the protection layer 110 is not removed because the protection layer 110 has a high etching selectivity relative to the first semiconductor material layer 106 .

[0085] The nanostructure 108' serves as a channel layer of the semiconductor structure 100a. The S / D structure 136 is attached to the nanostructure 108'. In addition, when the first semiconductor material layer 106 is removed, a portion of the liner layer 143 is exposed.

[0086] It should be noted that after removing the exposed dummy gate dielectric layer 120, the outer sidewall surface of the first gate spacer layer 126 extends beyond the sidewall surface of the protection layer 110 and the sidewall surface of the nanostructure 108'. Therefore, there is a gap between the outer sidewall surface of the first gate spacer layer 126 and the outer sidewall surface of the protection layer 110. In other words, the first gate spacer layer 126 protrudes from the top surface and the sidewall surface of the protection layer 110. There is a step height between the first gate spacer layer 126 and the protection layer 110.

[0087] The first semiconductor material layer 106 can be removed by performing a selective wet etching process, such as an APM (e.g., ammonium hydroxide-hydrogen peroxide-water mixture) etching process. For example, the wet etching process uses an etchant such as ammonium hydroxide (NH4OH), TMAH, ethylenediamine catechol (EDP) and / or potassium hydroxide (KOH) solution. In some embodiments, the upper portion of the gate spacer layer 126 is also removed.

[0088] Next, if Figure 1S As shown in , according to some embodiments, after forming the nanostructure 108', the exposed portion of the pad layer 143 is removed. The remaining pad layer 143 is located between the nanostructure 108' and the filling layer 144 and is in direct contact with the nanostructure 108' and the filling layer 144. The pad layer 143 has several separated portions that are not connected to each other after removing the exposed portion of the pad layer 143.

[0089] Afterwards, if Figure 1T As shown in , according to some embodiments, an interface layer 152 is formed to surround the nanostructure 108', and then a gate dielectric layer 154 is formed on the interface layer 152, the isolation structure 116, the dielectric wall 142, and the protection layer 110. More specifically, the gate dielectric layer 154 is in direct contact with the protection layer 110, the dielectric wall 142, the isolation structure 116, and the interface layer 152. In other words, the protection layer 110 is surrounded by the gate dielectric layer 154. The gate dielectric layer 154 is in direct contact with the liner layer 143 of the dielectric wall 142.

[0090] It should be noted that the gate dielectric layer 154 is conformally formed on the interface layer 152, the isolation structure 116, the dielectric wall 142 and the protection layer 110, and therefore the trench 147 is not completely filled with the gate dielectric layer 154. The trench 147 still remains. It should be noted that the gate dielectric layer 154 is in direct contact with the filling layer 144 of the dielectric wall 142. In addition, the gate dielectric layer 154 is in direct contact with the sidewall surface of the protection layer 110.

[0091] In addition, since the first gate spacer layer 126 protrudes from the top surface and the sidewall surface of the protection layer 110, as shown in FIG. Figure 1RAs mentioned in , the gate dielectric layer 154 directly on the first gate spacer layer 126 still protrudes from the gate dielectric layer 154 directly on the protection layer 110. Due to the step height between the first gate spacer layer 126 and the protection layer 110, a gap still exists.

[0092] In some embodiments, the interface layer 152 is an oxide layer formed around the nanostructures 108' and on top of the base fin structure 105. In some embodiments, the interface layer 152 is formed by performing a thermal process.

[0093] In some embodiments, gate dielectric layer 154 is formed over interface layer 152 such that nanostructure 108' is surrounded (eg, wrapped) by gate dielectric layer 154. Furthermore, gate dielectric layer 154 also covers sidewalls of first gate spacer layer 126 and second gate spacer layer 128 according to some embodiments.

[0094] In some embodiments, the gate dielectric layer 154 is made of one or more dielectric material layers, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, another suitable high-k dielectric material, or a combination thereof. In some embodiments, the gate dielectric layer 154 is formed using chemical vapor deposition (CVD), atomic layer deposition (ALD), another suitable method, or a combination thereof.

[0095] Next, if Figure 1U As shown in FIG. 1 , according to some embodiments, a gate electrode layer 156 is formed on the gate dielectric layer 154. The gate structure 150 is composed of the interface layer 152, the gate dielectric layer 154, and the gate electrode layer 156. It should be noted that the gate electrode layer 156 is conformally formed on the gate dielectric layer 154, and therefore the trench 147 still remains and is not filled with the gate electrode layer 156.

[0096] In some embodiments, the gate electrode layer 156 is formed on the gate dielectric layer 154. In some embodiments, the gate electrode layer 156 is made of one or more conductive material layers, such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, a metal alloy, another suitable material, or a combination thereof. In some embodiments, the gate electrode layer 156 is formed using chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, another suitable method, or a combination thereof.

[0097] Other conductive layers, such as work function metal layers, may also be formed in the gate structure 150, but they are not shown in the figure. In some embodiments, the work function layer includes tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), molybdenum nitride, tungsten nitride (WN), ruthenium (Ru), or a combination thereof.

[0098] Afterwards, if Figure 1V As shown in FIG. 1 , according to some embodiments, a portion of the gate electrode layer 156 is removed. Therefore, after the portion of the gate electrode layer 156 is removed, the trench 147 has a T-shaped structure. The outer sidewall surface of the gate electrode layer 156 is substantially flush with the outer sidewall surface of the gate dielectric layer 154 because the gap between the outer sidewall surface of the first gate spacer layer 126 and the outer sidewall surface of the protection layer 110 is Figure 1R In other words, due to the step height between the first gate spacer layer 126 and the protection layer 110, the outer sidewall surface of the gate electrode layer 156 can be substantially coplanar with the outer sidewall surface of the gate dielectric layer 154. Therefore, the removal amount of the gate electrode layer 156 can be controlled by defining the step height between the first gate spacer layer 126 and the protection layer 110.

[0099] In some embodiments, portions of the gate electrode layer 156 are removed by an etching process, such as dry etching or wet etching.

[0100] It should be noted that in order to reduce undesirable capacitance between the gate electrode layer 156 and the S / D contact structure, the area of ​​the gate electrode layer 156 is reduced by removing portions of the gate electrode layer 156 .

[0101] Next, if Figure 1W As shown in , according to some embodiments, the exposed portion of the gate dielectric layer 154 is removed to expose the second gate spacer layer 128. After removing the exposed portion of the gate dielectric layer 154, the trench 147 remains. The second gate spacer layer 128 is exposed by the trench 147. In some embodiments, the exposed portion of the gate dielectric layer 154 is removed by an etching process, such as dry etching or wet etching.

[0102] It should be noted that the outer sidewall surface of the gate electrode layer 156 is substantially flush with the outer sidewall surface of the gate dielectric layer 154 because the gap between the outer sidewall surface of the first gate spacer layer 126 and the outer sidewall surface of the protection layer 110 is Figure 1R Created in the steps of .

[0103] The gate structure 150 includes a first gate structure 150a and a second gate structure 150b. The first gate structure 150a is separated from the second gate structure 150b by the dielectric wall 142. The first gate structure 150a and the second gate structure 150b are formed on opposite sidewall surfaces of the dielectric wall 142.

[0104] The first gate structure 150a includes an interface layer 152 surrounding the nanostructure 108′ of the first fin structure 104a, a gate dielectric layer 154 formed on the interface layer 152, and a gate electrode layer 156 formed on the gate dielectric layer 154. The second gate structure 150b includes an interface layer 152 surrounding the nanostructure 108′ of the second fin structure 104b and the third fin structure 104c, a gate dielectric layer 154 formed on the interface layer 152, and a gate electrode layer 156 formed on the gate dielectric layer 154.

[0105] Afterwards, if Figure 1X As shown in FIG. 1 , according to some embodiments, a liner layer 163 and a filling layer 164 are filled into the trench 147. The dielectric wall 162 is composed of the liner layer 163 and the filling layer 164. The liner layer 163 is in direct contact with the gate electrode layer 156. The liner layer 163 is used to prevent the gate electrode layer 156 from being oxidized by the filling layer 164. The liner layer 163 and the filling layer 164 are made of different materials.

[0106] It should be noted that the dielectric wall 162 is located between two adjacent fin structures 104b and 104c. The dielectric wall 162 has a top portion and a bottom portion, and the top portion is wider than the bottom portion. The dielectric wall 162 has a T-shaped structure.

[0107] In some embodiments, the liner layer 163 is made of silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or another applicable material. In some embodiments, the liner layer 163 is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other applicable processes. In some embodiments, the liner layer 163 has a thickness in a range from about 1 nm to about 10 nm.

[0108] In some embodiments, the filling layer 164 is made of silicon oxide (SiO), silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), or a combination thereof. In some embodiments, the filling layer 164 is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other applicable processes.

[0109] Next, if Figure 1YAs shown in FIG. 1 , according to some embodiments, a top portion of the filling layer 164 of the dielectric wall 162 is removed to form a groove 165. Therefore, a portion of the liner layer 163 is exposed by the groove 165. The topmost surface of the filling layer 164 of the dielectric wall 162 is higher than the top surface of the protection layer 110.

[0110] In some embodiments, portions of the filling layer 164 of the dielectric wall 162 are removed by an etching process, such as a dry etching process or a wet etching process.

[0111] Afterwards, if Figure 1Z As shown in , according to some embodiments, a horizontal portion of the liner layer 163 of the dielectric wall 162 is removed. Therefore, a vertical portion of the gate electrode layer 156 is exposed by the recess 165. It should be noted that the horizontal portion of the liner layer 163 directly on the gate electrode layer 156 is removed to expose the gate electrode layer 156, but the sidewall portion of the liner layer 163 is still located on the gate electrode layer 156.

[0112] In some embodiments, the horizontal portions of the liner layer 163 of the dielectric wall 162 are removed by an etching process, such as a dry etching process or a wet etching process.

[0113] Next, if Figure 1ZA As shown in , according to some embodiments, a conductive layer 168 is formed in the groove 165. The groove 165 is not completely filled with the conductive layer 168. The conductive layer 168 is in direct contact with the gate electrode layer 156 and is electrically connected to the gate electrode layer 156. The bottom surface of the conductive layer 168 is in direct contact with the gate electrode layer 156, but the sidewall surface of the conductive layer 168 is separated from the gate electrode layer 156 by the liner layer 163.

[0114] It should be noted that conductive layer 168 is selectively formed by a selective deposition process and thus is selectively formed on gate electrode layer 156. Although conductive layer 168 is mainly formed on the surface of the conductive material, conductive layer 168 may extend to a position directly on the top surface of dielectric wall 162.

[0115] The conductive layer 168 and the gate electrode layer 156 are made of different materials. An interface exists between the conductive layer 168 and the gate electrode layer 156.

[0116] In some embodiments, the conductive layer 168 is made of a conductive material including aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), cobalt, tantalum nitride (TaN), nickel silicide (NiS), cobalt silicide (CoSi), copper silicide, tantalum carbide (TaC), tantalum silicon nitride (TaSiN), tantalum carbonitride (TaCN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), other suitable conductive materials, or combinations thereof. In some embodiments, the conductive layer 168 is made of tungsten (W) that does not contain fluorine (F).

[0117] Conductive layer 168 may be formed using a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), plasma enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other suitable deposition process.

[0118] Afterwards, if Figure 1ZB As shown in , according to some embodiments, a dielectric layer 170 is formed on the conductive layer 168 and in the groove 165. Next, a planarization process such as CMP or an etch-back process may be performed. Next, according to some embodiments, an etch stop layer 172 is formed on the dielectric wall 162, the protection layer 110, and the dielectric layer 170, and a dielectric layer 174 is formed on the etch stop layer 172.

[0119] In some embodiments, dielectric layer 170 is made of silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials. Dielectric layer 170 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other suitable processes.

[0120] In some embodiments, the etch stop layer 172 is made of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, another suitable dielectric material, or a combination thereof. The dielectric material for the etch stop layer 172 can be conformally deposited over the semiconductor structure by performing chemical vapor deposition (CVD), ALD, other application methods, or a combination thereof.

[0121] The dielectric layer 174 may include multiple layers made of a variety of dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or another suitable low-k dielectric material. The dielectric layer 174 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes.

[0122] Next, a gate contact structure 178 is formed on the conductive layer 168. The gate contact structure 178 penetrates the dielectric layer 170 and directly contacts the conductive layer 168. The gate contact structure 178 is electrically connected to the gate electrode layer 156 through the conductive layer 168.

[0123] In some embodiments, the gate contact structure 178 is made of a conductive material including aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), cobalt, tantalum nitride (TaN), nickel silicide (NiS), cobalt silicide (CoSi), copper silicide, tantalum carbide (TaC), tantalum silicon nitride (TaSiN), tantalum carbonitride (TaCN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), other suitable conductive materials, or combinations thereof.

[0124] The gate contact structure 178 may be formed using a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), plasma enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other suitable deposition process.

[0125] like Figure 1ZB As shown in FIG. 1 , the first gate structure 150a is separated from the second gate structure 150b by the dielectric wall 142. The first gate structure 150a and the second gate structure 150b are formed on opposite sidewall surfaces of the dielectric wall 142. The top surface of the first gate structure 150a is substantially coplanar with the top surface of the dielectric wall 142. The top surface of the second gate structure 150b is substantially coplanar with the top surface of the dielectric wall 142.

[0126] The gate electrode layer 156 of the second gate structure 150 b extends from a first position to a second position. The first position is located on the nanostructure 108 ′ of the second fin structure 104 b, and the second position is located on the nanostructure 108 ′ of the third fin structure 104 c. A portion of the gate electrode layer 156 of the second gate structure 150 b is located directly below the dielectric wall 162 .

[0127] The top surface of the dielectric wall 142 is higher than the top surface of the protection layer 110. In addition, the top surface of the dielectric wall 162 is higher than the top surface of the protection layer 110. The top surface of the dielectric wall 162 is lower than the top surface of the dielectric wall 142. The top surface of the dielectric wall 162 is lower than the topmost surface of the gate electrode layer 156 of the first gate structure 150a and the second gate structure 150b.

[0128] If the protective layer 110 is not formed on the nanostructure 108', when a step is used to remove a portion of the gate electrode layer 156 by a CMP process, the uniformity of the height of the gate electrode layer 156 is poor due to CMP process variations. If the height of the gate electrode layer 156 is designed to be high enough to reduce the influence of the CMP process variations, another undesirable capacitance problem may occur. In order to improve the uniformity of the height and prevent the undesirable capacitance problem, the protective layer 110 is formed on the nanostructure 108'.

[0129] In addition, if the protective layer 110 is not formed on the nanostructure 108', the topmost nanostructure 108' may be slightly removed, and the thickness of the topmost nanostructure 108' is different from the thickness of the second topmost nanostructure 108'. Therefore, the performance of the semiconductor structure 100a may be reduced. Therefore, the protective layer 110 is formed on the nanostructure 108', and the protective layer 110 can protect the underlying nanostructure 108' from etching during the manufacturing process to maintain the thickness of each of the nanostructures 108'. Due to the protection of the protective layer 110, each of the nanostructures 108' has substantially the same thickness. When the uniformity of the thickness of each of the nanostructures 108' is improved, the performance of the semiconductor structure 100a is improved.

[0130] The protection layer 110 is configured to protect the underlying nanostructures 108' from being etched or damaged. A gate dielectric layer 154 and a gate electrode layer 156 are formed on the protection layer 110. The topmost surface of the gate electrode layer 156 is higher than the top surface of the protection layer 110.

[0131] like Figure 1ZB As shown in FIG. 1 , there is a first width W1 between an end of the gate electrode layer 156 and an end of the nanostructure 108 ′ in a horizontal direction. In some embodiments, the first width W1 is in a range from about 2 nm to about 12 nm.

[0132] If the thickness of the first width W1 is less than 2 nm, the threshold voltage (Vth) of the semiconductor structure 100a is difficult to control. If the thickness of the first width W1 is greater than 12 nm, the area of ​​the gate electrode layer 156 is too large, and the undesirable capacitance between the nanostructure 108' of the second fin structure 104b and the nanostructure 108' of the third fin structure 104c may increase. In other words, the portion of the gate electrode layer 156 located between the nanostructure 108' of the second fin structure 104b and the nanostructure 108' of the third fin structure 104c is replaced with a dielectric wall 162. Therefore, the area of ​​the gate electrode layer 156 is reduced to reduce the undesirable capacitance between the nanostructure 108' of the second fin structure 104b and the nanostructure 108' of the third fin structure 104c. In addition, the undesirable capacitance between the gate electrode layer 156 and the contact on the S / D structure 136 can be reduced. Therefore, the performance of the semiconductor structure 100a is improved.

[0133] There is a first recess distance D1 of the gate dielectric layer 154 measured from the top surface of the interface layer 152 and the top surface of the liner layer 143. In some embodiments, the first recess distance D1 of the gate dielectric layer 154 is in a range from about 0.1 nm to about 5 nm. When the first recess distance D1 of the gate dielectric layer 154 is in the above range, the coverage of the gate dielectric layer 154 on the nanostructure 108' is increased, and the controllability of the gate structure 150 is improved. Therefore, the performance of the semiconductor structure 100a is improved.

[0134] Figure 2 According to some embodiments, Figure 1ZB The cross-section of the semiconductor structure 100 a shown by line BB′ in FIG.

[0135] like Figure 2 As shown in FIG. 1 , there is a second width W2 between two adjacent second spacer layers 128. The second width W2 is obtained by implementing Figure 1Q The exposed first gate spacer layer 126 is removed to expose a portion of the second gate spacer layer 128. Since a major portion of the first spacer layer 126 is removed, the remaining first spacer layer 126 remains below the liner layer 163 of the dielectric wall 162.

[0136] Furthermore, the bottom surface of the first spacer layer 126 and the bottom surface of the second spacer layer 128 are in direct contact with the top surface of the protection layer 110 .

[0137] Figure 3 According to some embodiments, Figure 1ZB FIG. 1 is a cross-sectional view of the semiconductor structure 100 a shown along line CC′ in FIG.

[0138] like Figure 3As shown in FIG. 1 , the remaining first spacer layer 126 is located directly below the dielectric wall 162. The top surface of the second spacer layer 128 is higher than the top surface of the first spacer layer 126. In addition, the top surface of the second spacer layer 128 is higher than the bottom surface of the conductive layer 168.

[0139] It should be noted that the second width W2 is located between two adjacent second spacer layers 128. The second width W2 is obtained by implementing Figure 1Q The exposed first gate spacer layer 126 is removed to expose a portion of the second gate spacer layer 128. Since a major portion of the first spacer layer 126 is removed, the remaining first spacer layer 126 remains under the dielectric wall 162. In addition, the second width W2 is greater than the distance between two adjacent first spacer layers 126.

[0140] FIG. 4A to FIG. 4B A cross-sectional representation of a semiconductor structure 100 b is shown in accordance with some embodiments. FIG. 4A to FIG. 4B The semiconductor structure 100b includes a semiconductor structure similar to Figure 1ZB The semiconductor structure 100a of the device or Figure 1ZB The materials and processes used to form the semiconductor structure 100b may be similar to or the same as those described above for forming the semiconductor structure 100a, and are not repeated here.

[0141] Figure 4A The semiconductor structure 100b and Figure 1R The difference between the semiconductor structure 100 a and the semiconductor structure 100 b is that the liner layer 143 of the dielectric wall 142 is not removed. The liner layer 143 is a continuous layer and is exposed by the trench 147 .

[0142] Afterwards, if Figure 4B As shown in FIG. 1 , the interface layer 152 is formed on the nanostructure 108 ′, and the gate dielectric layer 154 is formed on the interface layer 152. It should be noted that the gate dielectric layer 154 is formed on the sidewall surface of the liner layer 143 of the dielectric wall 142. Figure 1ZB Compared with the semiconductor structure 100a shown in Figure 4B The first recessed distance D1 of the gate dielectric layer 154 cannot be observed.

[0143] FIG. 5A to FIG. 5B A cross-sectional representation of a semiconductor structure 100 c is shown in accordance with some embodiments. FIG. 5A to FIG. 5B The semiconductor structure 100c includes a semiconductor structure similar to Figure 1ZB The semiconductor structure 100a of the device or Figure 1ZBThe materials and processes used to form the semiconductor structure 100c may be similar to or the same as those described above for forming the semiconductor structure 100a, and are not repeated here.

[0144] Figure 5A The semiconductor structure 100c and Figure 1S The difference between the semiconductor structure 100 a and the semiconductor structure 100 a is that no liner layer is formed between the gate electrode layer 156 and the filling layer 164 . The dielectric wall 162 is made of the filling layer 164 .

[0145] Next, if Figure 5B As shown in FIG. 1 , the conductive layer 168 is formed on the dielectric wall 162 having the filling layer 164 but without the liner layer 163. In addition, the sidewall surface of the conductive layer 168 is in direct contact with the gate electrode layer 156, but Figure 1ZB In the embodiment, the side wall surface of the conductive layer 168 is not in direct contact with the gate electrode layer 156.

[0146] FIG. 6A to FIG. 6B A cross-sectional representation of a semiconductor structure 100 d is shown in accordance with some embodiments. FIG. 6A to FIG. 6B The semiconductor structure 100d includes a semiconductor structure similar to Figure 1ZB The semiconductor structure 100a of the device or Figure 1ZB The materials and processes used to form the semiconductor structure 100d may be similar to or the same as those described above for forming the semiconductor structure 100a, and are not repeated here.

[0147] Fig. 6A The semiconductor structure 100d and Figure 1N The difference between the semiconductor structure 100a of FIG. 1 and FIG. 2 is that the protection layer 110 is not recessed when the dummy gate electrode layer 122 is removed. The protection layer 110 still has a rectangular structure.

[0148] Afterwards, if Figure 6B As shown in FIG. 1 , a dielectric wall 142 is formed in the trench 141. The dielectric wall 142 has a T-shaped structure.

[0149] Figure 7 A cross-sectional representation of a semiconductor structure 100 e is shown in accordance with some embodiments. Figure 7 The semiconductor structure 100e includes a semiconductor structure similar to Figure 4B The semiconductor structure 100b of the device or Figure 4BThe materials and processes used to form the semiconductor structure 100e may be similar to or the same as those described above for forming the semiconductor structure 100e, and are not repeated here.

[0150] Figure 7 The semiconductor structure 100e and Figure 4B The difference between the semiconductor structure 100b of FIG. 1 and FIG. 2 is that the protection layer 110 is not recessed when the dummy gate electrode layer 122 is removed. The protection layer 110 still has a rectangular structure.

[0151] Figure 8 A cross-sectional representation of a semiconductor structure 100 f is shown in accordance with some embodiments. Figure 8 The semiconductor structure 100f includes a semiconductor structure similar to Figure 5B The semiconductor structure 100c of the device or Figure 5B The materials and processes used to form the semiconductor structure 100f may be similar to or the same as those described above for forming the semiconductor structure 100c, and are not repeated here.

[0152] Figure 8 The semiconductor structure 100f and Figure 4B The difference between the semiconductor structure 100b of FIG. 1 and FIG. 2 is that the protection layer 110 is not recessed when the dummy gate electrode layer 122 is removed. The protection layer 110 still has a rectangular structure.

[0153] To improve the uniformity of the height of the gate structures 150a / 150b and prevent undesirable capacitance problems, a protection layer 110 is formed on the nanostructures 108'. The protection layer 110 may protect the underlying nanostructures 108' from damage to maintain the thickness of the nanostructures 108'.

[0154] In addition, a portion of the gate electrode layer 156 located between the nanostructure 108' of the second fin structure 104b and the nanostructure 108' of the third fin structure 104c is replaced with the dielectric wall 162. Therefore, the area of ​​the gate electrode layer 156 is reduced to reduce the undesired capacitance between the nanostructure 108' of the second fin structure 104b and the nanostructure 108' of the third fin structure 104c. In addition, the undesired capacitance between the gate electrode layer 156 and the contact on the S / D structure 136 can be reduced. Therefore, the performance of the semiconductor structure 100a is improved.

[0155] In addition, although disclosed method is shown and described as a series of steps or events below, it should be understood that in some other embodiments, the shown order of such steps or events can be changed. For example, some steps can occur in different orders and / or with other steps or events except those shown and / or described above. In addition, not all steps shown are necessary for implementing one or more aspects or embodiments described above. In addition, one or more of the steps described above can be performed in one or more separate steps and / or stages.

[0156] In addition, the terms "approximately", "substantially", "substantially" and "about" described above take into account small variations and may vary in different technologies and are within the range of deviations understood by those skilled in the art. For example, when used in conjunction with an event or situation, the term can refer to instances where the event or situation occurs exactly as well as instances where the event or situation occurs very close to occurring.

[0157] Embodiments for forming a semiconductor structure may be provided. Embodiments of a semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a first nanostructure and a second nanostructure formed above a substrate. A protective layer is formed on the first nanostructure and the second nanostructure. A gate structure is formed on the nanostructure, and a first spacer layer and a second spacer layer are formed on opposite sidewall surfaces of the gate structure. A dielectric wall is located between the first nanostructure and the second nanostructure. Because a portion of the gate electrode layer of the gate structure is replaced with the dielectric wall, the area of ​​the gate electrode layer is reduced. Undesirable capacitance in the semiconductor structure is reduced. In addition, due to the protection of the protective layer, each of the nanostructures has substantially the same thickness. The uniformity of the thickness of each of the nanostructures is improved. Therefore, the performance of the semiconductor structure is improved.

[0158] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a plurality of first nanostructures located above a substrate and a plurality of second nanostructures adjacent to the first nanostructures. The semiconductor structure includes a protective layer located above the first nanostructure and a first gate structure formed on the first nanostructure. The semiconductor structure includes a second gate structure formed on the second nanostructure. The semiconductor structure includes a first dielectric wall located between the first gate structure and the second gate structure, and a top surface of the first dielectric wall is higher than a top surface of the protective layer.

[0159] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a plurality of first nanostructures located above a substrate and a plurality of second nanostructures adjacent to the first nanostructures. The semiconductor structure includes a first protective layer located above the first nanostructure and a first gate structure formed on the first nanostructure and the second nanostructure. The semiconductor structure also includes a first dielectric wall located between the first nanostructure and the second nanostructure, and a top surface of the first gate structure is higher than a top surface of the first dielectric wall.

[0160] In some embodiments, a method for forming a semiconductor structure is provided. The method includes: forming a first fin structure and a second fin structure respectively above a substrate, and the first fin structure includes a first semiconductor material layer and a second semiconductor material layer that are alternately stacked, and the second fin structure includes a first semiconductor material layer and a second semiconductor material layer that are alternately stacked. The method includes: forming a first protective layer on the first fin structure and forming a second protective layer on the second fin structure; and forming a dummy gate structure across the first fin structure and the second fin structure. The method also includes: forming a first spacer layer and a second spacer layer on the sidewall surface of the dummy gate structure; and removing a portion of the dummy gate structure to expose the first spacer layer. The method includes: removing a portion of the first spacer layer to expose a portion of the second spacer layer; and removing a portion of the first semiconductor material layer to form a first nanostructure and a second nanostructure. The method includes: forming a gate dielectric layer on the first nanostructure and the second nanostructure, and the gate dielectric layer is located on the first spacer layer and the second spacer layer. The method includes: forming a gate electrode layer on the gate dielectric layer; and removing a portion of the gate electrode layer. The method includes removing a portion of the gate dielectric layer to expose a second spacer layer; and forming a dielectric wall between the first nanostructure and the second nanostructure.

[0161] Some embodiments of the present application provide a semiconductor structure, including: a plurality of first nanostructures located above a substrate; a plurality of second nanostructures adjacent to the first nanostructures; a protective layer located above the first nanostructures; a first gate structure formed on the first nanostructures; a second gate structure formed on the second nanostructures; and a first dielectric wall located between the first gate structure and the second gate structure, wherein a top surface of the first dielectric wall is higher than a top surface of the protective layer.

[0162] In some embodiments, the first gate structure is separated from the second gate structure by the first dielectric wall. In some embodiments, the semiconductor structure further includes: a plurality of third nanostructures adjacent to the second nanostructure; and a second dielectric wall located between the second nanostructure and the third nanostructure, wherein the top surface of the second dielectric wall is lower than the top surface of the first dielectric wall. In some embodiments, a portion of the second gate structure is located directly below the second dielectric wall. In some embodiments, the semiconductor structure further includes: a conductive layer formed on the second dielectric wall and the second gate structure; and a contact structure formed on the conductive layer. In some embodiments, the first dielectric wall includes a liner layer and a filling layer on the liner layer, and the liner layer is in direct contact with the first nanostructure. In some embodiments, the first gate structure includes a gate dielectric layer and a gate electrode layer, and the gate dielectric layer of the first gate structure is in direct contact with the filling layer. In some embodiments, the first gate structure is formed on the sidewall surface of the first dielectric wall. In some embodiments, the protective layer is in direct contact with the first dielectric wall. In some embodiments, a portion of the first dielectric wall is embedded in the protective layer.

[0163] Other embodiments of the present application provide a semiconductor structure, including: a plurality of first nanostructures located above a substrate; a plurality of second nanostructures adjacent to the first nanostructures; a first protective layer located above the first nanostructures; a first gate structure formed on the first nanostructures and the second nanostructures; and a first dielectric wall located between the first nanostructures and the second nanostructures, wherein a top surface of the first gate structure is higher than a top surface of the first dielectric wall.

[0164] In some embodiments, the semiconductor structure further comprises: a conductive layer formed on the first dielectric wall and the first gate structure; and a contact structure formed on the conductive layer. In some embodiments, a portion of the first gate structure is located directly below the first dielectric wall. In some embodiments, the semiconductor structure further comprises: a plurality of third nanostructures adjacent to the second nanostructure; and a second dielectric wall located between the second nanostructure and the third nanostructure, wherein a top surface of the second dielectric wall is higher than the top surface of the first dielectric wall. In some embodiments, the semiconductor structure further comprises: a second protective layer formed on the third nanostructure, wherein a portion of the second dielectric wall is embedded in the second protective layer. In some embodiments, the semiconductor structure further comprises: a first spacer layer adjacent to the first gate structure; and a second spacer layer formed on the first spacer layer, wherein a portion of the first spacer layer is located directly below the first dielectric wall.

[0165] Some other embodiments of the present application provide a method for forming a semiconductor structure, comprising: forming a first fin structure and a second fin structure respectively above a substrate, wherein the first fin structure includes a first semiconductor material layer and a second semiconductor material layer alternately stacked, and the second fin structure includes a first semiconductor material layer and a second semiconductor material layer alternately stacked; forming a first protective layer on the first fin structure, and forming a second protective layer on the second fin structure; forming a dummy gate structure across the first fin structure and the second fin structure; forming a first spacer layer and a second spacer layer on the sidewall surface of the dummy gate structure; removing a portion of the dummy gate structure to expose the first spacer layer; removing a portion of the first spacer layer to expose a portion of the second spacer layer; removing a portion of the first semiconductor material layer to form a first nanostructure and a second nanostructure; forming a gate dielectric layer on the first nanostructure and the second nanostructure, wherein the gate dielectric layer is located on the first spacer layer and the second spacer layer; forming a gate electrode layer on the gate dielectric layer; removing a portion of the gate electrode layer; removing a portion of the gate dielectric layer to expose the second spacer layer; and forming a dielectric wall between the first nanostructure and the second nanostructure.

[0166] In some embodiments, the method for forming a semiconductor structure further includes: forming the gate dielectric layer on the protective layer; and forming the gate electrode layer on the protective layer, wherein the top surface of the gate electrode layer is higher than the top surface of the protective layer. In some embodiments, the method for forming a semiconductor structure further includes: removing the top portion of the dielectric wall to expose the gate electrode layer; and forming a conductive layer on the dielectric wall and the gate electrode layer; and forming a contact structure on the conductive layer. In some embodiments, a portion of the gate electrode layer is located directly below the dielectric wall.

[0167] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a substrate to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A semiconductor structure comprising: A plurality of first nanostructures are disposed above the substrate; a plurality of second nanostructures, adjacent to the first nanostructure; A protective layer, located above the first nanostructure; A first gate structure formed on the first nanostructure; A second gate structure formed on the second nanostructure; and A first dielectric wall is located between the first gate structure and the second gate structure, wherein a top surface of the first dielectric wall is higher than a top surface of the protection layer.

2. The semiconductor structure according to claim 1, wherein: The first gate structure is separated from the second gate structure by the first dielectric wall.

3. The semiconductor structure according to claim 1, further comprising: a plurality of third nanostructures, adjacent to the second nanostructure; as well as A second dielectric wall is located between the second nanostructure and the third nanostructure, wherein a top surface of the second dielectric wall is lower than the top surface of the first dielectric wall.

4. The semiconductor structure according to claim 3, wherein: A portion of the second gate structure is located directly below the second dielectric wall.

5. The semiconductor structure according to claim 3, further comprising: a conductive layer formed on the second dielectric wall and the second gate structure; as well as A contact structure is formed on the conductive layer.

6. The semiconductor structure according to claim 1, wherein: The first dielectric wall includes a liner layer and a filling layer on the liner layer, and the liner layer is in direct contact with the first nanostructure.

7. The semiconductor structure according to claim 6, wherein: The first gate structure includes a gate dielectric layer and a gate electrode layer, and the gate dielectric layer of the first gate structure is in direct contact with the filling layer.

8. The semiconductor structure according to claim 1, wherein: The first gate structure is formed on a sidewall surface of the first dielectric wall.

9. A semiconductor structure comprising: A plurality of first nanostructures are disposed above the substrate; a plurality of second nanostructures, adjacent to the first nanostructure; A first protective layer, located above the first nanostructure; A first gate structure formed on the first nanostructure and the second nanostructure; as well as A first dielectric wall is located between the first nanostructure and the second nanostructure, wherein a top surface of the first gate structure is higher than a top surface of the first dielectric wall.

10. A method for forming a semiconductor structure, comprising: Forming a first fin structure and a second fin structure respectively over the substrate, wherein the first fin structure comprises a first semiconductor material layer and a second semiconductor material layer stacked alternately, and the second fin structure comprises a first semiconductor material layer and a second semiconductor material layer stacked alternately; forming a first protective layer on the first fin structure, and forming a second protective layer on the second fin structure; forming a dummy gate structure across the first fin structure and the second fin structure; forming a first spacer layer and a second spacer layer on a sidewall surface of the dummy gate structure; removing a portion of the dummy gate structure to expose the first spacer layer; removing portions of the first spacer layer to expose portions of the second spacer layer; removing a portion of the first semiconductor material layer to form a first nanostructure and a second nanostructure; forming a gate dielectric layer on the first nanostructure and the second nanostructure, wherein the gate dielectric layer is located on the first spacer layer and the second spacer layer; forming a gate electrode layer on the gate dielectric layer; removing a portion of the gate electrode layer; removing a portion of the gate dielectric layer to expose the second spacer layer; and A dielectric wall is formed between the first nanostructure and the second nanostructure.

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