Semiconductor power device, method of manufacture, power module, conversion circuit and vehicle

Abstract

The application discloses a semiconductor power device, a preparation method, a power module, a conversion circuit and a vehicle, and relates to the technical field of semiconductor power devices. The semiconductor power device comprises a semiconductor body, a trench gate structure, a gate trench on a first surface of the semiconductor body, a first contact region and a body region, wherein the first contact region comprises a first sub-contact region and a second sub-contact region, which respectively extend into the semiconductor body from the first surface, the first sub-contact region is arranged along a side wall of the gate trench and is in contact with the trench gate structure, the second sub-contact region is located on a side of the first sub-contact region away from the trench gate structure, the length of the first sub-contact region is greater than or equal to the thickness of the body region in the direction from the first surface to a second surface, and a contact metal layer is located on a second surface of the semiconductor body and forms a Schottky contact with the second surface of the semiconductor body. The technical scheme provided by the application simplifies the preparation difficulty of the semiconductor power device and reduces the energy loss of the device in a reverse freewheeling state.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor technology, and in particular to a semiconductor power device, a preparation method, a power module, a conversion circuit and a vehicle. BACKGROUND

[0002] As a representative of the third generation semiconductor material, silicon carbide (SiC) has excellent physical and electrical properties. Compared with silicon material, SiC material has a large band gap, high breakdown field, high thermal conductivity, high electron saturation rate, strong radiation resistance and other advantages, so the semiconductor device prepared by using SiC material can not only operate stably at a higher temperature, but also is suitable for high-voltage and high-frequency scenes.

[0003] Power metal oxide semiconductor field effect transistor (MOSFET) is widely used in the field of high speed and high power. The MOS device of SiC material commonly used in the related technology is an enhancement type device, which is not conductive in normal state and needs to be applied with a positive voltage on the gate to form a communication conduction. The depletion mode MOS device is conductive in normal state, and the off state needs to be applied with a negative voltage on Vgs to make the device channel off, so the depletion mode MOS device can respond and control current flow faster, with small conduction loss, and is more suitable for high-frequency circuits and switching circuits. In the preparation method of the current depletion mode trench MOS device, an external anti-parallel diode of the depletion mode trench MOS is usually used for reverse current conduction, however, the external anti-parallel diode of the depletion mode trench MOS device increases the preparation difficulty of the device, and the on-voltage drop of the diode is large, the energy loss of the device in the reverse current conduction state is large, which affects the performance of the device. SUMMARY

[0004] Embodiments of the present application provide a semiconductor power device, a preparation method, a power module, a conversion circuit and a vehicle to simplify the preparation difficulty of the semiconductor device and reduce the energy loss of the device in the reverse current conduction state.

[0005] According to an aspect of the present application, a semiconductor device is provided, comprising:

[0006] a semiconductor body; the semiconductor body comprises a first surface and a second surface arranged oppositely, the first surface comprises a first region surface and a second region surface, and the first region surface is provided with a gate trench;

[0007] a trench gate structure; the trench gate structure is located in the gate trench;

[0008] The semiconductor body comprises a first contact region and a body region; the first contact region comprises a first sub-contact region and a second sub-contact region, the first sub-contact region and the second sub-contact region respectively extend from the first surface into the semiconductor body, the first sub-contact region is arranged along the gate trench sidewall and is in contact with the trench gate structure; the second sub-contact region is in contact with the first sub-contact region and is located on a side of the first sub-contact region away from the trench gate structure;

[0009] The body region is located on a side of the first sub-contact region away from the trench gate structure and on a side of the second sub-contact region close to the second surface; in the direction from the first surface to the second surface, the length of the first sub-contact region is greater than or equal to the thickness of the body region;

[0010] The first electrode is located on the first region surface of the semiconductor body and is in contact with the second sub-contact region;

[0011] The contact metal layer is located on the second region surface of the semiconductor body, and the contact metal layer forms a Schottky contact with the second region surface of the semiconductor body.

[0012] Optionally, the semiconductor device further comprises: a gate electrode located on the first region surface of the semiconductor body and in contact with the trench gate structure; wherein the first electrode, the gate electrode and the contact metal layer are arranged in the same layer.

[0013] Optionally, the semiconductor body further comprises: a second contact region, the second contact region is located on a side of the first sub-contact region away from the trench gate structure and on a side of the body region away from the second surface; the second contact region is different from the first sub-contact region in conductivity type; the first electrode is in contact with the second sub-contact region and the second contact region.

[0014] Optionally, the first surface further comprises a third region surface; the semiconductor body further comprises a body diode, and a second conductivity type region of the body diode is located on the third region surface.

[0015] According to another aspect of the present application, a preparation method of a semiconductor device is provided, comprising:

[0016] forming a semiconductor body; the semiconductor body comprises oppositely arranged first and second surfaces, the first surface comprises a first region surface and a second region surface, and a gate trench is arranged on the first region surface;

[0017] forming a trench gate structure in the gate trench and forming a first contact region and a body region on at least one side of the trench gate structure; wherein the first contact region comprises a first sub-contact region and a second sub-contact region, the first sub-contact region and the second sub-contact region respectively extend from the first surface into the semiconductor body, the first sub-contact region is disposed along the sidewall of the gate trench and contacts the trench gate structure, and the second sub-contact region contacts the first sub-contact region and is located on a side of the first sub-contact region away from the trench gate structure; in a direction from the first surface to the second surface, a length of the first sub-contact region is greater than or equal to a thickness of the body region;

[0018] forming a contact metal layer on a second region surface of the semiconductor body; the contact metal layer forms a Schottky contact with the second region surface of the semiconductor body;

[0019] forming a first electrode on the first region surface of the semiconductor body, the first electrode contacts the second sub-contact region.

[0020] Optionally, the method for manufacturing the semiconductor device further comprises: forming a gate electrode that contacts the gate structure.

[0021] Optionally, forming a trench gate structure in the gate trench and forming a first contact region and a body region on at least one side of the trench gate structure comprises:

[0022] forming a first mask layer on the first surface of the semiconductor body and patterning the first mask layer to form a first opening in the first mask layer, the first opening exposes the first region surface;

[0023] based on the patterned first mask layer, implanting ions of a second conductive type into the first region surface of the semiconductor body to form an initial body region;

[0024] removing the first mask layer, forming a second mask layer on the first surface of the semiconductor body, and patterning the second mask layer to form at least one second opening in the second mask layer, the second opening exposes the initial body region; a width of the second opening is less than a width of the first opening;

[0025] based on the patterned second mask layer, implanting ions of a first conductive type into the initial body region to form at least one first sub-region on a surface of the initial body region away from the second surface;

[0026] removing the second mask layer, forming a third mask layer on the first surface of the semiconductor body, and patterning the third mask layer to form a third opening in the third mask layer, the third opening exposing a preset position of the trench gate structure; wherein the third opening exposes the initial body region and a region adjacent to the initial body region and the first sub-region;

[0027] forming a spacer layer in the third opening adjacent to the sidewall of the first sub-region to form a fourth opening in the third mask layer, the fourth opening having a width smaller than the third opening; wherein the width of the fourth opening is greater than or equal to the width of the initial body region exposed by the third opening;

[0028] forming a gate trench on the first region surface exposed by the fourth opening, and forming a first barrier layer in the gate trench;

[0029] removing the spacer layer on the sidewall of the third opening, and implanting ions of a first conduction type into the exposed first region surface to form a first sub-contact region; wherein the first sub-region remaining after forming the first sub-contact region serves as a second sub-contact region, and the initial body region not implanted with ions of the first conduction type serves as the body region;

[0030] removing the first barrier layer, and forming a trench gate structure in the gate trench.

[0031] Optionally, the semiconductor body further comprises a second contact region; and the method for manufacturing the semiconductor device further comprises: forming a second contact region on at least one side of the trench gate structure; the second contact region is located on a side of the first contact region away from the trench gate structure, and on a side of the body region away from the second surface.

[0032] Optionally, forming a second contact region on at least one side of the trench gate structure comprises: forming a second barrier layer on the surface of the first barrier layer and the first surface of the semiconductor body; patterning the second barrier layer to form an opening in the second barrier layer, the opening exposing a preset position of the second contact region; implanting ions of a second conduction type into the preset position of the second contact region based on the patterned second barrier layer to form the second contact region; and removing the second barrier layer.

[0033] Optionally, forming a second contact region at at least one side of the trench gate structure comprises: after forming the first sub-contact region, removing the third mask layer and removing the first barrier layer; forming an etching stop layer on the sidewall of the gate trench and the first surface of the semiconductor body; forming a third barrier layer on the surface of the etching stop layer, the third barrier layer having a thickness greater than that of the etching stop layer; patterning the third barrier layer to form an opening in the third barrier layer, the opening exposing the etching stop layer at a preset position of the second contact region; based on the patterned third barrier layer, implanting ions of the second conductivity type into the preset position of the second contact region to form the second contact region.

[0034] Before forming the trench gate structure in the gate trench, the method further comprises: removing the third barrier layer and the etching stop layer.

[0035] Optionally, forming the trench gate structure in the gate trench comprises: forming a gate insulating layer on the sidewall of the gate trench; and forming a polysilicon gate on the surface of the gate insulating layer.

[0036] Optionally, the first surface further comprises a third region surface, and forming the initial body region further comprises: implanting ions of the second conductivity type into the third region surface to form a second conductivity type region of a body diode.

[0037] Forming the second sub-contact region further comprises: implanting ions of the second conductivity type into the second conductivity type region of the body diode again to increase the ion doping concentration of the surface of the second conductivity type region of the body diode.

[0038] Optionally, before forming the gate electrode contacting the gate structure and the first electrode contacting the second sub-contact region on the first region surface of the semiconductor body, the method further comprises:

[0039] Forming a passivation layer on the first region surface of the semiconductor body, and forming a first electrode connecting port exposing the second sub-contact region and a gate connecting port exposing the gate structure in the passivation layer.

[0040] According to another aspect of the present application, there is provided a power module comprising a substrate and at least one semiconductor device as described in any of the embodiments of the present application, the substrate being configured to support the semiconductor device.

[0041] According to another aspect of the present application, there is provided a power conversion circuit configured to perform one or more of current conversion, voltage conversion, and power factor correction.

[0042] The power conversion circuit comprises a circuit board and at least one semiconductor device as described in any of the embodiments of the present application, the semiconductor device being electrically connected to the circuit board.

[0043] According to another aspect of the present application, there is provided a vehicle comprising a load and a power conversion circuit as described in any embodiment of the present application for converting AC power to DC power, AC power to AC power, DC power to DC power or DC power to AC power before inputting to the load.

[0044] The technical scheme provided by the embodiment of the present application integrates a Schottky barrier diode (SBD) in a semiconductor device, which can form the Schottky barrier diode while manufacturing the MOS device, simplifies the manufacturing process of the device, and can avoid the increase of the packaging cost and stray inductance of the device caused by the external parallel SBD, thereby preventing the degradation of the switching characteristics of the device; in addition, during reverse current conduction, the integrated Schottky diode is turned on before the body diode due to the smaller opening voltage of the Schottky diode than that of the PN junction diode, and the current flows through the Schottky junction, so that the energy loss of the device in the reverse current conduction state is greatly reduced.

[0045] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present application, nor to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0047] Figure 1 is a structure schematic diagram of a semiconductor device provided by the embodiment of the present application;

[0048] Figure 2 is a flowchart of a preparation method of a semiconductor device provided by the embodiment of the present application;

[0049] Figure 3 is a structure schematic diagram corresponding to step S110 in the preparation method of a semiconductor device provided by the embodiment of the present application;

[0050] Figure 4 is a structure schematic diagram corresponding to step S120 in the preparation method of a semiconductor device provided by the embodiment of the present application;

[0051] Figure 5Is the structure schematic diagram corresponding to step S210 in the preparation method of the semiconductor device provided by the embodiment of the application;

[0052] Figure 6 Is the structure schematic diagram corresponding to step S220 in the preparation method of the semiconductor device provided by the embodiment of the application;

[0053] Figure 7 Is the structure schematic diagram corresponding to step S230 in the preparation method of the semiconductor device provided by the embodiment of the application;

[0054] Figure 8 Is the structure schematic diagram corresponding to step S240 in the preparation method of the semiconductor device provided by the embodiment of the application;

[0055] Figure 9 Is the structure schematic diagram corresponding to step S250 in the preparation method of the semiconductor device provided by the embodiment of the application;

[0056] Figures 10-11 Is the structure schematic diagram corresponding to step S260 in the preparation method of the semiconductor device provided by the embodiment of the application;

[0057] Figures 12-13 Is the structure schematic diagram corresponding to step S270 in the preparation method of the semiconductor device provided by the embodiment of the application;

[0058] Figures 14-15 Is the structure schematic diagram corresponding to step S280 in the preparation method of the semiconductor device provided by the embodiment of the application;

[0059] Figure 16 Is the structure schematic diagram corresponding to step S2811 in the preparation method of the semiconductor device provided by the embodiment of the application;

[0060] Figure 17 Is the structure schematic diagram corresponding to step S2812 in the preparation method of the semiconductor device provided by the embodiment of the application;

[0061] Figure 18 Is the structure schematic diagram corresponding to step S2813 in the preparation method of the semiconductor device provided by the embodiment of the application;

[0062] Figure 19 Is the structure schematic diagram corresponding to step S2822 in the preparation method of the semiconductor device provided by the embodiment of the application;

[0063] Figure 20 Is the structure schematic diagram corresponding to step S2823 in the preparation method of the semiconductor device provided by the embodiment of the application;

[0064] Figure 21 is a structure schematic diagram corresponding to step S2824 in a preparation method of a semiconductor device provided by an embodiment of the present application;

[0065] Figure 22 is a structure schematic diagram corresponding to step S290 in a preparation method of a semiconductor device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0066] In order to make the personnel in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by the person of ordinary skill in the art without creative labor should belong to the scope of protection of the present application.

[0067] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not necessarily have to include those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to the process, method, product or device.

[0068] The embodiment of the present application also provides a semiconductor device, Figure 1 is a structure schematic diagram of a semiconductor device provided by an embodiment of the present application, referring to Figure 1 , the semiconductor device comprises:

[0069] The semiconductor body 1 comprises a first surface 11 and a second surface 12 arranged oppositely, the first surface 11 comprises a first region surface and a second region surface, and the first region surface is provided with a gate trench;

[0070] The trench gate structure 30 is located in the gate trench; wherein the semiconductor body 1 comprises a first contact region and a body region 21; the first contact region 22 comprises a first sub-contact region 222 and a second sub-contact region 221, the first sub-contact region 222 and the second sub-contact region 221 extend into the semiconductor body 1 from the first surface 11 respectively, the first sub-contact region 222 is arranged along the gate trench sidewall and is in contact with the trench gate structure 30; the second sub-contact region 221 is in contact with the first sub-contact region 222 and is located on the side of the first sub-contact region 222 away from the trench gate structure 30;

[0071] The body region 21 is located on the side of the first sub-contact region 222 away from the trench gate structure 30 and on the side of the second sub-contact region 221 close to the second surface 12; in the direction from the first surface 11 to the second surface 12, the length of the first sub-contact region 222 is greater than or equal to the thickness of the body region 21;

[0072] The first electrode is located on the first region surface of the semiconductor body 1 and is in contact with the second sub-contact region 221;

[0073] The contact metal layer 81 is located on the second region surface of the semiconductor body 1, and the contact metal layer 81 forms a Schottky contact with the second region surface of the semiconductor body 1.

[0074] The semiconductor device of the embodiment of the present application is a trench type and depletion mode semiconductor device, the depletion mode device is conductive in normal state, the current flows into through the second surface 12 of the semiconductor body 1, and flows to the first surface 11 of the semiconductor body 1 through the drift region 24 along the contact region (the first sub-contact region 222) of the sidewall of the trench gate structure 30. When the depletion mode device is switched to the cut-off state, a negative voltage needs to be applied to the trench gate structure 30 to make the device channel cut off, so that the depletion mode semiconductor device can respond faster and control the current flow, the conduction loss is small, and it is more suitable for high-frequency circuits and switching circuits.

[0075] In addition, the technical scheme provided by the embodiment of the present application integrates the Schottky diode 103 in the semiconductor device, compared with the diode used for reverse current continuation in parallel connection outside the semiconductor device, the Schottky diode 102 can be formed at the same time as the MOS device is prepared, the preparation process of the device is simplified, and the increase of the packaging cost and the stray inductance caused by the external parallel connection of the SBD can be avoided, so that the degradation of the switching characteristics of the device is prevented; in addition, during the reverse current continuation, since the opening voltage of the Schottky diode 103 is smaller than that of the PN junction diode, the integrated Schottky diode 103 is turned on earlier than the body diode 102, the current flows through the Schottky junction, and the energy loss of the device in the reverse current continuation state is greatly reduced.

[0076] Optionally, the semiconductor device further comprises: a gate electrode G located on the first region surface of the semiconductor body 1 and in contact with the trench gate structure 30; wherein the first electrode, the gate electrode G and the contact metal layer 81 are disposed in the same layer. The first electrode can be a source electrode S.

[0077] Optionally, the semiconductor body 1 further comprises a second contact region 23 located on the side of the first contact region 22 away from the trench gate structure 30 and on the side of the body region 21 away from the second surface 12; the second contact region 23 is of a different conductivity type from the first contact region 22; the first electrode is in contact with the second sub-contact region 221 and the second contact region 23.

[0078] Optionally, the first surface 11 further comprises a third region surface; the semiconductor body 1 further comprises a body diode 102, the second conductivity type region of the body diode 102 being located on the third region surface.

[0079] The embodiment of the present application also provides a preparation method of a semiconductor device, Figure 2 is a flowchart of the preparation method of the semiconductor device provided by the embodiment of the present application, referring to Figure 2 , the preparation method of the semiconductor device comprises:

[0080] S10, forming a semiconductor body; the semiconductor body comprises oppositely arranged first and second surfaces, and the first surface comprises a first region surface and a second region surface.

[0081] Specifically, the semiconductor body can be formed by one-time epitaxy or by multiple-time epitaxy. That is, the semiconductor body can be a semiconductor epitaxial layer or a stack structure formed by multiple semiconductor epitaxial layers. The semiconductor body can further comprise a substrate, that is, the semiconductor body comprises a substrate and at least one semiconductor epitaxial layer formed on one side of the substrate. The material of the substrate can be the same as that of the semiconductor epitaxial layer, or the material of the substrate can be different from that of the semiconductor epitaxial layer.

[0082] Referring to Figure 3 Optionally, the material of the semiconductor body 1 can be SiC, that is, the semiconductor device in the embodiment of the present application can be a trench-type SiC power device. The semiconductor body 1 comprises a substrate 10 and a semiconductor epitaxial layer 20 formed on one side of the substrate 10. SiC has excellent physical and electrical properties. Compared with silicon material, SiC material has a large band gap, high breakdown field, high thermal conductivity, high electron saturation rate, strong anti-radiation capability and other advantages, so that the semiconductor device prepared by using SiC material can not only operate stably at a higher temperature, but also is suitable for high-voltage and high-frequency scenarios.

[0083] The semiconductor body 1 comprises a first surface 11 and a second surface 12 oppositely arranged. In the case that the semiconductor body 1 only comprises a semiconductor epitaxial layer 20, the second surface 12 is the surface of the semiconductor body 1 close to the substrate 10, and the first surface 11 is the surface of the semiconductor body 1 far away from the substrate 10. In the case that the semiconductor body 1 comprises the substrate 10 and at least one semiconductor epitaxial layer 20, the second surface 12 is the surface of the substrate 10 far away from the semiconductor epitaxial layer 20, and the first surface 11 is the surface of the semiconductor epitaxial layer 20 far away from the substrate 10.

[0084] The first surface 11 comprises a first region surface Q1 and a second region surface Q2, which can be adjacent or spaced apart. It can be understood that the semiconductor body 1 comprises a first region and a second region, the first region surface Q1 is the first surface 11 of the semiconductor body 1 in the first region, and the second region surface Q2 is the first surface 11 of the semiconductor body 1 in the second region. The semiconductor body 1 in the first region is used to prepare a MOS device, and the semiconductor body 1 in the second region is used to form a Schottky diode.

[0085] S20, a gate trench is arranged on the first region surface, a trench gate structure is formed in the gate trench, and a first contact region and a body region are formed on at least one side of the trench gate structure; wherein the first contact region comprises a first sub-contact region and a second sub-contact region, the first sub-contact region and the second sub-contact region respectively extend from the first surface into the semiconductor body, the first sub-contact region is arranged along the side wall of the gate trench and contacts the trench gate structure; the second sub-contact region contacts the first sub-contact region and is located on the side of the first sub-contact region away from the trench gate structure; in the direction from the first surface to the second surface, the length of the first sub-contact region is greater than or equal to the thickness of the body region.

[0086] Specifically, referring to Figure 4The body region 21 can be formed by implanting ions of the second conductivity type into the surface of the semiconductor epitaxial layer after the semiconductor epitaxial layer is formed; the first contact region 22 is formed by implanting ions into the body region 21. The first contact region 22 includes a first sub-contact region 222 and a second sub-contact region 221. The first sub-contact region 222 is located on the first region surface of the semiconductor body 1 and the sidewall of the trench gate structure 30, and in the direction from the first surface 11 to the second surface 12, the length of the first sub-contact region 222 located on the sidewall of the trench gate structure 30 is greater than or equal to the thickness of the body region 21. The second sub-contact region 221 is located on the side of the first sub-contact region 222 away from the trench gate structure 30 and on the side of the body region 21 away from the second surface 12. The first sub-contact region 222 and the second sub-contact region 231 are of the same conductivity type. The first electrode is in contact with the second sub-contact region 221. Before the trench gate structure 30 is formed on the first region surface Q1 of the semiconductor body 1, a gate trench can be formed on the first region surface Q1 of the semiconductor body 1. The number of gate trenches corresponds to the number of trench gate structures 30. The gate trench can be etched from the first surface 11 of the semiconductor body 1 to form the first sub-contact region 222, the body region 21 and part of the drift region 24. Forming the trench gate structure 30 in the gate trench includes: forming a gate insulating layer 32 on the sidewall of the gate trench; and forming a polysilicon gate 31 on the surface of the gate insulating layer 32. The trench gate structure 30 includes the polysilicon gate 31 and the gate insulating layer 32 located between the polysilicon gate 31 and the gate trench 301. The material of the gate insulating layer 32 can include at least one of aluminum oxide and silicon oxide.

[0087] The trench gate structure 30 formed on the first region surface Q1 of the semiconductor body 1 can be one or multiple. That is, the semiconductor device of the embodiment of the present application includes at least one trench type SiC power device. At least one side of each trench gate structure 30 is provided with a first sub-contact region 222 and a body region 21, the first sub-contact region 222 is located on the first region surface Q1 of the semiconductor body 1 and the sidewall of the trench gate structure 30, and in the direction from the first surface 11 to the second surface 12, the length of the first sub-contact region 222 is greater than or equal to the thickness of the body region 21; that is, the semiconductor device of the embodiment of the present application is a depletion type device. The depletion type device is normally on, the current flows into the semiconductor body 1 through the second surface 12, and flows to the first surface 11 of the semiconductor body 1 (the first sub-contact region 222 located on the first surface 11) through the first sub-contact region 222 along the sidewall of the trench gate structure 30. When the depletion type device is switched to the off state, a negative voltage is applied to the trench gate structure 30 to make the device channel cut off, so the depletion type semiconductor device can respond faster and control the current flow, with small conduction loss, and is more suitable for high frequency circuits and switching circuits.

[0088] The first sub-contact region 222 has the same conductive type as the semiconductor body 1, and is doped with ions of the first conductive type, and the ion doping concentration of the first sub-contact region 222 is greater than the ion doping concentration of the semiconductor body 1. The body region 21 has a different conductive type from the semiconductor body 1, and is doped with ions of the second conductive type. The semiconductor epitaxial layer 20 between the body region 21 and the second surface 12 serves as a drift region 24. The ions of the first conductive type can be N-type doping ions, and the ions of the second conductive type are P-type doping ions; or, the ions of the first conductive type can be P-type doping ions, and the ions of the second conductive type are N-type doping ions. The N-type doping ions can be P (phosphorus) or N (nitrogen) ions, and the P-type doping ions can be Al (aluminum) ions or B (boron) ions. In the embodiment of the present application, the ions of the first conductive type are N-type doping ions, and the ions of the second conductive type are P-type doping ions.

[0089] S30, forming a contact metal layer on the second region surface of the semiconductor body; the contact metal layer forms a Schottky contact with the second region surface of the semiconductor body, and a first electrode is formed on the first region surface of the semiconductor body and contacts the second sub-contact region.

[0090] Specifically, the Schottky diode is a low-power, large-current, super-speed semiconductor device made by using the principle of metal-semiconductor contact formed by metal and semiconductor. The Schottky diode generally includes a cathode metal layer, a first conductive type substrate, a first conductive type epitaxial layer, a barrier metal or metal silicide, and an anode metal layer; the barrier metal or metal silicide and the first conductive type epitaxial layer form a Schottky contact. Figure 1 In the embodiment of the present application, the semiconductor body 1 is a first conductive type semiconductor layer, and only ions of the first conductive type are doped in the semiconductor body 1 located in the second region. At least the part of the contact metal layer 81 adjacent to the semiconductor body 1 is a barrier metal or metal silicide. The contact metal layer 81 is formed on the second region surface Q2 of the semiconductor body 1, and the contact metal layer 81 is annealed, so that the contact metal layer 81 forms a Schottky contact with the second region surface Q2 of the semiconductor body 1, thereby forming a Schottky diode 103. The first electrode can be a source electrode S.

[0091] Optionally, the contact metal layer 81 includes a barrier metal or metal silicide, and further includes an anode metal layer of the Schottky diode 103.

[0092] Optionally, please continue to refer to Figure 1Meanwhile, the semiconductor device also comprises: forming a first electrode in contact with the second contact sub-region 221 on the first region surface Q1 of the semiconductor body 1, and forming a gate electrode G in contact with the gate structure, so that the preparation process of the semiconductor device can be simplified.

[0093] For example, the first electrode, the gate electrode G and the contact metal layer 81 can be simultaneously prepared by sequentially depositing a Ti layer, a TiN layer and an Al layer, and then performing a metal etching treatment. The semiconductor body 1 is also provided with a second electrode away from the first surface 11. The first electrode can be a source electrode S, and the second electrode can be a drain electrode D; or the first electrode can be a drain electrode D, and the second electrode can be a source electrode S. Figure 1 For example, the first electrode is a source electrode S, and the second electrode is a drain electrode D. The cathode metal layer of the Schottky diode 103 can be electrically connected to or shared with the second electrode, and the anode metal layer of the Schottky diode 103 can be electrically connected to or shared with the first electrode.

[0094] The technical scheme provided by the embodiment of the present application can integrate a Schottky barrier diode in a semiconductor device, form a Schottky barrier diode while preparing a depletion mode MOS device, simplify the preparation process of the semiconductor device, and avoid the problems of increasing packaging cost and stray inductance caused by externally connecting an SBD, thereby preventing the degradation of the switching characteristics of the device. In addition, during reverse current conduction, the Schottky diode 103 is turned on before the body diode 102 because the opening voltage of the Schottky diode 103 is smaller than that of the PN junction diode, and the current flows through the Schottky junction, so that the energy loss of the device in the reverse current conduction state is greatly reduced.

[0095] On the basis of the above-mentioned embodiments, step S20 forms a trench gate structure on the first region surface of the semiconductor body, and forms a first contact region and a body region on at least one side of the trench gate structure, comprising:

[0096] S210, forming a first mask layer on the first surface of the semiconductor body, and patterning the first mask layer to form a first opening exposing the first region surface in the first mask layer.

[0097] Specifically, referring to Figure 5The first mask layer 100 can be formed by PECVD (Plasma Enhanced Chemical Vapor Deposition) and then patterned by photolithography. The photolithography is an important step in the process of manufacturing semiconductor devices. In the step, a geometric pattern is drawn on a photoresist layer by exposure and development, and then the pattern is transferred to the first mask layer 100 by etching, so as to pattern the first mask layer 100. The first opening 01 on the first surface Q1 can expose the whole first surface Q1.

[0098] S220, implanting ions of the second conductive type into the first surface of the semiconductor body based on the patterned first mask layer, to form an initial body region.

[0099] Specifically, referring to Figure 6 The initial body region 211 on the first surface Q1 of the semiconductor body 1 is a film layer formed in the process of manufacturing the semiconductor device, and the body region 21 is formed on the basis of the initial body region 211. In the embodiment of the present application, the initial body region 211 is a doped region formed by implanting ions of the second conductive type into the surface of the semiconductor epitaxial layer 20 after forming the semiconductor epitaxial layer 20. Compared with the way of doping the epitaxial material with ions of the second conductive type in the epitaxial process, the embodiment of the present application can make the semiconductor epitaxial layer 20 used for preparing the initial body region 211 and the semiconductor epitaxial layer 20 used for preparing the Schottky diode 103 formed in the same epitaxial process, so as to simplify the process of manufacturing the semiconductor device.

[0100] S230, removing the first mask layer, forming a second mask layer on the first surface of the semiconductor body, and patterning the second mask layer to form at least one second opening exposing the initial body region in the second mask layer; the width of the second opening is smaller than the width of the first opening.

[0101] Specifically, referring to Figure 7The first mask layer 100 of the silicon dioxide material can be corroded by a hydrofluoric acid solution, and then a second mask layer 200 of SiO2 is deposited by a PECVD process, and the second mask layer 200 is patterned by a photolithography process to form at least one second opening 02 exposing the initial body region 211. The width of the second opening 02 is smaller than the width of the first opening 01. The position of the second opening 02 corresponds to the position of the first sub-region a1 of the first conductivity type formed in step S240. When one trench gate structure 30 is formed in the first region of the semiconductor body 1, one or two second openings 02 can be formed. When multiple trench gate structures 30 are formed in the first region of the semiconductor body 1, at least as many second openings 02 as the number of trench gate structures 30 are formed. The second openings 02 are arranged at intervals.

[0102] S240, based on the patterned second mask layer, implanting ions of the first conductivity type into the initial body region to form at least one first sub-region on the surface of the initial body region away from the second surface.

[0103] Specifically, referring to Figure 8 , based on the patterned second mask layer 200, implanting ions of the first conductivity type into the initial body region 211 to form at least one first sub-region a1 of the first conductivity type on the surface of the initial body region 211 away from the second surface 12. The thickness of the first sub-region a1 is smaller than the thickness of the initial body region 211.

[0104] S250, removing the second mask layer, forming a third mask layer on the first surface of the semiconductor body, and patterning the third mask layer to form third openings exposing the predetermined positions of the trench gate structures in the third mask layer.

[0105] Specifically, referring to Figure 9 , the second mask layer 200 of the silicon dioxide material can be corroded by a hydrofluoric acid solution, and then a third mask layer 300 of SiO2 is deposited by a PECVD process, and the third mask layer 300 is patterned by a photolithography process to form at least one third opening 03. The third opening 03 exposes the predetermined position of the trench gate structure 30, and the number of the third opening 03 is the same as the number of the trench gate structure 30. The third opening 03 exposes the initial body region 211 and the region adjacent to the initial body region 211 and the first sub-region a1. Figure 9 An exemplary third opening 03 exposes the initial body region 211 between two adjacent first sub-regions a1 and part of the region of the two adjacent first sub-regions a1.

[0106] S260, forming a spacer layer on the sidewall of the third opening adjacent to the first sub-region to form a fourth opening in the third mask layer, the width of the fourth opening being less than the width of the third opening; wherein the width of the fourth opening is greater than or equal to the width of the initial body region exposed by the third opening.

[0107] Specifically, referring to Figure 10 and Figure 11 The SiN material can be deposited to form a spacer layer 40 on the surface of the third mask layer 300 away from the semiconductor body 1, the sidewall of the third opening 03 and the first surface 11 of the semiconductor body 1 exposed by the third opening 03; and then the spacer layer 40 on the surface of the third mask layer 300 away from the semiconductor body 1 and the spacer layer 40 on the first surface 11 of the semiconductor body 1 exposed by the third opening 03 are removed by the dry etching process, so as to form the spacer layer 40 on the sidewall of the third opening 03. In the embodiment of the present application, the third opening 03 has first sub-regions a1 on opposite sides, so the spacer layer 40 on the opposite sides of the third opening 03 can be reserved.

[0108] S270, forming a gate trench on the first region surface exposed by the fourth opening, and forming a first barrier layer in the gate trench.

[0109] Specifically, referring to Figure 12 and Figure 13 The gate trench 301 is formed on the first region surface Q1 exposed by the fourth opening 04, and the first barrier layer 51 is formed in the gate trench 301. The width of the fourth opening 04 is greater than or equal to the width of the initial body region 211 between the adjacent two first sub-regions 221 of the first conductive type, so that the sidewall of the gate trench 301 formed by etching the semiconductor body 1 based on the fourth opening 04 is in contact with the first sub-region 221 of the first conductive type.

[0110] S280, removing the spacer layer on the sidewall of the third opening, implanting ions of the first conductive type on the exposed first region surface to form a first sub-contact region; wherein the first sub-region reserved after the formation of the first sub-contact region serves as a second sub-contact region, and the initial body region without the implantation of the ions of the first conductive type serves as a body region.

[0111] Specifically, referring to Figure 14 and Figure 15The spacer layer 40 on the sidewall of the third opening 03 is removed, and the initial body region 211 under the spacer layer 40 is implanted with ions of the first conductive type to form the first sub-contact region 222. The material of the spacer layer 40 is different from the material of the third mask layer 300 and the material of the first barrier layer 51. Thus, the spacer layer 40 can be removed without damaging the third mask layer 300 and the first barrier layer 51. Optionally, the material of the spacer layer 40 can be SiN, and the material of the first barrier layer 51 can be polysilicon. The spacer layer 40 on the sidewall of the third opening 03 can be removed by a phosphoric acid solution.

[0112] After the spacer layer 40 on the sidewall of the third opening 03 is removed, part of the first sub-region 221 under the spacer layer 40 is exposed, and the first sub-contact region 222 is formed along the sidewall of the gate trench 301 by implanting ions of the first conductive type again, so that the preparation of the first sub-contact region 222 is completed. The first sub-region a1 retained after the first sub-contact region 222 is formed serves as the second sub-contact region 221. The first barrier layer 51 is used to block the implantation of the ions of the first conductive type into the bottom of the gate trench 301 when the first sub-contact region 222 is formed. The initial body region 211 which is not implanted with the ions of the first conductive type forms the body region 21. The ion doping concentration in the first sub-contact region 222 is greater than the ion doping concentration in the second sub-contact region 221.

[0113] S290, removing the first barrier layer to form a trench gate structure in the gate trench.

[0114] Specifically, the first barrier layer 51 can be removed by a nitric acid solution, so that the sidewall and the bottom of the gate trench 301 are exposed to form the trench gate structure 30 in the gate trench 301.

[0115] On the basis of the above embodiments, the semiconductor device further comprises a second contact region located on the side of the first contact region away from the trench gate structure and on the side of the body region away from the second surface. The method for manufacturing the semiconductor device further comprises: forming the second contact region on at least one side of the trench gate structure; and the second contact region is located on the side of the first contact region away from the trench gate structure and on the side of the body region away from the second surface.

[0116] On the basis of the above embodiments, in one embodiment of the present application, the second contact region is formed on at least one side of the trench gate structure 30, comprising:

[0117] After the first sub-contact region 222 is formed in step S280, the method further comprises:

[0118] S2811, removing the third mask layer 300 and forming a second barrier layer 52 on the surface of the first barrier layer 51 and the first surface 11 of the semiconductor body 1. (Referring to Figure 16)

[0119] S2812, patterning the second blocking layer 52 to form an opening 521 exposing the second contact region 23 at the preset position in the second blocking layer 52. (Refer to Figure 17 )

[0120] S2813, based on the patterned second blocking layer 52, implanting ions of the second conductivity type into the second contact region 23 at the preset position to form the second contact region 23. (Refer to Figure 18 )

[0121] The second contact region 23 is doped with ions of the second conductivity type, and the ion doping concentration in the second contact region 23 is greater than the ion doping concentration of the body region 21.

[0122] Before forming the trench gate structure 30 in the gate trench 301, it further includes: removing the second blocking layer 52. That is, the second blocking layer 52 and the first blocking layer 51 need to be removed before forming the trench gate structure 30 in the gate trench 301. The materials of the first blocking layer 51 and the second blocking layer 52 can be the same, so that they can be removed in the same removal process, thereby simplifying the preparation process of the semiconductor device.

[0123] On the basis of the above-mentioned embodiments, in another embodiment of the present application, the second contact region is formed on at least one side of the trench gate structure, comprising:

[0124] After forming the first sub-contact region 222 in step S280, it includes:

[0125] S2821, removing the third mask layer 300 and removing the first blocking layer 51.

[0126] S2822, forming an etching stop layer 60 on the groove wall of the gate trench 301 and the first surface 11 of the semiconductor body 1, and forming a third blocking layer 53 with a thickness greater than that of the etching stop layer 60 on the surface of the etching stop layer 60. (Refer to Figure 19 )

[0127] Specifically, the etching stop layer 60 can prevent damage to the surface of the semiconductor body 1 during the patterning of the third blocking layer 53 in step S2823. The etching stop layer 60 is set to have a thickness less than that of the third blocking layer 53, which can reduce the impact on the implantation of ions of the second conductivity type in step S2824. The material of the etching stop layer 60 can be silicon dioxide, and the material of the third blocking layer 53 can be polysilicon.

[0128] S2823, patterning the third blocking layer 53 to form an opening 531 exposing the etching stop layer at the second sub-contact region 23 at the preset position in the third blocking layer 53. (Refer to Figure 20 )

[0129] S2824, based on the third blocking layer 53, the second contact region 23 is preset position for the second conductive type ion implantation, forming the second contact region 23. (Reference Figure 21 )

[0130] Before forming the trench gate structure 30 in the gate trench 301, it also includes: removing the third blocking layer 53 and the etching stop layer 60.

[0131] On the basis of the above embodiments, the step S290 of forming the trench gate structure 30 in the gate trench 301, comprising:

[0132] S2910, forming the gate insulating layer 32 on the groove wall of the gate trench 301.

[0133] S2920, forming the gate insulating layer 32 on the groove wall of the gate trench 301.

[0134] Specifically, reference Figure 22 , the gate insulating layer 32 can be formed on the side wall and bottom of the gate trench 301 and the first surface 11 of the semiconductor body 1 by thermal oxidation process. Depositing doped Poly polysilicon, and then etching back, filling Poly-Si in the gate trench, forming a polysilicon gate 31, so as to complete the preparation of the trench gate structure 30.

[0135] Further, before forming the trench gate structure 30 in the gate trench 301 in step S290, it also includes: sputtering a layer of carbon film on the first surface 11 of the semiconductor body 1 and the groove wall of the gate trench 301, annealing in the annealing furnace, and then removing the carbon film. Specifically, since ion implantation will produce some lattice defects in the semiconductor, low temperature annealing or laser annealing can be used to eliminate these defects after ion implantation.

[0136] Further, after removing the carbon film, it also includes: forming a sacrificial oxide layer on the first surface 11 of the semiconductor body 1 and the groove wall surface of the gate trench 301 by thermal oxidation process, so as to repair the lattice of the surface of the semiconductor body 1; and then removing the sacrificial oxide layer.

[0137] On the basis of the above embodiments, optionally, the first surface 11 further includes a third region surface Q3, and the step S220 of forming the initial body region 211 also includes: implanting the second conductive type ions on the third region surface Q3 to form the second conductive type region 1021 of the body diode 102. (Reference Figure 6 )

[0138] In step S2813 and step S2824, while forming the second contact region 23, the method also includes: implanting second conductivity type ions again into the second conductivity type region of the body diode 102 to increase the ion doping concentration on the surface of the second conductivity type region 1021 of the body diode 102. (Reference) Figure 18 and Figure 21 )

[0139] Based on the above embodiments, optionally, refer to... Figure 1 Before forming a gate electrode that contacts the gate structure and a first electrode that contacts the second sub-contact region 221 on the surface Q1 of the first region of the semiconductor body 1, the method further includes: forming a passivation layer 70 on the surface Q1 of the first region of the semiconductor body 1, and forming a first electrode connection port that exposes the second sub-contact region 221 and a gate connection port that exposes the trench gate structure 3 in the passivation layer 70.

[0140] The first electrode is also in contact with the second contact area 23.

[0141] This invention also provides a power module, including a substrate and at least one semiconductor device as described in any embodiment of this invention, wherein the substrate is used to support the semiconductor device. It has the same technical effects and will not be described again here.

[0142] This invention also provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of this invention, and the semiconductor device is electrically connected to the circuit board. It has the same technical effects and will not be described again here.

[0143] This invention also provides a vehicle, including a load and a power conversion circuit as described in any embodiment of the invention. The power conversion circuit is used to convert AC power to DC power, AC power to AC power, DC power to DC power, or DC power to AC power and then input it to the load. It has the same technical effects and will not be described again here.

[0144] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized by, The semiconductor body comprises a first surface and a second surface arranged oppositely, the first surface comprises a first region surface and a second region surface, and the first region surface is provided with a gate trench; The trench gate structure is located in the gate trench; The semiconductor body comprises a first contact region and a body region; the first contact region comprises a first sub-contact region and a second sub-contact region, the first sub-contact region and the second sub-contact region respectively extend from the first surface into the semiconductor body, the first sub-contact region is arranged along the sidewall of the gate trench and is in contact with the trench gate structure; the second sub-contact region is in contact with the first sub-contact region and is located on the side of the first sub-contact region away from the trench gate structure; the length of the first sub-contact region is greater than or equal to the thickness of the body region in the direction from the first surface to the second surface; The first electrode is located on the first region surface of the semiconductor body and is in contact with the second sub-contact region; The contact metal layer is located on the second region surface of the semiconductor body, and the contact metal layer forms a Schottky contact with the second region surface of the semiconductor body. Further comprising: The gate electrode is located on the first region surface of the semiconductor body and is in contact with the trench gate structure; 2. The semiconductor device according to claim 1, wherein The first electrode, the gate electrode and the contact metal layer are arranged in the same layer. The semiconductor body further comprises: The second contact region is located on the side of the first contact region away from the trench gate structure and on the side of the body region away from the second surface; the second contact region is different from the first contact region in conductivity type; 3. The semiconductor device of claim 2, wherein, The first electrode is in contact with the second sub-contact region and the second contact region. The first surface further comprises a third region surface; The semiconductor body further comprises a body diode, and the second conductivity type region of the body diode is located on the third region surface.

4. The semiconductor device of claim 1, wherein The semiconductor body comprises a first surface and a second surface arranged oppositely, the first surface comprises a first region surface and a second region surface, and the first region surface is provided with a gate trench; The trench gate structure is located in the gate trench, and the first contact region and the body region are formed on at least one side of the trench gate structure; wherein the first contact region comprises a first sub-contact region and a second sub-contact region, the first sub-contact region and the second sub-contact region respectively extend from the first surface into the semiconductor body, the first sub-contact region is arranged along the sidewall of the gate trench and is in contact with the trench gate structure; the second sub-contact region is in contact with the first sub-contact region and is located on the side of the first sub-contact region away from the trench gate structure; the length of the first sub-contact region is greater than or equal to the thickness of the body region in the direction from the first surface to the second surface; 5. A method of manufacturing a semiconductor device, characterized by, The contact metal layer is formed on the second region surface of the semiconductor body; the contact metal layer forms a Schottky contact with the second region surface of the semiconductor body. ​ ​ ​ A first electrode is formed in contact with the second sub-contact region on the first region surface of the semiconductor body.

6. The method of producing a semiconductor device according to claim 5, wherein Further comprising: A gate electrode is formed in contact with the trench gate structure.

7. The method of producing a semiconductor device according to claim 5, wherein A trench gate structure is formed in the gate trench, and a first contact region and a body region are formed on at least one side of the trench gate structure, comprising: A first mask layer is formed on the first surface of the semiconductor body, and the first mask layer is patterned to form a first opening in the first mask layer to expose the first region surface; Based on the patterned first mask layer, ions of the second conductive type are implanted into the first region surface of the semiconductor body to form an initial body region; The first mask layer is removed, a second mask layer is formed on the first surface of the semiconductor body, and the second mask layer is patterned to form at least one second opening in the second mask layer to expose the initial body region; the width of the second opening is smaller than the width of the first opening; Based on the patterned second mask layer, ions of the first conductive type are implanted into the initial body region to form at least one first sub-region on the surface of the initial body region away from the second surface; The second mask layer is removed, a third mask layer is formed on the first surface of the semiconductor body, and the third mask layer is patterned to form a third opening in the third mask layer to expose a predetermined position of the trench gate structure; wherein the third opening exposes the initial body region and a region adjacent to the first sub-region and the initial body region; A spacer layer is formed on the sidewall of the third opening adjacent to the first sub-region to form a fourth opening in the third mask layer with a width smaller than the third opening; wherein the width of the fourth opening is greater than or equal to the width of the initial body region exposed by the third opening; A gate trench is formed on the first region surface exposed by the fourth opening, and a first barrier layer is formed in the gate trench; The spacer layer located on the sidewall of the third opening is removed, and ions of the first conductive type are implanted into the exposed first region surface to form a first sub-contact region; wherein the first sub-region remaining after the formation of the first sub-contact region serves as a second sub-contact region, and the initial body region without the implantation of ions of the first conductive type serves as the body region; The first barrier layer is removed, and a trench gate structure is formed in the gate trench.

8. The method of producing a semiconductor device according to Claim 7, wherein The semiconductor body further comprises a second contact region; and the method for manufacturing a semiconductor device further comprises: A second contact region is formed on at least one side of the trench gate structure; the second contact region is located on the side of the first contact region away from the trench gate structure, and on the side of the body region away from the second surface.

9. The method of producing a semiconductor device according to Claim 8, wherein A second contact region is formed on at least one side of the trench gate structure, comprising: A second barrier layer is formed on the surface of the first barrier layer and the first surface of the semiconductor body; The second barrier layer is patterned to form an opening in the second barrier layer to expose a predetermined position of the second contact region; Based on the patterned second barrier layer, ions of the second conductive type are implanted into the predetermined position of the second contact region to form a second contact region; The second barrier layer is removed.

10. The method of producing a semiconductor device according to Claim 8, wherein forming a second contact region on at least one side of the trench gate structure, comprising: after forming the first sub-contact region, removing the third mask layer and removing the first barrier layer; forming an etching stop layer on the sidewall of the gate trench and the first surface of the semiconductor body; forming a third barrier layer on the surface of the etching stop layer, the thickness of the third barrier layer being greater than the thickness of the etching stop layer; patterning the third barrier layer to form an opening in the third barrier layer that exposes the etching stop layer at a predetermined position of the second contact region; based on the patterned third barrier layer, implanting ions of the second conductivity type into the predetermined position of the second contact region to form the second contact region; before forming the trench gate structure in the gate trench, further comprising: removing the third barrier layer and the etching stop layer.

11. The method of producing a semiconductor device according to claim 9 or 10, wherein forming the trench gate structure in the gate trench, comprising: forming a gate insulating layer on the sidewall of the gate trench; forming a polysilicon gate on the surface of the gate insulating layer.

12. The method of producing a semiconductor device according to claim 9 or 10, wherein the first surface further comprises a third region surface, and forming the initial body region further comprises: implanting ions of the second conductivity type into the third region surface to form a second conductivity type region of a body diode; forming the second sub-contact region further comprises: implanting ions of the second conductivity type into the second conductivity type region of the body diode again to increase the ion doping concentration on the surface of the second conductivity type region of the body diode.

13. The method of producing a semiconductor device according to Claim 6, wherein before forming the gate electrode that contacts the trench gate structure and the first electrode that contacts the second sub-contact region on the first region surface of the semiconductor body, further comprising: forming a passivation layer on the first region surface of the semiconductor body, and forming a first electrode connection port that exposes the second sub-contact region and a gate connection port that exposes the trench gate structure in the passivation layer.

14. A power module, characterized by a substrate for carrying the semiconductor device.

15. A power conversion circuit, characterized by the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit comprises a circuit board and at least one semiconductor device as claimed in any one of claims 1 to 4, the semiconductor device being electrically connected to the circuit board.

16. A vehicle characterized by comprising: a load and the power conversion circuit as claimed in claim 15, the power conversion circuit being used for converting alternating current into direct current, converting alternating current into alternating current, converting direct current into direct current, or converting direct current into alternating current before inputting to the load.

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