JFET device structure and forming method thereof

Abstract

The invention discloses a JFET device structure and a forming method thereof. The device comprises a substrate; the bottom doped region is positioned in the substrate; the drift region is positioned in the substrate and is adjacent to the upper part of the bottom doped region; the first doped regions are located in the drift region, penetrate through the drift region in the direction perpendicular to the substrate and are connected with the bottom doped region, the conduction type of the first doped regions is opposite to that of the drift region, and the distance between every two adjacent first doped regions is determined based on pinch-off voltage of the JFET device structure; and the second doped region is positioned above the bottom doped region and around the drift region, the second doped region is respectively contacted with the drift region and the bottom doped region, and the conduction types of the second doped region, the first doped region and the bottom doped region are the same. Therefore, JFET devices with various pinch-off voltages and excellent performance can be designed and prepared on the same platform without adjusting a process formula.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a JFET device structure and a forming method thereof. Background Art

[0002] In the current process of preparing Junction Field-Effect Transistor (JFET) based on BCD (Bipolar-CMOS-DMOS) platform, in order to consider factors such as process stability, the process recipe under the same platform is usually not changed after it is determined, and the corresponding various types of ion implantation process concentrations and depths are fixed. Therefore, using the existing vertical depletion JFET device structure, it is difficult to prepare JFET devices with multiple pinch-off voltages through the ion implantation process combination of the same platform while ensuring that JFET devices with various pinch-off voltages can achieve good depletion pinch-off, resulting in the deterioration of JFET devices. Summary of the invention

[0003] The technical problem solved by the present invention is to provide a JFET device structure and a method for forming the same, so as to design and prepare a JFET device with excellent performance and good pinch-off voltage diversity on the same platform.

[0004] In order to solve the above technical problems, the technical solution of the present invention provides a JFET device structure, including: a substrate; a bottom doped region, located in the substrate; a drift region, located in the substrate and adjacent to the bottom doped region; a plurality of independent first doped regions, the first doped region is located in the drift region, and penetrates the drift region in a direction perpendicular to the substrate and connects to the bottom doped region, the conductivity type of the first doped region is opposite to the conductivity type of the drift region, and the spacing between two adjacent first doped regions is determined based on the pinch-off voltage of the JFET device structure; a second doped region, located above the bottom doped region and around the drift region, and the second doped region is in contact with the drift region and the bottom doped region respectively, and the second doped region, the first doped region and the bottom doped region have the same conductivity type.

[0005] Optionally, a plurality of the first doped regions are evenly spaced and arranged along a designated path, and the designated path is a ring path; and the second doped regions surround the drift region.

[0006] Optionally, the annular path includes an arcuate path segment, a first doped region on the arcuate path segment has a first doped region projection on the substrate surface, the two ends of the first doped region projection along the radial direction of the arcuate path segment are respectively a first end and a second end, the second end is located between the first end and the second doped region, and the minimum spacing between adjacent first ends is smaller than the spacing between adjacent second ends.

[0007] Optionally, the projection of the first doped region is a trapezoid, and parallel opposite sides of the trapezoid are perpendicular to the radial direction of the arc-shaped path segment.

[0008] Optionally, it also includes: a top isolation structure located on the top surface of the first doped region; a source region and a drain region located in the drift region and respectively located on both sides of the top isolation structure, wherein the source region is located between the first doped region and the second doped region.

[0009] Optionally, it also includes: a second contact region, located on the second doped region, the conductivity type of the second contact region is the same as that of the second doped region, and the conductive ion doping concentration of the second contact region is higher than the conductive ion doping concentration of the second doped region; a first isolation structure, located between the second contact region and the source region, and between a portion of the drift region under the source region and a portion of the second doped region under the second contact region, and the height of the first isolation structure is less than the depth of the second doped region, and the second doped region is in contact with the drift region below the first isolation structure.

[0010] Optionally, it also includes: a third doped region, surrounding the second doped region and independent of the second doped region, the third doped region and the second doped region having a conductivity type opposite to that of the second doped region; a buried layer, located below the bottom doped region and the third doped region, the bottom of the bottom doped region and the bottom of the third doped region are respectively connected to the buried layer, and the buried layer and the third doped region have the same conductivity type.

[0011] Optionally, it also includes: a third contact region, located on the third doped region, the conductivity type of the third contact region is the same as that of the third doped region, and the conductive ion doping concentration of the third contact region is higher than the conductive ion doping concentration of the third doped region; a second isolation structure, located between the second contact region and the third contact region, and between a portion of the second doped region under the second contact region and a portion of the third doped region under the third contact region.

[0012] Optionally, it also includes: a fourth doping region, located in the substrate and surrounding the third doping region, the fourth doping region having the same conductivity type as the second doping region; a fourth contact region, located on the fourth doping region, the fourth contact region having the same conductivity type as the fourth doping region, and a conductive ion doping concentration of the fourth contact region being higher than that of the fourth doping region; a third isolation structure, located between the third contact region and the fourth contact region, and between a portion of the third doping region under the third contact region and a portion of the fourth doping region under the fourth contact region.

[0013] Correspondingly, the technical solution of the present invention also provides a method for forming the above-mentioned JFET device structure.

[0014] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0015] In the JFET device structure and the formation method thereof provided by the technical solution of the present invention, a plurality of first doped regions which are inversely related to the drift region and independent of each other are provided in the drift region, and the first doped regions penetrate the drift region to connect to the bottom doped region of the same type as the first doped regions. Meanwhile, the second doped regions are located above the bottom doped regions and around the drift region, and are respectively connected to the drift region which is inversely related to the first doped regions and the bottom doped regions of the same type as the first doped regions. Therefore, by adjusting the spacing between two adjacent first doped regions, the depletion region width of the JFET device can be adjusted, that is, the pinch-off voltage of the JFET device can be adjusted. Thus, JFET devices with various pinch-off voltages of excellent performance can be designed and prepared on the same platform without adjusting the process recipe. Especially in the fields of medium and low voltage consumer electronics, automotive electronics, etc., the introduction of high-performance JFET devices can bring more efficient and reliable working performance to the circuit, and bring greater economic benefits. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic cross-sectional structure diagram of a vertically depleted JFET device structure;

[0017] Figure 2 is a schematic diagram of a top view of a JFET device structure in one embodiment of the present invention;

[0018] Figure 3 yes Figure 2 A schematic diagram of the cross-sectional structure along the direction A1-A2;

[0019] Figure 4 and Figure 5 Schematic diagram of the depletion region of a JFET device structure in one embodiment of the present invention.

[0020] Description of reference numerals:

[0021] 100-P type substrate; 110-P type bottom doping region; 120-N type drift region; 130-P type heavily doped region;

[0022] 200-substrate; 210-buried layer; 220-bottom doped region; 230-drift region; 240-first doped region; 241-projection of first doped region; 241a-first end; 241b-second end; 250-second doped region; 261-source region; 262-drain region; 270-third doped region; 280-fourth doped region; 292-second contact region; 293-third contact region; 294-fourth contact region; 300-top isolation structure; 310-first isolation structure; 320-second isolation structure; 330-third isolation structure; 340-device isolation structure. DETAILED DESCRIPTION

[0023] As described in the background art, it is difficult to use the existing vertical depletion JFET device structure to prepare JFET devices with various pinch-off voltages through the ion implantation process combination of the same platform while ensuring that JFET devices with various pinch-off voltages can achieve good depletion pinch-off, resulting in the deterioration of the JFET device. Figure 1 Provide explanation.

[0024] Figure 1 It is a schematic diagram of the cross-sectional structure of a vertically depleted JFET device structure.

[0025] Please refer to Figure 1 The JFET device structure includes: a P-type substrate 100. A P-type bottom doped region 110, an N-type drift region 120, and a P-type heavily doped region 130 are distributed in the P-type substrate 100. In the direction perpendicular to the surface of the P-type substrate 100, the P-type bottom doped region 110 and the P-type heavily doped region 130 are respectively on both sides of the N-type drift region 120.

[0026] In the JFET device structure, the P-type bottom doped region 110 and the P-type heavily doped region 130 respectively form depletion regions with the N-type drift region 120 , and the two depletion regions are connected to achieve vertical pinch-off.

[0027] However, on the same BCD platform, various types of ion implantation processes are fixed, and it is difficult to adjust the doping concentration of the P-type bottom doping region 110 and the P-type heavily doped region 130 and the spacing between the P-type bottom doping region 110 and the P-type heavily doped region 130 to meet various different pinch-off voltages. Forcibly forming longitudinally depleted JFET device structures with different pinch-off voltages on the same BCD platform will result in each longitudinally depleted JFET device structure being unable to be well depleted and pinched off, causing the JFET device to deteriorate.

[0028] In order to solve the above technical problems, the technical solution of the present invention provides a FET device structure and a method for forming the same, by forming a plurality of first doping regions in the drift region that are inversely related to the drift region and independent of each other, and a second doping region located above the bottom doping region and around the drift region, and the first doping region runs through the drift region and connects to the bottom doping region of the same type as the first doping region, and the second doping region is respectively connected to the drift region of the inversely related to the second doping region and the bottom doping region of the same type as the second doping region, so that by adjusting the spacing between two adjacent first doping regions, the depletion region width required for the pinch-off of the JFET device can be correspondingly adjusted, that is, the pinch-off voltage of the JFET device can be adjusted. Therefore, JFET devices with various pinch-off voltages of excellent performance can be designed and prepared on the same platform without adjusting the process recipe, especially in the fields of medium and low voltage consumer electronics, automotive electronics, etc., the introduction of high-performance JFET devices can bring more efficient and reliable working performance to the circuit, and bring greater economic benefits.

[0029] In order to make the above-mentioned purposes, features and beneficial effects of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. In addition, directional terms such as above, below, up, down, upward, downward, left, right, etc. are used relative to the exemplary embodiments as they are shown in the figures, with the upward or upper direction toward the top of the corresponding figure, and the downward or lower direction toward the bottom of the corresponding figure.

[0031] Figure 2 is a schematic diagram of a top view of a JFET device structure in one embodiment of the present invention, Figure 3 yes Figure 2 Schematic diagram of the cross-sectional structure along the direction A1-A2.

[0032] Please refer to Figure 2 and Figure 3 The JFET device structure includes: a substrate 200 , a bottom doped region 220 , a drift region 230 , a plurality of first doped regions 240 , and a second doped region 250 .

[0033] The bottom doped region 220 and the drift region 230 are both located in the substrate 200 , and the drift region 230 is adjacent to and above the bottom doped region 220 .

[0034] The first doping regions 240 are located in the drift region 230 , and are independent of each other. In a direction perpendicular to the surface of the substrate 200 , the first doping regions 240 penetrate the drift region 230 , and the bottom of the first doping regions 240 is connected to the bottom doping region 220 .

[0035] The second doping region 250 is located above the bottom doping region 220 and around the drift region 230 , and the second doping region 250 is in contact with the drift region 230 and the bottom doping region 220 , respectively.

[0036] The bottom doped region 220 , the first doped region 240 and the second doped region 250 have the same conductivity type, the conductivity type of the first doped region 240 is opposite to the conductivity type of the drift region 230 , and the spacing between two adjacent first doped regions 240 is determined based on the pinch-off voltage Vp of the JFET device structure.

[0037] Since the drift region 230 has a plurality of first doping regions 240 that are inversely type (opposite to the conductive type) and independent of the drift region 230, and the first doping region 240 penetrates the drift region 230 and is connected to the bottom doping region 220 of the same type (same conductive type), and the second doping region 250 is located above the bottom doping region 220 and around the drift region, and is respectively connected to the drift region 230 of the inverse type and the bottom doping region 220 of the same type, therefore, by adjusting the spacing between two adjacent first doping regions 240, the depletion region width of the JFET device can be adjusted, that is, the pinch-off voltage Vp of the JFET device can be adjusted. Therefore, by determining the pinch-off voltage Vp of the JFET device structure through the spacing between two adjacent first doping regions 240, it is possible to design and prepare JFET devices with various pinch-off voltages with excellent performance on the same platform without adjusting the process recipe.

[0038] Specifically, the same type of first doping region 240, bottom doping region 220 and second doping region 250 are connected, so that the first doping region 240 can be connected to voltage G through the second doping region 250 to form a depletion region at the first doping region 240 and the surrounding drift region 230. Figure 4 and Figure 5As the input voltage G gradually increases, the width of the depletion region formed at the first doping region 240 and the surrounding drift region 230 also gradually increases until the input voltage G reaches the pinch-off voltage Vp, so that the depletion regions formed between adjacent first doping regions 240 are connected, and the lateral depletion pinch-off of the JFET device structure is realized. Therefore, by adjusting the spacing between two adjacent first doping regions 240, the depletion region width required for pinch-off can be adjusted accordingly, that is, the pinch-off voltage Vp can be adjusted, so that JFET devices with various pinch-off voltages Vp with excellent performance can be designed and prepared on the same platform without adjusting the process recipe.

[0039] It should be noted that, for ease of understanding, Figure 4 and Figure 5 The depletion region is indicated by the blue dashed line, where Figure 4 Schematically shows the depletion region when the voltage G connected to the second doping region 250 is less than the pinch-off voltage Vp. Figure 5 FIG. 2 schematically shows the depletion region when the voltage G connected to the second doping region 250 is greater than or equal to the pinch-off voltage Vp.

[0040] Moreover, since a highly versatile photomask can be used to form the patterns of a plurality of first doping regions 240 , additional photomasks for the first doping regions 240 are reduced, thus effectively saving costs.

[0041] In one embodiment, the distance between two adjacent first doping regions 240 is positively correlated with the pinch-off voltage Vp of the JFET device structure, that is, the larger the pinch-off voltage Vp is, the larger the distance between two adjacent first doping regions 240 can be.

[0042] Those skilled in the art will appreciate that, in practical applications, depending on the device material, JFET device structure, application, etc., the pinch-off voltage Vp of the JFET device structure and the spacing between two adjacent first doping regions 240 may vary greatly, and the relationship between the two may also vary greatly. Therefore, the present application does not impose any specific restrictions on this.

[0043] In this embodiment, the substrate 200 is a P-type substrate.

[0044] Furthermore, the substrate 200 includes a bottom silicon layer (not shown) and a silicon epitaxial layer (not shown). In addition, the bottom doped region 220, the first doped region 240 and the second doped region 250 are all located in the silicon epitaxial layer.

[0045] In other embodiments, the substrate may also be made of materials such as germanium or germanium silicon, or may also be an SOI substrate.

[0046] In the present embodiment, the conductivity types of the bottom doping region 220 , the first doping region 240 , and the second doping region 250 are P-type, and the conductivity type of the drift region 230 is N-type.

[0047] In this embodiment, a plurality of first doping regions 240 are evenly spaced and arranged along a designated path, wherein the designated path is a ring path, thus facilitating uniform depletion, that is, the pinch-off voltage Vp difference at each location is small, thereby improving the performance and reliability of the device.

[0048] Accordingly, the second doping region 250 surrounds the drift region 230 to correspond to each of the first doping regions 240 on a designated path, so that each of the first doping regions 240 can be connected to the voltage G uniformly.

[0049] For ease of understanding, Figure 2 The designated path is schematically indicated by a blue dashed line in FIG. The circular path can be as follows: Figure 2 The track shape shown in the figure may also be other shapes such as circle, square, or rectangle.

[0050] In this embodiment, the annular path includes an arc-shaped path segment, and the first doping region 240 on the arc-shaped path segment has a first doping region projection 241 on the surface of the substrate 200 .

[0051] The two radial ends of the first doping region projection 241 along the arc path segment are respectively a first end 241a and a second end 241b, the second end 241b is located between the first end 241a and the second doping region 250, and the minimum spacing L1 between adjacent first ends 241a is smaller than the minimum spacing L2 between adjacent second ends 241b.

[0052] Generally, along the radial direction of a specified path, the closer to the inner side, the slower the depletion. By making the minimum spacing L1 between adjacent first ends 241a smaller than the minimum spacing L2 between adjacent second ends 241b, the depletion can be more uniform in the radial direction, thereby further improving the performance and reliability of the device. In addition, compared with the non-arc-shaped path segment, the change in the depletion speed of the arc-shaped path segment is more obvious. Therefore, in the arc-shaped path segment, the minimum spacing L1 is smaller than the minimum spacing L2, which can improve the improvement efficiency of the depletion uniformity.

[0053] In this embodiment, the first doping region projection 241 is a trapezoid, and the parallel opposite sides of the trapezoid are perpendicular to the radial direction of the arc-shaped path segment. In other words, the width of the first doping region projection 241 gradually increases along the radial direction of the arc-shaped path segment, thereby better improving the depletion uniformity.

[0054] In other embodiments, other shapes of the first doping region projection may be used to increase the width of the first doping region projection discontinuously along the radial direction of the arc-shaped path segment.

[0055] In this embodiment, the JFET device structure further includes: a top isolation structure 300 , a source region 261 and a drain region 262 .

[0056] It should be noted that in order to facilitate understanding of the positional relationship, Figure 2 Only corresponding indication Figure 3 The drift region 230, the first doped region 240, the source region 261 and the drain region 262 are formed in the embodiment of the present invention.

[0057] The top isolation structure 300 is located on the top surface of the first doping region 240, the source region 261 and the drain region 262 are located in the drift region 230 and are located on both sides of the top isolation structure 300, and the top surfaces of the source region 261 and the drain region 262 are flush with the top surface of the drift region 230. The source region 261 is located between the first doping region 240 and the second doping region 250.

[0058] The top isolation structure 300 can prevent a conductive layer directly connecting the source region 261 and the drain region 262 from being formed on the surface between the source region 261 and the drain region 262 , thereby reducing device failure.

[0059] Specifically, the top isolation structure 300 in this embodiment is a polysilicon pseudo gate. Therefore, the top isolation structure 300 shields the surface of the drift region 230 and the top surface of the first doping region 240 below it, avoiding the formation of a conductive layer directly connecting the source region 261 and the drain region 262 during the silicon metallization process.

[0060] In other embodiments, dielectric material may also be used as the material of the top isolation structure 300 .

[0061] Specifically, in another embodiment, the top isolation structure may also be a silicide blocking layer (SAB).

[0062] Specifically, in yet another embodiment, the top isolation structure may also be a shallow trench isolation (STI) structure located in the drift region 230 .

[0063] In this embodiment, the JFET device structure further includes: a second contact region 292 .

[0064] The second contact region 292 is located on the second doping region 250 and exposes the top surface. The conductivity type of the second contact region 292 is the same as that of the second doping region 250, and the conductive ion doping concentration of the second contact region 292 is higher than that of the second doping region 250 to better lead out the second doping region 250.

[0065] In this embodiment, the JFET device structure further includes: a first isolation structure 310 exposing the top surface.

[0066] The first isolation structure 310 is located between the source region 261 and the second contact region 292, and extends between the drift region 230 and the second doping region 250, and the height of the first isolation structure 310 is less than the depth of the second doping region 250, that is, the first isolation structure 310 is also located between a portion of the drift region 230 under the source region 261 and a portion of the second doping region 250 under the second contact region 292, and the second doping region 250 is in contact with the drift region 230 below the first isolation structure 310. Therefore, on the one hand, the first isolation structure 310 can avoid the formation of a conductive layer (such as a silicon metal layer, etc.) that directly connects the source region 261 and the second contact region 292, and on the other hand, a conductive channel is left below the first isolation structure 310.

[0067] Specifically, the first isolation structure 310 may be a shallow trench isolation structure.

[0068] In this embodiment, the JFET device structure further includes: a third doped region 270 and a buried layer 210 .

[0069] The third doping region 270 surrounds the second doping region 250 and is independent of the second doping region 250 . The third doping region 270 and the second doping region 250 have opposite conductivity types.

[0070] Specifically, the third doping region 270 is located in the epitaxial layer of the substrate 200 .

[0071] The buried layer 210 is located below the bottom doped region 220 and the third doped region 270 . The bottom of the bottom doped region 220 and the bottom of the third doped region 270 are respectively connected to the buried layer 210 . The buried layer 210 and the third doped region 270 have the same conductivity type.

[0072] Specifically, the buried layer 210 is located on the surface of the bottom silicon layer in the substrate 200 , and the silicon epitaxial layer in the substrate 200 is located on the surfaces of the buried layer 210 and the bottom silicon layer.

[0073] Since the third doping region 270 surrounds the second doping region 250, the buried layer 210 is located below the bottom doping region 220 and the third doping region 270, and the bottom of the bottom doping region 220 and the bottom of the third doping region 270 are respectively connected to the buried layer 210, therefore, the third doping region 270 and the buried layer 210 divide the substrate into its outer region and its inner region in a connected structure, and surround the bottom doping region 220 and the second doping region 250 in the inner region to separate the two from the substrate 200 in the outer region thereof. On this basis, by having the third doping region 270 and the second doping region 250 having opposite conductivity types, and the buried layer 210 and the third doping region 270 having the same conductivity type, conduction between the substrate 200 in the outer region of the third doping region 270 and the buried layer 210 and the bottom doping region 220 and the second doping region 250 is avoided.

[0074] Specifically, the third doping region 270 and the buried layer 210 are both N-type.

[0075] In this embodiment, the JFET device structure further includes: a third contact region 293 .

[0076] The third contact region 293 is located on the third doping region 270 and exposes the top surface. The conductivity type of the third contact region 293 is the same as that of the third doping region 270, and the conductive ion doping concentration of the third contact region 293 is higher than that of the third doping region 270 to better lead out the third doping region 270.

[0077] Specifically, the third contact region 293 is of N type.

[0078] In this embodiment, the JFET device structure further includes: a second isolation structure 320 exposing the top surface.

[0079] The second isolation structure 320 is located between the second contact region 292 and the third contact region 293, and between a portion of the second doping region 250 below the second contact region 292 and a portion of the third doping region 270 below the third contact region 293. Therefore, the second isolation structure 320 can prevent a conductive layer (such as a silicon metal layer, etc.) from being formed between the second contact region 292 and the third contact region 293 to directly connect the two.

[0080] Specifically, the second isolation structure 320 may be a shallow trench isolation structure.

[0081] In this embodiment, the JFET device structure further includes: a fourth doping region 280 .

[0082] The fourth doping region 280 is located in the substrate 200 and surrounds the third doping region 270. The fourth doping region 280 has the same conductivity type as the second doping region 250. Specifically, the fourth doping region 280 is P-type. Thus, the substrate 200 is led out.

[0083] Specifically, the fourth doping region 280 is located in the silicon epitaxial layer in the substrate 200 .

[0084] In this embodiment, the JFET device structure further includes: a fourth contact region 294 .

[0085] The fourth contact region 294 is located on the fourth doping region 280 . The conductivity type of the fourth contact region 294 is the same as that of the fourth doping region 280 . The conductive ion doping concentration of the fourth contact region 294 is higher than that of the fourth doping region 280 to better lead out the fourth doping region 280 .

[0086] Specifically, the fourth contact region 294 is of P type.

[0087] In this embodiment, the JFET device structure further includes: a third isolation structure 330 exposing the top surface.

[0088] The third isolation structure 330 is located between the third contact region 293 and the fourth contact region 294, and between a portion of the third doping region 270 under the third contact region 293 and a portion of the fourth doping region 280 under the fourth contact region 294. Therefore, the third isolation structure 330 can prevent a conductive layer (such as a silicon metal layer, etc.) from being formed between the second contact region 292 and the third contact region 293 to directly connect the two.

[0089] Specifically, the second isolation structure 320 may be a shallow trench isolation structure.

[0090] In this embodiment, the JFET device structure further includes: a device isolation structure 340 .

[0091] The device isolation structure 340 surrounds and is adjacent to the fourth doping region 280 to isolate the JFET device structure from other surrounding devices.

[0092] Specifically, the device isolation structure 340 may be a shallow trench isolation structure.

[0093] The shallow trench isolation structures in this embodiment can be formed in the same process to simplify the process complexity of the JFET device structure.

[0094] Correspondingly, an embodiment of the present invention further provides a method for forming the above-mentioned JFET device structure, comprising: forming a substrate 200 and a bottom doping region 220 located in the substrate 200; after forming the bottom doping region 220, forming a drift region 230 in the substrate 200, wherein the drift region 230 is adjacent to the bottom doping region 220; forming a plurality of mutually independent first doping regions 240 in the drift region 230, wherein the first doping regions 240 penetrate the drift region 230 in a direction perpendicular to the surface of the substrate 200 and connect to the bottom doping region 220, wherein the conductivity type of the first doping regions 240 is opposite to the conductivity type of the drift region 230, and the spacing between two adjacent first doping regions 240 is determined based on the pinch-off voltage Vp of the JFET device structure; forming a second doping region 250 in the substrate 200 and around the drift region 230, wherein the second doping region 250 connects the drift region 230 and the bottom doping region 220 respectively, and the second doping region 250, the first doping region 240 and the bottom doping region 220 have the same conductivity type.

[0095] In this embodiment, during the process of forming the substrate 200 , a buried layer 210 is also formed.

[0096] Specifically, the method for forming the substrate 200 and the buried layer 210 includes: providing a bottom silicon layer; forming the buried layer 210 on the bottom silicon layer; and forming a silicon epitaxial layer on the surfaces of the bottom silicon layer and the buried layer 210 .

[0097] In this embodiment, after the silicon epitaxial layer is formed, an ion implantation process is performed on the silicon epitaxial layer to form a bottom doped region 220 .

[0098] In this embodiment, after forming the drift region 230 and before forming the first doping region 240 and the second doping region 250 , a first isolation structure 310 , a second isolation structure 320 , a third isolation structure 330 and a device isolation structure 340 are formed in the substrate 200 .

[0099] Furthermore, the method for forming the first isolation structure 310, the second isolation structure 320, the third isolation structure 330 and the device isolation structure 340 includes: etching the silicon epitaxial layer to form a plurality of openings corresponding to the first isolation structure 310, the second isolation structure 320, the third isolation structure 330 and the device isolation structure 340 in the silicon epitaxial layer; and filling the plurality of openings with dielectric material to form the first isolation structure 310, the second isolation structure 320, the third isolation structure 330 and the device isolation structure 340.

[0100] In this embodiment, after forming the first doping region 240 and before forming the second doping region 250 , a top isolation structure 300 is formed on the surface of the first doping region 240 and the substrate 200 .

[0101] The method for forming the top isolation structure 300 includes: forming a top isolation structure material layer (not shown) on the surface of the first doped region 240, the substrate 200, the first isolation structure 310, the second isolation structure 320, the third isolation structure 330 and the device isolation structure 340; etching the top isolation structure material layer to form a patterned top isolation structure 300.

[0102] In this embodiment, after the top isolation structure 300 is formed, a third doping region 270 and a fourth doping region 280 are respectively formed in the silicon epitaxial layer.

[0103] In this embodiment, after the third doping region 270 and the fourth doping region 280 are formed, a source region 261 and a drain region 262 are respectively formed on the drift region 230 on both sides of the top isolation structure 300, a second contact region 292 is formed on the second doping region 250, a third contact region 293 is formed on the third doping region 270, and a fourth contact region 294 is formed on the fourth doping region 280.

[0104] It should be understood that since this embodiment is a method embodiment corresponding to the above-mentioned structural embodiment, for a detailed explanation of each feature in this embodiment, please refer to the relevant description of the corresponding features in the above-mentioned structural embodiment, which will not be repeated here.

[0105] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A JFET device structure, characterized in that: include: substrate; a bottom doped region located in the substrate; A drift region, located in the substrate and adjacent to the bottom doped region; a plurality of mutually independent first doped regions, wherein the first doped regions are located in the drift region, penetrate the drift region in a direction perpendicular to the substrate and are connected to the bottom doped region, The conductivity type of the first doping region is opposite to the conductivity type of the drift region, and the distance between two adjacent first doping regions is determined based on the pinch-off voltage of the JFET device structure; The second doping region is located above the bottom doping region and around the drift region, and the second doping region is in contact with the drift region and the bottom doping region respectively, and the second doping region, the first doping region and the bottom doping region have the same conductivity type.

2. The JFET device structure according to claim 1, characterized in that: A plurality of the first doped regions are evenly spaced and arranged along a designated path, and the designated path is a ring path; the second doped regions surround the drift region.

3. The JFET device structure according to claim 2, characterized in that: The annular path includes an arcuate path segment, a first doped region on the arcuate path segment has a first doped region projection on the substrate surface, two radial ends of the first doped region projection along the arcuate path segment are respectively a first end and a second end, the second end is located between the first end and the second doped region, and a minimum spacing between adjacent first ends is smaller than a spacing between adjacent second ends.

4. The JFET device structure according to claim 3, characterized in that: The projection of the first doping region is a trapezoid, and the parallel opposite sides of the trapezoid are perpendicular to the radial direction of the arc-shaped path segment.

5. The JFET device structure according to any one of claims 1 to 4, characterized in that: Also includes: A top isolation structure, located on a top surface of the first doped region; A source region and a drain region are located in the drift region and are respectively located on both sides of the top isolation structure, wherein the source region is located between the first doping region and the second doping region.

6. The JFET device structure according to claim 5, characterized in that: Also includes: a second contact region, located on the second doping region, the conductivity type of the second contact region being the same as that of the second doping region, and the conductive ion doping concentration of the second contact region being higher than that of the second doping region; A first isolation structure is located between the second contact region and the source region, and between a portion of the drift region under the source region and a portion of the second doped region under the second contact region, and a height of the first isolation structure is less than a depth of the second doped region, and the second doped region is in contact with the drift region below the first isolation structure.

7. The JFET device structure according to claim 6, characterized in that: Also includes: a third doping region, surrounding the second doping region and being independent of the second doping region, the third doping region and the second doping region having a conductivity type opposite to each other; A buried layer is located below the bottom doped region and the third doped region, the bottom of the bottom doped region and the bottom of the third doped region are respectively connected to the buried layer, and the buried layer and the third doped region have the same conductivity type.

8. The JFET device structure according to claim 7, characterized in that: Also includes: a third contact region, located on the third doping region, the conductivity type of the third contact region being the same as that of the third doping region, and the conductive ion doping concentration of the third contact region being higher than that of the third doping region; The second isolation structure is located between the second contact region and the third contact region, and between a portion of the second doped region under the second contact region and a portion of the third doped region under the third contact region.

9. The JFET device structure according to claim 8, characterized in that: Also includes: a fourth doping region, located in the substrate and surrounding the third doping region, the fourth doping region and the second doping region having the same conductivity type; a fourth contact region, located on the fourth doping region, the conductivity type of the fourth contact region being the same as that of the fourth doping region, and the conductive ion doping concentration of the fourth contact region being higher than that of the fourth doping region; The third isolation structure is located between the third contact region and the fourth contact region, and between a portion of the third doped region under the third contact region and a portion of the fourth doped region under the fourth contact region.

10. A method for forming a JFET device structure, characterized in that: A JFET device structure is formed as claimed in any one of claims 1 to 9.

Images