A silicon carbide power MOSFET and its fabrication method

Abstract

This invention belongs to the field of power semiconductor technology, specifically relating to a silicon carbide power MOSFET and its fabrication method. The silicon carbide power MOSFET provided by this invention includes a substrate, a first epitaxial layer, a first CSL layer, a first P-body region, a second epitaxial layer, a second CSL layer, and a second P-body region. A trench region is provided between the two P-body regions, with P+ regions injected at the bottom of the trench and N+ regions distributed on the sidewalls. Specifically, the on-resistance is reduced by the double CSL layer and P-body structure, while the JFET region length is extended to limit short-circuit current, significantly improving short-circuit withstand time. This makes it suitable for high-power, high-reliability power electronic devices.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor technology, specifically relating to a silicon carbide power MOSFET and its fabrication method. Background Technology

[0002] The information disclosed in this background section is intended only to enhance understanding of the overall background of the invention and is not necessarily to be construed as an admission or in any way implying that such information constitutes prior art known to those skilled in the art.

[0003] Power MOSFETs need to carry large currents in the on-state and withstand high breakdown voltages in the off-state. Traditional silicon-based MOSFETs suffer from high on-resistance and high switching losses. Silicon carbide (SiC), as a third-generation wide-bandgap semiconductor material, has higher breakdown voltage, lower on-resistance, and lower on-loss, but it still faces problems such as excessive on-resistance and short-circuit withstand time in power device applications, leading to increased on-loss and reduced reliability.

[0004] Traditional MOSFET designs aimed at reducing on-resistance often result in excessively high saturation current, leading to shorter short-circuit times and reduced reliability. Conversely, increasing short-circuit withstand time increases on-resistance, cost, and switching losses. Therefore, improving device reliability while reducing on-resistance is a critical challenge in silicon carbide MOSFET design. This requires those skilled in the art to explore a device design that combines low on-resistance and high short-circuit withstand capability to optimize silicon carbide MOSFET performance. Summary of the Invention

[0005] To address the aforementioned problems, the present invention aims to provide a silicon carbide power MOSFET and its fabrication method. The silicon carbide power MOSFET fabricated by the present invention has a two-layer cell structure created using a regeneration technique, and a trench structure is formed by etching silicon carbide. P-type ion implantation is performed at the bottom and sidewalls of the trench to achieve ohmic contacts. The two-layer cell structure provides twice the JFET region length, limiting the saturation current of the MOSFET device while reducing on-resistance. Under short-circuit conditions, the current flowing through the device is significantly reduced, greatly improving the device's short-circuit withstand capability, thus resolving the contradiction between reducing on-resistance and improving short-circuit withstand capability.

[0006] Specifically, the present invention provides the following technical solution:

[0007] A first aspect of the present invention provides a silicon carbide power MOSFET, comprising, from bottom to top:

[0008] Substrate;

[0009] A first epitaxial layer, a first CSL layer, a first P-body region implanted on the first epitaxial layer, a second epitaxial layer, a second CSL layer, and a second P-body region implanted on the second epitaxial layer are sequentially stacked on the substrate.

[0010] A trench region is provided between the first P body region and the second P body region. The lower half of the trench region is surrounded by a P+ region, and the upper half is distributed with N+ regions on both sides.

[0011] A gate oxide layer and a gate polysilicon layer are applied to both sides above the second epitaxial layer, wherein the gate oxide layer and the gate polysilicon layer partially cover the second CSL layer, a portion of the second P body region and a portion of the N+ region;

[0012] A dielectric layer disposed above and on the side of the gate polysilicon, and a source metal layer covering the N+ region, the dielectric layer region and the entire trench region;

[0013] And a top metal layer disposed above the dielectric layer and the source metal layer.

[0014] Preferably, the thickness of the first CSL layer is 1.2~1.5 μm, the thickness of the second epitaxial layer is 1.5~2.5 μm, the thickness of the second CSL layer is 1.2~1.5 μm, the thickness of the first P body region is 0.7~1.0 μm, and the thickness of the second P body region is 0.7~1.0 μm.

[0015] Preferably, the etching depth of the trench region is 1.5~3.5 μm, the thickness of the N+ region is 0.1~0.5 μm, and the thickness of the P+ region is 0.1~0.5 μm.

[0016] Preferably, the thickness of the gate oxide layer is 20~80 nm; the thickness of the dielectric layer is 0.3~0.8 μm; and the thickness of the top metal layer is 1~10 μm.

[0017] In this invention, the thickness and doping concentration of the epitaxial layer are generally determined according to the voltage rating of the device to be fabricated. For example, when fabricating a device with a voltage rating of 1200 V, the thickness of the first epitaxial layer is 8~15 μm.

[0018] In this invention, the etching depth of the trench region is greater than the thickness of the second epitaxial layer and less than the sum of the thicknesses of the second epitaxial layer and the first P body region.

[0019] A second aspect of the present invention provides a method for manufacturing the above-mentioned silicon carbide power MOSFET, comprising the following steps:

[0020] S1. A first epitaxial layer is grown on an n-type heavily doped substrate, and carpet-like ion implantation is performed to form a first CSL layer.

[0021] S2. A first hard mask layer is formed on the surface of the first epitaxial layer. The ion implantation window of the first P body region is exposed by etching through the mask, and aluminum ions are implanted to form the first P body region.

[0022] S3. A second epitaxial layer is grown on the first P body region, and carpet-like ion implantation is performed to form a second CSL layer;

[0023] S4. A second hard mask layer is fabricated on the surface of the second epitaxial layer. The ion implantation window of the second P body region is exposed by etching through the mask, and aluminum ions are implanted to form the second P body region.

[0024] S5. A sidewall region is formed on the sidewall of the second hard mask layer, and nitrogen ions are injected to form an N+ region.

[0025] S6. Remove the second hard mask layer and use a mask to etch the third hard mask layer to expose the window for etching silicon carbide; etch the first epitaxial layer and the second epitaxial layer to form a trench region, at which point the N+ region is divided into two by the trench region; after etching, inject aluminum ions into the bottom and sidewalls of the trench to form a P+ region.

[0026] S7. Remove the third hard mask layer, deposit the cap layer and perform high-temperature thermal annealing to activate the implanted ions, and then remove the cap layer.

[0027] S8. The gate oxide layer is formed by thermally oxidizing silicon carbide and annealing, the gate region is formed by depositing and etching n-type doped polysilicon, the source window is deposited and the source metal layer is etched, the source metal layer is sputtered to form an ohmic contact with the N+ and P+ regions, the top metal layer is evaporated and the source region is etched using a mask, and then the back side is scribing, cleaning and substrate thinning processes are performed to form ohmic contacts and electrodes on the back side, thus completing the fabrication of the device.

[0028] Preferably, in step S1, the substrate is an n-type heavily doped low resistivity substrate of 4H-SiC with a resistivity of 0.015~0.025 Ω·cm.

[0029] Preferably, in steps S1 and S3, the doping concentration of the first epitaxial layer and the second epitaxial layer is 1×10⁻⁶. 15 ~1×10 16 cm -3 The doping concentration of the first CSL layer and the second CSL layer is 2×10⁻⁶. 16 ~1×10 17 cm -3 .

[0030] Preferably, in steps S2 and S4, the composition of the first hard mask layer and the second hard mask layer is selected from any of the following:

[0031] a. Ion implantation barrier layer and oxide layer;

[0032] b. Ion implantation barrier layer, polysilicon layer;

[0033] c. Ion implantation barrier layer, polysilicon layer, metal layer;

[0034] d. Ion implantation barrier layer, polysilicon layer, oxide layer;

[0035] e. Ion implantation barrier layer, polysilicon layer, oxide layer, metal layer;

[0036] The ion implantation barrier layer includes a silicon dioxide layer, the oxide layer includes a silicon dioxide layer, and the metal layer is made of materials including nickel, titanium, gold, copper, chromium, and aluminum.

[0037] Preferably, in steps S2 and S4, the peak aluminum ion implantation concentration in the first P-body region and the second P-body region is 1×10⁻⁶. 18 ~3×10 18 cm -3 Furthermore, it employs a reverse doping distribution, with the surface doping concentration being lower than the deep doping concentration.

[0038] Preferably, in step S5, the peak concentration of nitrogen ions in the N+ region is ≥1×10⁻⁶. 20 cm -3 The sidewall region is made of polycrystalline silicon, silicon dioxide, or silicon nitride, with a thickness not exceeding 0.5 μm, to form a short channel structure with a channel length ≤ 0.5 μm.

[0039] Preferably, in step S6, the etching depth of the trench region is greater than the thickness of the second epitaxial layer and less than the sum of the thicknesses of the second epitaxial layer and the first P-body region, and the surface doping concentration of the P+ region is 1×10⁻⁶. 18 ~1×10 19 cm -3 .

[0040] Preferably, in step S6, the composition of the third hard mask layer is selected from any of the following:

[0041] a. Oxide layer;

[0042] b. Metal layer;

[0043] The oxide layer includes a silicon dioxide layer, and the metal layer is made of materials including nickel, titanium, gold, copper, chromium, and aluminum.

[0044] Preferably, in step S7, the cap layer is composed of carbon; the high-temperature annealing temperature is 1500~1900℃, the time is 8~15 minutes, and the annealing atmosphere is nitrogen or argon.

[0045] Preferably, in step S8, the material of the source metal layer is nickel, titanium, tungsten, tantalum, molybdenum, aluminum or an alloy thereof, and the material of the top metal layer is aluminum.

[0046] Preferably, in step S8, the source metal layer forms an ohmic contact with the P+ region in step S6 to ensure that the potential of the first P body region is the same as that of the source.

[0047] A third aspect of the present invention provides an application of the silicon carbide power MOSFET described in the first aspect in a semiconductor device.

[0048] One or more embodiments of the present invention have at least the following beneficial effects:

[0049] (1) The present invention provides a MOSFET structure with low on-resistance and high short-circuit withstand capability. The double CSL layer reduces the on-resistance of the device, and the double P body layer extends the length of the JFET region, so that the MOSFET has a smaller current under short-circuit operating conditions and can withstand a longer short-circuit time.

[0050] (2) The structure fabricated by the present invention has an on-resistance of 78.5 mohm when Ids=20 A, which is lower than that of the traditional structure (89.6 mohm). In addition, the structure fabricated by the present invention shuts down normally when the short circuit time is 3.8 μs and fails just when the short circuit time is 31 μs (at 800 V bus voltage), which is higher than that of the traditional structure (short circuit withstand time is 3.8 μs).

[0051] (3) In the structure fabricated by the present invention, the trench is etched to the first P body region and the P+ region is injected to ground, so that the potential of the first P body region is the same as that of the source, thus ensuring the breakdown voltage of the MOSFET. Attached Figure Description

[0052] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0053] Figure 1 This is a schematic cross-sectional view of the silicon carbide power MOSFET fabricated in Embodiment 1 of the present invention;

[0054] Figure 2This is a schematic cross-sectional view of the device formed after step S2 in the manufacturing method of Embodiment 1 of the present invention;

[0055] Figure 3 This is a schematic cross-sectional view of the device formed after step S4 in the manufacturing method of Embodiment 1 of the present invention;

[0056] Figure 4 This is a schematic cross-sectional view of the device formed after step S5 in the manufacturing method of Embodiment 1 of the present invention;

[0057] Figure 5 This is a schematic cross-sectional view of the device formed after step S6 in the manufacturing method of Embodiment 1 of the present invention;

[0058] Figure 6 A cross-sectional schematic diagram of the conventional structure fabricated in Comparative Example 1 of this invention;

[0059] Figure 7 This is a comparison chart of the structural output curves obtained in Embodiment 1 and Comparative Example 1 of the present invention;

[0060] Figure 8 This is a comparison chart of the short-circuit withstand time curves of the structures obtained in Embodiment 1 and Comparative Example 1 of the present invention;

[0061] Wherein: 1. Substrate; 2. First epitaxial layer; 3. First CSL layer; 4. First hard mask layer; 5. First P-body region implantation window; 6. First P-body region; 7. Second epitaxial layer; 8. Second CSL layer; 9. Second hard mask layer; 10. Second P-body region implantation window; 11. Second P-body region; 12. Sidewall region; 13. N+ region; 14. Third hard mask layer; 15. Trench region; 16. P+ region; 17. Gate oxide layer; 18. Gate polysilicon; 19. Dielectric layer; 20. Source metal layer; 21. Top metal layer. Detailed Implementation

[0062] It should be noted that the following detailed description is illustrative and intended to provide further explanation of the invention. Unless otherwise specified, all technical and scientific terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0063] The present invention will be further described in detail below with reference to specific embodiments. It should be noted that the specific embodiments are explanations of the present invention and not limitations thereof.

[0064] Example 1:

[0065] A silicon carbide planar gate power MOSFET, such as Figure 1 As shown, from bottom to top, it includes:

[0066] Substrate 1; a first epitaxial layer 2, a first CSL layer 3, a first P body region 6 implanted on the first epitaxial layer, a second epitaxial layer 7, a second CSL layer 8, and a second P body region 11 implanted on the second epitaxial layer are sequentially stacked on the substrate; a trench region 15 is disposed between the first P body region 6 and the second P body region 11, the lower half of the trench region 15 is surrounded by a P+ region 16, and the upper half is distributed with N+ regions 13 on both sides;

[0067] The gate oxide layer 17 and the gate polysilicon 18 are covered on both sides above the second epitaxial layer 7, and the gate oxide layer 17 and the gate polysilicon 18 partially cover the second CSL layer 8, part of the second P body region 11 and part of the N+ region 13; the dielectric layer 19 is disposed above and on the side of the gate polysilicon 18; the source metal layer 20 covers the N+ region 13, the dielectric layer 19 region and the entire trench region 15; and the top metal layer 21 is disposed above the dielectric layer 19 and the source metal layer 20.

[0068] In this embodiment, the substrate is an n-type heavily doped low resistivity substrate of 4H-SiC with a resistivity of 0.020 Ω·cm.

[0069] In this embodiment, the thickness of the first epitaxial layer 2 is 8 μm, and the doping concentration is 1×10⁻⁶. 16 cm -3 The thickness of the first CSL layer 3 is 1.2 μm, and the doping concentration is 1×10⁻⁶. 16 cm -3 ~2×10 17 cm -3 .

[0070] The second epitaxial layer 7 has a thickness of 2 μm and a doping concentration of 1×10⁻⁶. 16 cm -3 The second CSL layer 8 has a thickness of 1.2 μm and a doping concentration of 1×10⁸. 16 cm -3 ~2×10 17 cm -3 .

[0071] In this embodiment, to achieve a sufficient breakdown voltage, the thickness of the first P-body region 6 is 1 μm, and the aluminum ion implantation concentration is 1 × 10⁻⁶. 17 cm -3 ~3×10 18 cm -3 The thickness of the second P-body region 11 is 1 μm, and the aluminum ion implantation concentration is 1 × 10⁻⁶. 17 cm -3 ~3×10 18 cm-3 The doping concentration at this order of magnitude is high enough that the barrier at the channel source end will not be lowered by the voltage applied to the drain.

[0072] In this embodiment, the etching depth of trench region 15 is 2.2 μm; the peak nitrogen ion concentration of N+ region 13 is 1×10⁻⁶. 20 cm -3 The thickness is 0.3 μm; the surface doping concentration of P+ region 16 is 3 × 10⁻⁶. 18 cm -3 The thickness is 0.3 μm to ensure good ohmic contact.

[0073] In this embodiment, the thickness of the gate oxide layer 17 is 50 nm; the thickness of the dielectric layer 19 is 0.5 μm; and the thickness of the top metal layer 21 is 2 μm.

[0074] In this embodiment, the fabrication method based on the aforementioned silicon carbide planar gate power MOSFET structure includes the following steps:

[0075] like Figure 2 As shown: (1) An n-type first epitaxial layer 2 is grown on the substrate and carpet implantation is performed to form a first CSL layer 3; (2) A first hard mask layer 4 of sufficient thickness is fabricated on the wafer surface, and the first hard mask layer 4 is etched using a mask to expose the window for ion implantation of the first P body region (first P body region implantation window 5); p-type (e.g., aluminum ion) implantation is performed to form the first P body region 6;

[0076] In this embodiment, in step (2), the composition of the first hard mask layer 4 from bottom to top includes the following selections:

[0077] a. Ion implantation barrier layer (e.g., silicon dioxide layer), oxide layer (e.g., silicon dioxide);

[0078] b. Ion implantation barrier layer (e.g., silicon dioxide layer), polycrystalline silicon layer;

[0079] c. Ion implantation barrier layer (e.g., silicon dioxide layer), polycrystalline silicon layer, metal layer (e.g., nickel, titanium, gold, copper, chromium, aluminum);

[0080] d. Ion implantation barrier layer (e.g., silicon dioxide layer), polysilicon layer, oxide layer (e.g., silicon dioxide layer);

[0081] e. Ion implantation barrier layer (e.g., silicon dioxide layer), polycrystalline silicon layer, oxide layer (e.g., silicon dioxide layer), metal layer (e.g., nickel, titanium, gold, copper, chromium, aluminum).

[0082] For example, if the first hard mask layer is selected as a, then the composition of the first hard mask layer from bottom to top is an ion implantation barrier layer and an oxide layer.

[0083] like Figure 3 As shown: (3) After the first P body region 6 is implanted, a second epitaxial layer 7 is grown on the wafer surface and a second CSL layer 8 is formed by carpet implantation; (4) A second hard mask layer 9 of sufficient thickness is fabricated on the wafer surface, and the second hard mask layer is etched using a mask to expose the window for ion implantation of the second P body region (second P body region implantation window 10); p-type implantation is performed to fabricate the second P body region 11;

[0084] In this embodiment, in step (4), the composition of the second hard mask layer 9 from bottom to top includes the following selections:

[0085] a. Ion implantation barrier layer (e.g., silicon dioxide layer), oxide layer (e.g., silicon dioxide);

[0086] b. Ion implantation barrier layer (e.g., silicon dioxide layer), polycrystalline silicon layer;

[0087] c. Ion implantation barrier layer (e.g., silicon dioxide layer), polycrystalline silicon layer, metal layer (e.g., nickel, titanium, gold, copper, chromium, aluminum);

[0088] d. Ion implantation barrier layer (e.g., silicon dioxide layer), polysilicon layer, oxide layer (e.g., silicon dioxide layer);

[0089] e. Ion implantation barrier layer (e.g., silicon dioxide layer), polycrystalline silicon layer, oxide layer (e.g., silicon dioxide layer), metal layer (e.g., nickel, titanium, gold, copper, chromium, aluminum).

[0090] In this embodiment, to avoid excessively high threshold voltage, the second P-body region 11 employs a reverse doping distribution, with a low surface doping concentration and a high doping concentration at deeper depths. Since silicon carbide is a wide bandgap semiconductor material, it possesses a larger built-in electric field in the PN junction. Silicon carbide can be used to fabricate normally-off accumulation-channel MOSFETs. Therefore, the doping concentration in the channel region is approximately 2 × 10⁻⁶ for n-type doping. 16 cm -3 Up to p-type doping 5×10 16 cm -3 between.

[0091] like Figure 4 As shown: (5) Next, a uniform thin layer is deposited and carpet-etched to the same thickness to form a sidewall region on the sidewall of the second hard mask layer 9 of the second P body region 11 in this step; the sidewall region is used to realize the self-aligned channel of the MOSFET; n-type implantation is performed to create the N+ region;

[0092] In this embodiment, the thickness of the uniform thin layer (sidewall region) should not exceed 0.5 μm to form a shorter channel of no more than 0.5 μm, thereby reducing the resistance of the channel region and thus reducing the on-resistance of the device.

[0093] In this embodiment, the material of the sidewall region can be polycrystalline silicon, silicon dioxide, or silicon nitride.

[0094] like Figure 5 As shown: (6) Remove the dielectric layer 19 and hard mask layer in step (5) on the wafer surface, and then fabricate a third hard mask layer 14 of sufficient thickness. Use a mask to etch the third hard mask layer 14 to expose the window for etching silicon carbide. Etch the first epitaxial layer 2 and the second epitaxial layer 7 to form a trench region 15. The N+ region 13 is divided into two by the trench region. After etching, p-type implantation is performed at the bottom and sidewalls of the trench to form a P+ region. After implantation, remove the third hard mask layer 14.

[0095] In this embodiment, the composition of the third hard mask layer 14 is selected from any of the following:

[0096] a. Oxide layer;

[0097] b. Metal layer;

[0098] The oxide layer includes a silicon dioxide layer, and the metal layer is made of materials including nickel, titanium, gold, copper, chromium, and aluminum.

[0099] (7) Next, a cap layer is deposited and subjected to high-temperature thermal annealing in an inert gas atmosphere to activate the implanted ions; after annealing, the cap layer is removed.

[0100] In this embodiment, the cap layer is composed of carbon; the inert gas is nitrogen or argon; the heat annealing temperature is between 1500℃ and 1900℃, and the time is between 8 and 15 minutes.

[0101] (8) such as Figure 1 As shown, the subsequent fabrication is carried out using standard MOSFET fabrication processes. First, the wafer surface after the above steps is cleaned; a gate oxide layer 17 is formed by thermal oxidation of silicon carbide and annealing; an n-type doped polysilicon gate electrode is deposited, and the gate region (gate polysilicon 18) is etched using a mask; a dielectric layer 19 is deposited, and the source region window is etched using a mask; a source metal layer is sputtered and rapidly thermally annealed to form an ohmic contact between the source metal layer 20 and the N+ and P+ regions; the top metal layer 21 is evaporated, and the source region is etched using a mask; back side scribing, cleaning, and substrate thinning processes are performed to form ohmic contacts and electrodes on the back side.

[0102] In this embodiment, the source metal can be selected from nickel, titanium, tungsten, tantalum, molybdenum, aluminum or alloys thereof; the top metal layer is composed of aluminum.

[0103] Comparative Example 1:

[0104] like Figure 6 The diagram shown is a traditional structural diagram, including the following from bottom to top:

[0105] Substrate 1; a first epitaxial layer 2, a second CSL layer 8, a second P body region 11 implanted on the first epitaxial layer, and a P+ region 16 are sequentially stacked on the substrate; N+ regions 13 are provided on both sides of the P+ region;

[0106] The gate oxide layer 17 and gate polysilicon 18 are covered on both sides above the first epitaxial layer 2, and the gate oxide layer 17 and gate polysilicon 18 partially cover the second CSL layer, part of the second P body region and part of the N+ region; the dielectric layer 19 is disposed above and on the side of the gate polysilicon 18; the source metal layer 20 covers the N+ region, the dielectric layer region and the entire trench region; and the top metal layer 21 is disposed above the dielectric layer and the source metal layer.

[0107] In this comparative example, the thickness of the first epitaxial layer is 10 μm, and the doping concentration is 1×10⁻⁶. 16 cm -3 The second CSL layer has a thickness of 1.2 μm and a doping concentration of 1×10⁻⁶. 16 cm -3 ~2×10 17 cm -3 ;

[0108] In this comparative example, the thickness of the second P-body region is 1 μm, and the aluminum ion implantation concentration is 1 × 10⁻⁶. 17 cm -3 ~3×10 18 .

[0109] In this comparative example, the peak concentration of nitrogen ions in the N+ region is 1 × 10⁻⁶. 20 cm -3 The thickness is 0.3 μm; the surface doping concentration of the P+ region is 3 × 10⁻⁶. 18 cm -3 The thickness is 1.0 μm to ensure good ohmic contact.

[0110] In this comparative example, the thickness of the gate oxide layer is 50 nm; the thickness of the dielectric layer is 0.5 μm; and the thickness of the top metal layer is 2 μm.

[0111] Experimental Example 1: This experimental example investigates the performance of the devices prepared in Example 1 and Comparative Example 1.

[0112] (1) such as Figure 7 As shown, under the same device area, the result obtained in Example 1 of the present invention has an on-resistance of 78.5 mohm when Ids=20 A. Compared with the conventional structure obtained in Comparative Example 1 (89.6 mohm), the on-resistance of the device is reduced. At the same time, the saturation current of the device is significantly reduced compared with the conventional structure.

[0113] (2) For example Figure 8 As shown, the short-circuit curves are compared under a bus voltage of 800 V for the same device area. The failure time of the conventional structure obtained in Comparative Example 1 is 3.8 μs, while the failure time of the structure obtained in the embodiment of the present invention is as long as 31 μs. Therefore, compared with the comparative example, the short-circuit withstand time of the device structure obtained in the embodiment of the present invention is greatly increased.

[0114] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A silicon carbide power MOSFET, characterized in that, From bottom to top, including: Substrate; A first epitaxial layer, a first CSL layer, a first Pbody region implanted on the first epitaxial layer, a second epitaxial layer, a second CSL layer, and a second Pbody region implanted on the second epitaxial layer are sequentially stacked on the substrate. A trench region is provided between the first P body region and the second P body region. The lower half of the trench region is surrounded by a P+ region, and the upper half is distributed with N+ regions on both sides. A gate oxide layer and a gate polysilicon layer are applied to both sides above the second epitaxial layer, wherein the gate oxide layer and the gate polysilicon layer partially cover the second CSL layer, a portion of the second P body region and a portion of the N+ region; A dielectric layer disposed above and on the side of the gate polysilicon, and a source metal layer covering the N+ region, the dielectric layer region and the entire trench region; And a top metal layer disposed above the dielectric layer and the source metal layer.

2. The silicon carbide power MOSFET as described in claim 1, characterized in that, The thickness of the first CSL layer is 1.2~1.5 μm, the thickness of the second epitaxial layer is 1.5~2.5 μm, the thickness of the second CSL layer is 1.2~1.5 μm, the thickness of the first P body region is 0.7~1.0 μm, and the thickness of the second P body region is 0.7~1.0 μm. The etching depth of the trench region is 1.5~3.5 μm, the thickness of the N+ region is 0.1~0.5 μm, and the thickness of the P+ region is 0.1~0.5 μm; wherein, the etching depth of the trench region is greater than the thickness of the second epitaxial layer and less than the sum of the thicknesses of the second epitaxial layer and the first P body region; The thickness of the gate oxide layer is 20~80 nm, the thickness of the dielectric layer is 0.3~0.8 μm, and the thickness of the top metal layer is 1~10 μm.

3. A method for fabricating a silicon carbide power MOSFET according to any one of claims 1 to 2, characterized in that, Includes the following steps: S1. A first epitaxial layer is grown on an n-type heavily doped substrate, and carpet-like ion implantation is performed to form a first CSL layer. S2. A first hard mask layer is formed on the surface of the first epitaxial layer. The ion implantation window of the first P body region is exposed by etching through the mask, and aluminum ions are implanted to form the first P body region. S3. A second epitaxial layer is grown on the first P body region, and carpet-like ion implantation is performed to form a second CSL layer; S4. A second hard mask layer is fabricated on the surface of the second epitaxial layer. The ion implantation window of the second P body region is exposed by etching through the mask, and aluminum ions are implanted to form the second P body region. S5. A sidewall region is formed on the sidewall of the second hard mask layer, and nitrogen ions are injected to form an N+ region. S6. Remove the second hard mask layer and use a mask to etch the third hard mask layer to expose the window for etching silicon carbide; etch the first epitaxial layer and the second epitaxial layer to form a trench region, at which point the N+ region is divided in two by the trench region; After etching, aluminum ions are injected into the bottom and sidewalls of the trench to form P+ regions; S7. Remove the third hard mask layer, deposit the cap layer and perform high-temperature thermal annealing to activate the implanted ions, and then remove the cap layer. S8. The gate oxide layer is formed by thermally oxidizing silicon carbide and annealing, the gate region is formed by depositing and etching n-type doped polysilicon, the source window is deposited and the source metal layer is etched, the source metal layer is sputtered to form an ohmic contact with the N+ and P+ regions, the top metal layer is evaporated and the source region is etched using a mask, and then the back side is scribing, cleaning and substrate thinning processes are performed to form ohmic contacts and electrodes on the back side, thus completing the fabrication of the device.

4. The manufacturing method as described in claim 3, characterized in that, In step S1, the substrate is an n-type heavily doped low resistivity substrate of 4H-SiC with a resistivity of 0.015~0.025 Ω·cm; In steps S1 and S3, the doping concentration of the first epitaxial layer and the second epitaxial layer is 1×10⁻⁶. 15 ~1×10 16 cm -3 The doping concentration of the first CSL layer and the second CSL layer is 2×10⁻⁶. 16 ~1×10 17 cm -3 .

5. The manufacturing method as described in claim 3, characterized in that, In steps S2 and S4, the composition of the first hard mask layer and the second hard mask layer is selected from any of the following: a. Ion implantation barrier layer and oxide layer; b. Ion implantation barrier layer, polysilicon layer; c. Ion implantation barrier layer, polysilicon layer, metal layer; d. Ion implantation barrier layer, polysilicon layer, oxide layer; e. Ion implantation barrier layer, polysilicon layer, oxide layer, metal layer; The ion implantation barrier layer includes a silicon dioxide layer, the oxide layer includes a silicon dioxide layer, and the metal layer is made of materials including nickel, titanium, gold, copper, chromium, and aluminum.

6. The manufacturing method as described in claim 3, characterized in that, In steps S2 and S4, the peak aluminum ion implantation concentration in the first P-body region and the second P-body region is 1×10⁻⁶. 18 ~3×10 18 cm -3 Furthermore, it employs a reverse doping distribution, with the surface doping concentration being lower than the deep doping concentration; In step S5, the peak concentration of nitrogen ions in the N+ region is ≥1×10⁻⁶. 20 cm -3 The sidewall region is made of polycrystalline silicon, silicon dioxide, or silicon nitride, with a thickness not exceeding 0.5 μm, to form a short channel structure with a channel length ≤ 0.5 μm.

7. The manufacturing method as described in claim 3, characterized in that, In step S6, the etching depth of the trench region is greater than the thickness of the second epitaxial layer and less than the sum of the thicknesses of the second epitaxial layer and the first P-body region, and the surface doping concentration of the P+ region is 1×10⁻⁶. 18 ~1×10 19 cm -3 ; In step S6, the composition of the third hard mask layer is selected from any of the following: a. Oxide layer; b. Metal layer; The oxide layer includes a silicon dioxide layer, and the metal layer is made of materials including nickel, titanium, gold, copper, chromium, and aluminum.

8. The manufacturing method as described in claim 3, characterized in that, In step S7, the cap layer is composed of carbon; the high-temperature annealing temperature is 1500~1900℃, the time is 8~15 minutes, and the annealing atmosphere is nitrogen or argon.

9. The manufacturing method as described in claim 3, characterized in that, In step S8, the material of the source metal layer is nickel, titanium, tungsten, tantalum, molybdenum, aluminum or an alloy thereof, and the material of the top metal layer is aluminum; The source metal layer forms an ohmic contact with the P+ region described in step S6, ensuring that the potential of the first P body region is the same as that of the source.

10. The application of a silicon carbide power MOSFET according to any one of claims 1 to 2 in a semiconductor device.

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