Integrated chip structure and manufacturing method thereof

Abstract

The invention provides an integrated chip structure and a manufacturing method thereof. The integrated chip structure comprises a composite epitaxial structure, a high-voltage device region, a low-voltage device region and a BJT (Bipolar Junction Transistor) region, the high-voltage device region, the low-voltage device region and the BJT region are arranged in the upper region of the composite epitaxial structure in a mutually isolated manner; the high-voltage device region is used for forming a high-voltage device, the low-voltage device region is used for forming a low-voltage device, and the BJT region is used for forming a bipolar junction transistor; the composite epitaxial structure comprises a bottom layer, a SiC isolation layer and a device preparation layer which are stacked along a second direction; the SiC isolation layer is bonded on the bottom layer, and a bonding interface layer is formed between the SiC isolation layer and the bottom layer; and the device preparation layer is arranged on the SiC isolation layer in an epitaxial manner and is used for manufacturing a high-voltage device region, a low-voltage device region and a BJT region. The size of a wafer obtained by using the composite epitaxial structure can reach 12 inches, which is far greater than the size of a current mainstream 4H-SiC wafer, so that the overall process cost is reduced, and the bonding SiC isolation layer can effectively avoid the occurrence of current and voltage crosstalk.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to an integrated chip structure and a manufacturing method thereof. Background Art

[0002] In recent years, the field of wide-bandgap semiconductor materials has developed rapidly, and materials such as SiC, GaN, gallium oxide (Ga2O3), diamond (C) and aluminum nitride (AlN) have emerged. Compared with traditional Si materials, these wide-bandgap semiconductor materials have shown significant advantages in key physical properties such as bandgap width, breakdown field strength, and electron saturation drift velocity, successfully breaking through the bottleneck that silicon-based materials are difficult to cope with high-power, high-voltage, high-frequency, and high-temperature application scenarios, and opening up a feasible path to surpass Moore's Law.

[0003] In practical applications, SiC power devices, due to their material properties, have shown broad application potential in new energy, aerospace, nuclear power and other fields facing high temperature, high pressure and high radiation environments. However, the driving circuits and protection circuits used with SiC power devices at this stage still use silicon-based materials. This mismatch greatly limits the full performance of SiC power devices, thereby restricting their application scope.

[0004] To overcome this problem, the field attempts to integrate the driving circuit and protection circuit of SiC power devices on SiC wafers, in order to effectively enhance system reliability, reduce parasitic effects, and optimize the overall system performance. However, as far as the existing silicon carbide integrated devices are concerned, although the phased results of monolithic integration have been achieved, they have fallen into a new dilemma: voltage or current crosstalk problems frequently occur between the device regions, which greatly reduces the chip performance.

[0005] Therefore, there is an urgent need to design a complex and effective isolation structure to resolve the above-mentioned technical difficulties and promote the in-depth application and steady development of wide bandgap semiconductor materials in the field of power devices. Summary of the invention

[0006] Based on the above description, the present invention provides an integrated chip structure and a method for manufacturing the same to solve the technical problem in the prior art that when performing monolithic integration on a SiC wafer, there is serious voltage and current crosstalk between device regions, which seriously affects the performance of the chip.

[0007] The technical solution of the present invention to solve the above technical problems is as follows: In a first aspect, the present invention provides an integrated chip structure, comprising: a composite epitaxial structure, an interlayer dielectric layer, a high voltage device region, a low voltage device region and a BJT region; The interlayer dielectric layer is arranged on the upper surface of the composite epitaxial structure; The high voltage device region, the low voltage device region and the BJT region are isolated from each other and are arranged in the upper region of the composite epitaxial structure and the interlayer dielectric layer; The high-voltage device region is used to form a high-voltage device, the low-voltage device region is used to form a low-voltage device, and the BJT region is used to form a bipolar junction transistor; Among them, the composite epitaxial structure includes a bottom layer, a SiC isolation layer and a device preparation layer which are stacked in sequence along the vertical direction; the SiC isolation layer is bonded on the bottom layer, and a bonding interface layer is formed between the SiC isolation layer and the bottom layer; the device preparation layer is epitaxially arranged on the SiC isolation layer, and is used to manufacture the high-voltage device area, the low-voltage device area and the BJT area.

[0008] Based on the above technical solution, the present invention can also be improved as follows.

[0009] Further, the high voltage device region is formed with a first N-type well region and a P-body region; and, a first P+ region and a first N+ region formed in a top region of the P-body region; A gate oxide dielectric layer formed above the device preparation layer; A first gate is formed on the gate oxide dielectric layer above the P-body region between the first N-type well region and the first N+ region, and the first gate partially covers the first N-type well region and the first N+ region; A first source electrode penetrating the interlayer dielectric layer and connected to the first P+ region and the first N+ region; a second N+ region formed in a top region of the first N-type well region; A first drain is disposed through the interlayer dielectric layer and connected to the second N+ region.

[0010] Furthermore, the low voltage device region includes a P-type MOS region and an N-type MOS region which are arranged at intervals in the device preparation layer.

[0011] Further, the P-type MOS region is formed with a second N-type well region; and, a second P+ region, a third P+ region and a third N+ region formed in a top region of the second N-type well region; A second drain electrode penetrating the interlayer dielectric layer and the gate oxide dielectric layer and connected to the second P+ region; A second source electrode penetrating the interlayer dielectric layer and the gate oxide dielectric layer and connected to the third P+ region and the third N+ region; A second gate is formed on the gate oxide dielectric layer above the P-body region between the second P+ region and the third P+ region, and the second gate partially covers the second P+ region and the third P+ region.

[0012] Further, the N-type MOS region is formed with a first P-type well region; and, a fourth P+ region, a fourth N+ region and a fifth N+ region formed in the top region of the first P-type well region; A third source electrode penetrating the interlayer dielectric layer and the gate oxide dielectric layer and connected to the fourth P+ region and the fourth N+ region; a third drain electrode penetrating the interlayer dielectric layer and the gate oxide dielectric layer and connected to the fifth N+ region; A third gate is formed on the gate oxide dielectric layer above the P-body region between the fourth N+ region and the fifth N+ region, and the third gate partially covers the fourth N+ region and the fifth N+ region.

[0013] Further, when the device preparation layer is a P-type epitaxial layer, the BJT region is formed with a third N-type well region and a second P-type well region; and, a sixth N+ region and a fifth P+ region formed in the top region of the third N-type well region; a sixth P+ region formed in the top region of the second P-type well region; a base electrode penetrating the interlayer dielectric layer and the gate oxide dielectric layer and connected to the sixth N+ region; an emitter electrode penetrating the interlayer dielectric layer and the gate oxide dielectric layer and connected to the fifth N+ region; and a collector electrode penetrating the interlayer dielectric layer and the gate oxide dielectric layer and connected to the fourth N+ region. When the device preparation layer is N-type epitaxial, the BJT region is formed with a third P-type well region and a fourth N-type well region; and, a seventh P+ region, a seventh N+ region and an eighth N+ region are formed in the top area of ​​the third P-type well region; a base electrode is arranged through the interlayer dielectric layer and the gate oxide dielectric layer and connected to the seventh P+ region; an emitter electrode is arranged through the interlayer dielectric layer and the gate oxide dielectric layer and connected to the seventh N+ region; and a collector electrode is arranged through the interlayer dielectric layer and the gate oxide dielectric layer and connected to the eighth N+ region.

[0014] Furthermore, the bottom layer includes a Si substrate and a high heat dissipation layer epitaxially grown on the Si substrate; the high heat dissipation layer is a 3C-SiC epitaxial layer; Alternatively, the bottom layer is a 3C-SiC polycrystalline substrate.

[0015] Furthermore, the device preparation layer is a 3C-SiC or 4H-SiC epitaxial layer.

[0016] In a second aspect, the present invention further provides a method for manufacturing the integrated chip structure as described in the first aspect, comprising: epitaxially growing a 3C-SiC epitaxial layer on a Si substrate to obtain a 3C-SiC substrate; H+ is injected into the surface of the semi-insulating SiC wafer to form an H+ aggregation layer; Cleaning 3C-SiC substrate and semi-insulating SiC wafer surface; Flip the semi-insulating SiC wafer to bond with the 3C-SiC substrate and strengthen the bonding strength at 150°C; The semi-insulating SiC wafer was peeled off along the H+ aggregation layer at 300°C, annealed at 1100°C to strengthen the bonding strength, and the wafer surface was polished; Epitaxially growing a 3C or 4H-SiC epitaxial layer to form a device preparation layer; preparing an integrated device on the device preparation layer; Wherein, the device preparation layer includes a high-voltage device area, a low-voltage device area and a BJT area; a high-voltage device is formed in the high-voltage device area, a low-voltage device is formed in the low-voltage device area, and a bipolar junction transistor is formed in the BJT area.

[0017] Based on the above technical solution, the present invention can also be improved as follows.

[0018] Furthermore, the step of preparing an integrated device on the device preparation layer specifically includes: By multiple ion implantations, a plurality of N-type well regions, P-type well regions, P-body regions, N-type heavily doped regions and P-type heavily doped regions are formed in the device preparation layer; growing a gate oxide dielectric layer by thermal oxidation; forming a polysilicon gate by deposition and etching; An isolation trench is formed by etching and filling a dielectric, or a PN junction isolation is used; growing an interlayer dielectric layer and etching metal vias; Metal is deposited and etched to form metal electrodes.

[0019] Compared with the prior art, the technical solution of this application has the following beneficial technical effects: Compared with the prior art, the integrated chip structure and the manufacturing method thereof provided by the present invention have the following beneficial effects: The composite epitaxial structure is to first epitaxially grow a 3C-SiC epitaxial layer on a Si substrate, then bond a semi-insulating (HPSI) SiC peeling film on the structure, and then epitaxially grow a 3C-SiC or 4H-SiC epitaxial layer on the surface. Finally, the device structure is integrated in the 3C-SiC or 4H-SiC epitaxial layer on the surface - the high-voltage device area, the low-voltage device area and the BJT area are isolated from each other and arranged in the upper area of ​​the composite epitaxial structure, the high-voltage device area is used to form a high-voltage device, the low-voltage device area is used to form a low-voltage device, and the BJT area is used to form a bipolar junction transistor.

[0020] The wafer size obtained by using the above-mentioned composite epitaxial structure can reach 12 inches, which is much larger than the size of the current mainstream 4H-SiC wafer, thereby reducing the overall process cost and being able to adopt advanced processes in Si integrated circuits. In addition, after the bonded semi-insulating (HPSI) SiC peeling film, a SiC isolation layer is naturally formed, which can effectively prevent the occurrence of current and voltage crosstalk. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of the structure of an integrated chip provided in Embodiment 1 of the present invention; Figure 2 A schematic structural diagram of a composite epitaxial structure in an integrated chip structure provided in Embodiment 1 of the present invention; Figure 3 A schematic diagram of the structure of an integrated chip provided in Embodiment 2 of the present invention; Figure 4 A schematic structural diagram of a composite epitaxial structure in an integrated chip structure provided in Embodiment 3 of the present invention; Figure 5 A schematic diagram of the structure of an integrated chip provided in Embodiment 4 of the present invention; Figure 6 A schematic diagram of the structure of an integrated chip provided in Embodiment 5 of the present invention; Figure 7 A schematic diagram of the manufacturing process of the integrated chip structure provided in Example 6 of the present invention; Figure 8 A schematic diagram of a process of preparing an integrated device on a device preparation layer in the manufacturing process of an integrated chip structure provided in Example 6 of the present invention; In the accompanying drawings, the components represented by the reference numerals are listed as follows: 1. Composite epitaxial structure; 11. Bottom layer; 111. Substrate; 112. High heat dissipation layer; 12. SiC isolation layer; 13. Device preparation layer; 2. High-voltage device region; 21. First N-type well region; 22. P-body region; 23. First gate; 24. First P+ region; 25. First N+ region; 26. First source; 27. Second N+ region; 28. First drain; 3. Low voltage device area; 31, P-type MOS region; 311, second N-type well region; 312, second P+ region; 313, third P+ region; 314, third N+ region; 315, second source; 316, second gate; 317, second drain; 32, N-type MOS region; 321, first P-type well region; 322, fourth P+ region; 323, fourth N+ region; 324, fifth N+ region; 325, third source; 326, third drain; 327, third gate; 4. BJT region; 41. third N-type well region; 42. second P-type well region; 43. sixth N+ region; 44. fifth P+ region; 45. sixth P+ region; 46. base; 47. emitter; 48. collector; 49. third P-type well region; 410. fourth N-type well region; 411. seventh P+ region; 412. seventh N+ region; 413. eighth N+ region; 5. Isolation area; 6. Shallow trench isolation; 7. Interlayer dielectric layer; 8. Gate oxide dielectric layer. DETAILED DESCRIPTION

[0022] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0023] In the prior art, the development status and existing defects of power devices are as follows: 1. At present, the driving circuits and protection circuits used with silicon carbide power devices are still silicon-based, which limits the application scope of power devices.

[0024] 2. The cost of developing integrated chips on SiC is too high. The current mainstream SiC wafer is a 6-inch 4H-SiC wafer. On the one hand, the price of the wafer itself is relatively high. On the other hand, the smaller wafer size brings higher process costs.

[0025] 3. Currently, the wafer size used in Si advanced processes is mostly 12 inches. Therefore, the 6-inch 4H-SiC wafer limits the application of more advanced processes.

[0026] 4. When performing monolithic integration on a SiC wafer, there is serious voltage and current crosstalk between the device areas, which will seriously affect the performance of the chip, so a more complex isolation structure needs to be designed.

[0027] Based on this, the present invention provides a new integrated chip structure and a manufacturing method thereof.

[0028] The following embodiments of the present invention are further described in detail in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention but cannot be used to limit the scope of the present invention.

[0029] It should be noted that the terms "first" and "second" and the like in the specification, claims and drawings of this application are used to distinguish different objects rather than to limit a specific order.

[0030] Example 1 like Figure 1 As shown, this embodiment provides an integrated chip structure, including: a composite epitaxial structure 1, an interlayer dielectric layer 7, a high-voltage device region 2, a low-voltage device region 3 and a BJT region 4.

[0031] The high voltage device region 2 , the low voltage device region 3 and the BJT region 4 are isolated from each other and are arranged in the upper region of the composite epitaxial structure 1 and in the interlayer dielectric layer 7 .

[0032] In this embodiment, the interlayer dielectric layer 7 is disposed on the upper surface of the composite epitaxial structure 1 .

[0033] The high voltage device area 2 , the low voltage device area 3 and the BJT area 4 are isolated from each other by forming an isolation area 5 through an isolation trench.

[0034] The high voltage device region 2 is used to form a high voltage device, the low voltage device region 3 is used to form a low voltage device, and the BJT region 4 is used to form a bipolar junction transistor.

[0035] Among them, Figure 2 As shown, the composite epitaxial structure 1 includes a bottom layer 11, a SiC isolation layer 12 and a device preparation layer 13 which are stacked in sequence along the vertical direction; the SiC isolation layer 12 is bonded on the bottom layer 11, and a bonding interface layer is formed between the SiC isolation layer 12 and the bottom layer 11; the device preparation layer 13 is epitaxially arranged on the SiC isolation layer 12, and is used to manufacture a high-voltage device area 2, a low-voltage device area 3 and a BJT area 4.

[0036] In this embodiment, if Figure 2 As shown, the bottom layer 11 includes a Si substrate 111 and a high heat dissipation layer 112 epitaxially grown on the Si substrate; the high heat dissipation layer 112 is a 3C-SiC epitaxial layer.

[0037] The device preparation layer 13 is a 3C-SiC epitaxial layer or a 4H-SiC epitaxial layer.

[0038] Furthermore, in a specific example, Figure 1 As shown, the high voltage device region 2 is formed with a first N-type well region 21 and a P-body region 22; and, a first P+ region 24 and a first N+ region 25 formed in a top region of the P-body region 22; A gate oxide dielectric layer 8 formed on the device preparation layer 13; A first gate 23 is formed on the gate oxide dielectric layer 8 above the P-body region 22 between the first N-type well region 21 and the first N+ region 25, and the first gate 23 partially covers the first N-type well region 21 and the first N+ region 25; A first source electrode 26 penetrating the interlayer dielectric layer 7 and the gate oxide dielectric layer 8 and connected to the first P+ region 24 and the first N+ region 25; A second N+ region 27 formed in the top region of the first N-type well region 21; A first drain electrode 28 is disposed through the interlayer dielectric layer 7 and the gate oxide dielectric layer 8 and connected to the second N+ region 27 .

[0039] The low voltage device region 3 includes a P-type MOS region 31 and an N-type MOS region 32 which are arranged in the device preparation layer 13 at intervals.

[0040] The P-type MOS region 31 is formed with a second N-type well region 311; and, a second P+ region 312 , a third P+ region 313 , and a third N+ region 314 formed in the top region of the second N-type well region 311 ; A second drain electrode 317 penetrating the interlayer dielectric layer 7 and the gate oxide dielectric layer 8 and connected to the second P+ region 312; A second source 315 penetrating the interlayer dielectric layer 7 and the gate oxide dielectric layer 8 and connected to the third P+ region 313 and the third N+ region 314; A second gate 316 is formed on the gate oxide dielectric layer 8 above the P-body region 22 between the second P+ region 312 and the third P+ region 313 , and the second gate 316 partially covers the second P+ region 312 and the third P+ region 313 .

[0041] The N-type MOS region 32 is formed with a first P-type well region 321; and, a fourth P+ region 322, a fourth N+ region 323 and a fifth N+ region 324 formed in the top region of the first P-type well region 321; A third source 325 penetrating the interlayer dielectric layer 7 and the gate oxide dielectric layer 8 and connected to the fourth P+ region 322 and the fourth N+ region 323; A third drain electrode 326 penetrating the interlayer dielectric layer 7 and the gate oxide dielectric layer 8 and connected to the fifth N+ region 324; A third gate 327 is formed on the gate oxide dielectric layer 8 above the P-body region between the fourth N+ region 323 and the fifth N+ region 324 , and the third gate 327 partially covers the fourth N+ region 323 and the fifth N+ region 324 .

[0042] It should be noted that, in this embodiment, the device preparation layer is P-type epitaxial, and the BJT region 4 is formed with a third N-type well region 41 and a second P-type well region 42; and, a sixth N+ region 43 and a fifth P+ region 44 are formed in the top area of ​​the third N-type well region 41; a sixth P+ region 45 is formed in the top area of ​​the second P-type well region 42; a base 46 is penetrated through the interlayer dielectric layer 7 and the gate oxide dielectric layer 8 and connected to the sixth N+ region 43; an emitter 47 is penetrated through the interlayer dielectric layer 7 and the gate oxide dielectric layer 8 and connected to the fifth N+ region 44; and a collector 48 is penetrated through the interlayer dielectric layer 7 and the gate oxide dielectric layer 8 and connected to the fourth N+ region 323.

[0043] In summary, the integrated chip structure provided in this embodiment first epitaxially grows a 3C-SiC epitaxial layer on a Si substrate, then bonds a semi-insulating (HPSI) SiC peeling film on the structure, and then epitaxially grows a 3C-SiC epitaxial layer on the surface, and integrates the device structure in the 3C-SiC epitaxial layer on the surface; the wafer size of the composite sheet made by this scheme can be 12 inches, which is much larger than the size of the current mainstream 4H-SiC wafer, thereby reducing the overall process cost and being able to adopt advanced processes in Si integrated circuits; because 3C-SiC is a high heat dissipation layer, it can effectively improve the thermal characteristics of the device. In addition, after bonding the semi-insulating (HPSI) SiC peeling film, an isolation layer is naturally formed, which can effectively prevent the occurrence of current and voltage crosstalk.

[0044] Example 2 Based on Example 1, the difference from Example 1 is that: In this embodiment, if Figure 3 As shown, the device preparation layer on the surface can also be N-type, and accordingly, the device structure will have certain changes (BJT area); Specifically, when the device preparation layer is N-type epitaxial, the BJT region 4 is formed with a third P-type well region 49 and a fourth N-type well region 410; and, a seventh P+ region 411, a seventh N+ region 412 and an eighth N+ region 413 are formed in the top area of ​​the third P-type well region 49; a base electrode is penetrated through the interlayer dielectric layer 7 and the gate oxide dielectric layer 8 and connected to the seventh P+ region 411; an emitter electrode is penetrated through the interlayer dielectric layer 7 and the gate oxide dielectric layer 8 and connected to the seventh N+ region 412; and a collector electrode is penetrated through the interlayer dielectric layer 7 and the gate oxide dielectric layer 8 and connected to the eighth N+ region 413.

[0045] For the rest of the same structures, please refer to the introduction of Example 1 and will not be repeated here.

[0046] Example 3 Based on Example 1, the difference from Example 1 is that: In this embodiment, if Figure 4 As shown, the bottom layer 11 is a 3C-SiC polycrystalline substrate.

[0047] Specifically, a 3C-SiC polycrystalline substrate is used instead of epitaxially growing a 3C-SiC epitaxial layer on a Si substrate. The polycrystalline 3C-SiC substrate is cheap and has high mechanical strength.

[0048] For the rest of the same structures, please refer to the introduction of Example 1 and will not be repeated here.

[0049] Example 4 Based on Example 1, the difference from Example 1 is that: like Figure 5 As shown, a shallow trench isolation (STI) 6 may be introduced between the NMOS region and the PMOS region of the low voltage device region to avoid crosstalk between the NMOS and the PMOS.

[0050] For the rest of the same structures, please refer to the introduction of Example 1 and will not be repeated here.

[0051] Example 5 Based on Example 1, the difference from Example 1 is that: like Figure 6 As shown, the isolation between different device regions can adopt PN junction isolation instead of trench isolation, and by grounding the epitaxial layer, it is ensured that the PN junction between the deep N-well region and the epitaxial layer will not be forward biased.

[0052] For the rest of the same structures, please refer to the introduction of Example 1 and will not be repeated here.

[0053] Example 6 This embodiment provides a method for manufacturing the integrated chip structure provided in Embodiment 1, such as Figure 7 As shown, the operation is as follows: Step S1: epitaxially grow a 3C-SiC epitaxial layer on a Si substrate to obtain a 3C-SiC substrate.

[0054] Next, the semi-insulating (HPSI) SiC wafer is bonded to the surface of the 3C-SiC epitaxial layer through the Smart-cut process. The bonding equipment and process can use the wafer bonding process equipment with SAB (surface activation bonding) technology to avoid defects, oxide layers or amorphous layers at the bonding interface; the bonding interface is further repaired and enhanced through annealing and other treatment methods; the specific process flow includes the following steps S2 to S5: Step S2: H+ injection is performed on the surface of the semi-insulating SiC wafer to form an H+ aggregation layer.

[0055] Step S3: Clean the surface of the 3C-SiC substrate and the semi-insulating SiC wafer.

[0056] Step S4: flipping the semi-insulating SiC wafer and bonding it to the 3C-SiC substrate, and strengthening the bonding strength at 150° C.; Step S5: peeling the semi-insulating SiC wafer along the H+ aggregation layer at 300° C., annealing at 1100° C. to enhance the bonding strength, and polishing the wafer surface; Step S6: epitaxially growing a 3C epitaxial layer to form a device preparation layer; Step S7: preparing an integrated device on the device preparation layer; Among them, the device preparation layer includes a high-voltage device area, a low-voltage device area and a BJT area; a high-voltage device is formed in the high-voltage device area, a low-voltage device is formed in the low-voltage device area, and a bipolar junction transistor is formed in the BJT area.

[0057] Specifically, in this embodiment, a P-type epitaxial layer is taken as an example. Figure 8 As shown, step S7 specifically includes: Step S701: forming a plurality of N-type well regions (N-well), P-type well regions (P-well), P-body regions, N-type heavily doped regions (N+) and P-type heavily doped regions (P+) in the device preparation layer by multiple ion implantations; Step S702: growing a gate oxide dielectric layer by thermal oxidation; Step S703: forming a polysilicon gate by deposition and etching; Step S704: forming an isolation trench by etching and filling a dielectric, or using PN junction isolation; Step S705: growing an interlayer dielectric layer and etching metal through holes; Step S706: depositing metal and etching to form metal electrodes.

[0058] In summary, the integrated chip structure and the corresponding manufacturing method provided in the above embodiments 1 to 6 have the following technical effects: the composite epitaxial structure is to first epitaxially grow a 3C-SiC epitaxial layer on a Si substrate, then bond a semi-insulating (HPSI) SiC peeling film on the structure, and then epitaxially grow a 3C-SiC or 4H-SiC epitaxial layer on the surface; finally, the device structure is integrated in the 3C-SiC or 4H-SiC epitaxial layer on the surface - the high-voltage device area, the low-voltage device area and the BJT area are isolated from each other and arranged in the upper area of ​​the composite epitaxial structure, the high-voltage device area is used to form a high-voltage device, the low-voltage device area is used to form a low-voltage device, and the BJT area is used to form a bipolar junction transistor.

[0059] The wafer size obtained by using the above-mentioned composite epitaxial structure can reach 12 inches, which is much larger than the size of the current mainstream 4H-SiC wafer, thereby reducing the overall process cost and being able to adopt advanced processes in Si integrated circuits. In addition, after the bonded semi-insulating (HPSI) SiC peeling film, a SiC isolation layer is naturally formed, which can effectively prevent the occurrence of current and voltage crosstalk.

[0060] In the description of this specification, the description with reference to the terms "specific example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present invention. In this specification, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples, unless they are contradictory.

[0061] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An integrated chip structure, characterized in that: include: Composite epitaxial structure, interlayer dielectric layer, high voltage device area, low voltage device area and BJT area; The interlayer dielectric layer is arranged on the upper surface of the composite epitaxial structure; The high voltage device area, the low voltage device area and the BJT area are isolated from each other and are arranged in the upper area of ​​the composite epitaxial structure and the interlayer dielectric layer; The high-voltage device area is used to form a high-voltage device, the low-voltage device area is used to form a low-voltage device, and the BJT area is used to form a bipolar junction transistor; Among them, the composite epitaxial structure includes a bottom layer, a SiC isolation layer and a device preparation layer which are stacked in sequence along the vertical direction; the SiC isolation layer is bonded on the bottom layer, and a bonding interface layer is formed between the SiC isolation layer and the bottom layer; the device preparation layer is epitaxially arranged on the SiC isolation layer, and is used to manufacture the high-voltage device area, the low-voltage device area and the BJT area.

2. The integrated chip structure according to claim 1, characterized in that: The high voltage device region is formed with a first N-type well region and a P-body region; and, a first P+ region and a first N+ region formed in a top region of the P-body region; A gate oxide dielectric layer formed above the device preparation layer; A first gate is formed on the gate oxide dielectric layer above the P-body region between the first N-type well region and the first N+ region, and the first gate partially covers the first N-type well region and the first N+ region; A first source electrode penetrating the interlayer dielectric layer and the gate oxide dielectric layer and connected to the first P+ region and the first N+ region; a second N+ region formed in a top region of the first N-type well region; A first drain electrode is provided through the interlayer dielectric layer and the gate oxide dielectric layer and connected to the second N+ region.

3. The integrated chip structure according to claim 2, characterized in that: The low voltage device region includes a P-type MOS region and an N-type MOS region which are arranged at intervals in the device preparation layer.

4. The integrated chip structure according to claim 3, characterized in that: The P-type MOS region is formed with a second N-type well region; and, a second P+ region, a third P+ region and a third N+ region formed in a top region of the second N-type well region; A second drain electrode penetrating the interlayer dielectric layer and the gate oxide dielectric layer and connected to the second P+ region; A second source electrode penetrating the interlayer dielectric layer and the gate oxide dielectric layer and connected to the third P+ region and the third N+ region; A second gate is formed on the gate oxide dielectric layer above the P-body region between the second P+ region and the third P+ region, and the second gate partially covers the second P+ region and the third P+ region.

5. The integrated chip structure according to claim 3, characterized in that: The N-type MOS region is formed with a first P-type well region; and, a fourth P+ region, a fourth N+ region and a fifth N+ region formed in the top region of the first P-type well region; A third source electrode penetrating the interlayer dielectric layer and the gate oxide dielectric layer and connected to the fourth P+ region and the fourth N+ region; a third drain electrode penetrating the interlayer dielectric layer and the gate oxide dielectric layer and connected to the fifth N+ region; A third gate is formed on the gate oxide dielectric layer above the P-body region between the fourth N+ region and the fifth N+ region, and the third gate partially covers the fourth N+ region and the fifth N+ region.

6. The integrated chip structure according to claim 2, characterized in that: When the device preparation layer is a P-type epitaxial layer, the BJT region is formed with a third N-type well region and a second P-type well region; and a sixth N+ region and a fifth P+ region formed in the top region of the third N-type well region; a sixth P+ region formed in the top region of the second P-type well region; a base electrode penetrating the interlayer dielectric layer and the gate oxide dielectric layer and connected to the sixth N+ region; an emitter electrode penetrating the interlayer dielectric layer and the gate oxide dielectric layer and connected to the fifth N+ region; a collector electrode penetrating the interlayer dielectric layer and the gate oxide dielectric layer and connected to the fourth N+ region; When the device preparation layer is an N-type epitaxial layer, the BJT region is formed with a third P-type well region and a fourth N-type well region; And, a seventh P+ region, a seventh N+ region and an eighth N+ region formed in the top area of ​​the third P-type well region; a base electrode penetrating the interlayer dielectric layer and the gate oxide dielectric layer and connected to the seventh P+ region; an emitter electrode penetrating the interlayer dielectric layer and the gate oxide dielectric layer and connected to the seventh N+ region; and a collector electrode penetrating the interlayer dielectric layer and the gate oxide dielectric layer and connected to the eighth N+ region.

7. The integrated chip structure according to claim 1, characterized in that: The bottom layer includes a Si substrate and a high heat dissipation layer epitaxially grown on the Si substrate; the high heat dissipation layer is a 3C-SiC epitaxial layer; Alternatively, the bottom layer is a 3C-SiC polycrystalline substrate.

8. The integrated chip structure according to claim 1, characterized in that: The device preparation layer is a 3C-SiC or 4H-SiC epitaxial layer.

9. A method for manufacturing an integrated chip structure as claimed in any one of claims 1 to 8, characterized in that: include: epitaxially growing a 3C-SiC epitaxial layer on a Si substrate to obtain a 3C-SiC substrate; H+ is injected into the surface of the semi-insulating SiC wafer to form an H+ aggregation layer; Cleaning 3C-SiC substrate and semi-insulating SiC wafer surface; Flip the semi-insulating SiC wafer to bond with the 3C-SiC substrate and strengthen the bonding strength at 150°C; The semi-insulating SiC wafer was peeled off along the H+ aggregation layer at 300°C, annealed at 1100°C to strengthen the bonding strength, and the wafer surface was polished; Epitaxially growing a 3C or 4H-SiC epitaxial layer to form a device preparation layer; preparing an integrated device on the device preparation layer; Wherein, the device preparation layer includes a high-voltage device area, a low-voltage device area and a BJT area; a high-voltage device is formed in the high-voltage device area, a low-voltage device is formed in the low-voltage device area, and a bipolar junction transistor is formed in the BJT area.

10. The manufacturing method according to claim 9, characterized in that: The step of preparing an integrated device on the device preparation layer specifically includes: By multiple ion implantations, a plurality of N-type well regions, P-type well regions, P-body regions, N-type heavily doped regions and P-type heavily doped regions are formed in the device preparation layer; growing a gate oxide dielectric layer by thermal oxidation; forming a polysilicon gate by deposition and etching; An isolation trench is formed by etching and filling a dielectric, or a PN junction isolation is used; growing an interlayer dielectric layer and etching metal vias; Metal is deposited and etched to form metal electrodes.

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