A semiconductor device, a manufacturing method thereof, and an electronic device

Abstract

A semiconductor device, a manufacturing method thereof, and an electronic device. The manufacturing method includes: providing a semiconductor substrate, the semiconductor substrate including a photoelectric conversion region and a transistor region, a gate electrode being formed on the semiconductor substrate of the transistor region; forming a dielectric layer on the surfaces of the semiconductor substrate and the gate electrode; forming a patterned hard mask layer on the surface of the dielectric layer located on the sidewalls of the photoelectric conversion region and the gate electrode; etching the dielectric layer based on the hard mask layer to remove the dielectric layer formed on the top of the gate electrode and on the surface of the semiconductor substrate in the transistor region, obtaining an offset sidewall formed by the dielectric layer formed on the sidewall of the gate electrode, and a protective layer formed by the dielectric layer formed in the photoelectric conversion region. The present invention can avoid damaging the semiconductor substrate during the formation of the offset sidewall.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more particularly to a semiconductor device, a manufacturing method thereof, and an electronic device. Background Art

[0002] A CMOS image sensor (CIS) is a semiconductor device that converts optical signals into electrical signals. It is widely used in fields such as mobile phones, digital cameras, security monitoring, medical imaging, and automotive electronics, and has advantages such as low power consumption, high integration, good compatibility, and strong anti-noise ability.

[0003] A CMOS image sensor typically includes a transistor region and a photoelectric conversion region, each of which undertakes different functions and jointly completes the capture and processing of images. Among them, the photoelectric conversion region is mainly responsible for capturing optical signals and converting them into electrical signals, and the transistor region is mainly responsible for controlling the operation of the photoelectric conversion region and performing signal processing on the electrical signals.

[0004] When forming offset sidewalls on both sides of the gate electrode in the transistor region, a common method is to form a photoresist layer in the photoelectric conversion region and use the photoresist layer as a mask to perform dry etching on the offset sidewalls of the transistor region. However, the photoresist has poor plasma resistance and cannot effectively resist the erosion of etching gases, so the protection of the photoelectric conversion region is insufficient, and the plasma during the dry etching process is also likely to damage the surface of the semiconductor substrate in the transistor region. Summary of the Invention

[0005] A series of simplified concepts are introduced in the Summary of the Invention section, which will be further described in detail in the Detailed Description section. The Summary of the Invention section of the present invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the protection scope of the claimed technical solution.

[0006] In view of the existing problems, an embodiment of the present invention provides a manufacturing method of a semiconductor device, including:

[0007] Providing a semiconductor substrate, the semiconductor substrate including a photoelectric conversion region and a transistor region, and a gate electrode is formed on the semiconductor substrate of the transistor region;

[0008] Forming a dielectric layer on the surfaces of the semiconductor substrate and the gate electrode;

[0009] Forming a patterned hard mask layer on the surface of the dielectric layer located on the sidewalls of the photoelectric conversion region and the gate electrode;

[0010] Etch the dielectric layer based on the hard mask layer to remove the dielectric layer formed on top of the gate electrode and on the surface of the semiconductor substrate in the transistor region, obtaining an offset sidewall formed by the dielectric layer formed on the sidewalls of the gate electrode and a protective layer formed by the dielectric layer in the photoelectric conversion region.

[0011] In one embodiment, forming a patterned hard mask layer on the surface of the dielectric layer located on the sidewalls of the photoelectric conversion region and the gate electrode includes:

[0012] Deposit a hard mask layer on the dielectric layer;

[0013] Form a photoresist layer on the hard mask layer in the photoelectric conversion region;

[0014] Use the photoresist layer as a mask to perform dry etching on the hard mask layer to remove the hard mask layer formed on top of the gate electrode and on the surface of the semiconductor substrate in the transistor region, obtaining the patterned hard mask layer; and,

[0015] Remove the photoresist layer.

[0016] In one embodiment, the dry etching also removes a part of the dielectric layer.

[0017] In one embodiment, after depositing the hard mask layer and before forming the photoresist layer, the method further includes:

[0018] Perform a scrub cleaning process on the surface of the hard mask layer.

[0019] In one embodiment, etching the dielectric layer based on the hard mask layer includes:

[0020] Etch the dielectric layer using a wet etching process.

[0021] In one embodiment, after etching the dielectric layer based on the hard mask layer, the method further includes:

[0022] Remove the hard mask layer using a wet etching process.

[0023] In one embodiment, the dielectric layer includes a silicon oxide layer, and the hard mask layer includes a silicon nitride layer and / or a silicon oxynitride layer.

[0024] In one embodiment, after forming the offset sidewall, the method further includes:

[0025] Perform a lightly doped ion implantation on the semiconductor substrate in the transistor region based on the offset sidewall to form lightly doped drain regions on both sides of the gate electrode.

[0026] On the other hand, an embodiment of the present invention provides a semiconductor device, which is manufactured by using the method described above.

[0027] Another aspect of an embodiment of the present invention provides an electronic device, which includes the semiconductor device described above.

[0028] According to the semiconductor device, its manufacturing method, and the electronic device provided by the present invention, a patterned hard mask layer is formed on the dielectric layer, and the hard mask layer is used instead of the photoresist layer as a mask during the process of etching the dielectric layer to form an offset sidewall, which can not only avoid plasma damage to the semiconductor substrate surface of the transistor region, but also better protect the optoelectronic conversion region. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The following drawings of the present invention are used as a part of the present invention to understand the present invention. The embodiments of the present invention shown in the drawings and their descriptions are used to explain the principles of the present invention.

[0030] In the drawings:

[0031] Figures 1A to 1B A cross-sectional schematic diagram of a semiconductor device obtained by successively implementing each step of a manufacturing method of a semiconductor device according to the related art is shown;

[0032] Figure 2 A schematic flowchart of a manufacturing method of a semiconductor device according to a specific embodiment of the present invention is shown;

[0033] Figures 3A to 3F A cross-sectional schematic diagram of a semiconductor device obtained by successively implementing each step of a manufacturing method of a semiconductor device according to a specific embodiment of the present invention is shown. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0034] In the following description, a large number of specific details are given to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, some technical features well known to those skilled in the art are not described to avoid confusion with the present invention.

[0035] It should be understood that the present invention can be implemented in different forms and should not be construed as limited to the embodiments presented herein. On the contrary, these embodiments are provided to make the disclosure thorough and complete, and to fully convey the scope of the present invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0036] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or portions, these elements, components, regions, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Thus, a first element, component, region, layer or portion discussed below may be denoted as a second element, component, region, layer or portion without departing from the teachings of the present invention.

[0037] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience in describing the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "below" other elements or features will be oriented "on" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientation) and the spatial descriptors used herein are to be interpreted accordingly.

[0038] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present invention. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0039] As Figure 1A and Figure 1BAs shown, the CMOS image sensor includes a photoelectric conversion region and a transistor region, which can be isolated by a shallow trench isolation structure 101. A gate electrode 102 is formed on the semiconductor substrate 100 in the transistor region. When forming an offset spacer on the sidewall of the gate electrode 102, the common practice is to first form a dielectric layer 103 covering the photoelectric conversion region and the transistor region, then form a photoresist layer 104 on the dielectric layer 103 in the photoelectric conversion region, and then etch the dielectric layer 103 in the transistor region using the photoresist layer 104 as a mask, so as to form an offset sidewall 103a on the sidewall of the gate electrode 102, which is used to protect the sidewall of the gate electrode 102 and serve as a self-alignment process for the subsequent formation of a lightly doped drain (LDD). The dielectric layer 103 in the photoelectric conversion region is retained due to the coverage of the photoresist layer 104 and serves as a protective layer 103b for the photoelectric conversion region.

[0040] In the above process flow, there are mainly the following two problems: First, the plasma resistance of the photoresist layer is poor and it cannot effectively resist the erosion of the etching gas, so the protection of the photoelectric conversion region is insufficient; Second, when using the dry etching process to etch the dielectric layer 103 in the transistor region, the plasma used for etching is likely to damage the surface of the semiconductor substrate in the transistor region.

[0041] In view of the existence of the foregoing technical problems, an embodiment of the present invention proposes a method for manufacturing a semiconductor device. Next, refer to Figures 2 to 3F A detailed description is given of the method for manufacturing a semiconductor device according to an embodiment of the present invention. Among them, Figure 2 shows a schematic flow chart of the method for manufacturing a semiconductor device according to a specific embodiment of the present invention, Figures 3A to 3F shows a cross-sectional schematic diagram of the semiconductor device obtained by successively implementing each step of the method for manufacturing a semiconductor device according to a specific embodiment of the present invention.

[0042] First, step S201 is executed. As Figure 3A shown, a semiconductor substrate 300 is provided. The semiconductor substrate 300 includes a photoelectric conversion region and a transistor region. A gate electrode 302 is formed on the semiconductor substrate 300 in the transistor region.

[0043] Among them, the material of the semiconductor substrate 300 includes but is not limited to at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, or is silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI).

[0044] The CMOS image sensor includes a pixel region and a logic region. The pixel region includes a photoelectric conversion region and a pixel transistor region. The photoelectric conversion region is used to form a photodiode (PD). The photodiode is used for photoelectric conversion. When it is illuminated, electron transition occurs, converting the optical signal into an electrical signal. The pixel transistor region is used to form pixel transistors, which are mainly used to control charge transfer, reset, and signal readout in the photoelectric conversion region; the pixel transistors are usually MOSFET transistors. The logic region is used to form logic transistors, which are mainly used to implement relatively complex digital logic operations and signal processing; the logic transistors are usually CMOS transistors.

[0045] It can be understood that the photoelectric conversion region in the embodiments of the present invention is the photoelectric conversion region in the pixel region. The transistor region can be the pixel transistor region in the pixel region or the logic region (or referred to as the logic transistor region). Exemplarily, the photoelectric conversion region and the transistor region are isolated by a shallow trench isolation structure 301.

[0046] A gate electrode 302 is formed on the semiconductor substrate 300 of the transistor region. The material of the gate electrode 302 includes one or more of a polysilicon layer, a metal layer, a conductive metal nitride layer, a conductive metal oxide layer, and a metal silicide layer. Exemplarily, a gate dielectric layer is further formed between the semiconductor substrate 300 and the gate electrode 302. The gate dielectric layer includes a silicon oxide layer, and the gate dielectric layer can be formed by a thermal oxidation growth process or a chemical vapor deposition process; the gate dielectric layer can also include a high-k gate dielectric layer, and its material can be selected, for example, from TiO2, Al2O3, ZrO2, HfO2, Ta2O5, La2O3, etc. Exemplarily, before forming the gate electrode 302, ion implantation can also be performed on the semiconductor substrate 300 of the photoelectric conversion region to form pixel units.

[0047] Next, step S202 is executed to form a dielectric layer 303 on the surfaces of the semiconductor substrate 300 and the gate electrode 302.

[0048] Specifically, the dielectric layer 303 is formed on the upper surface of the semiconductor substrate 300 of the transistor region, the top and sidewalls of the gate electrode 302, the upper surface of the semiconductor substrate 300 of the photoelectric conversion region, and the upper surface of the shallow trench isolation structure 301. Among them, the dielectric layer 303 can include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric layer, etc. In one example, TEOS (tetraethyl orthosilicate) can be used as a precursor material to perform a chemical vapor deposition (CVD) process to form a silicon dioxide layer as the dielectric layer 303. After TEOS enters the reaction chamber, it decomposes into silicon dioxide and by-products at high temperature, and the silicon dioxide is deposited on the surfaces of the gate electrode 302 and the semiconductor substrate 300 to form a uniform thin film.

[0049] Exemplarily, before forming the dielectric layer 303, a pre-cleaning process may also be performed to remove contaminants and native oxides on the wafer surface, activate the chemical activity of the wafer surface, and improve the quality and adhesion of the deposited dielectric layer 303.

[0050] Next, step S203 is performed to form a patterned hard mask layer 304 on the surface of the dielectric layer 303 located on the sidewalls of the optoelectronic conversion region and the gate electrode 302.

[0051] Among them, the material of the hard mask layer 304 is different from that of the dielectric layer 303, and there is a certain etching selectivity between the two. Exemplarily, when the dielectric layer 303 is a silicon oxide layer, the hard mask layer 304 may be a silicon nitride layer or a silicon oxynitride layer.

[0052] Such as Figure 3A and Figure 3B As shown, the steps of forming the patterned hard mask layer 304 specifically include: First, deposit the hard mask layer 304 on the dielectric layer 303. The process used to deposit the hard mask layer 304 may include chemical vapor deposition process, physical vapor deposition process, atomic layer deposition process and other commonly used deposition processes in the art.

[0053] Exemplarily, after depositing the hard mask layer 304, a scrubber clean process may also be performed on the surface of the hard mask layer 304 to remove particles and contaminants on its surface, and to change the surface of the hard mask layer 304 from hydrophobic to hydrophilic, improving the contact between the hard mask layer 304 and the subsequently formed photoresist layer.

[0054] Next, a photoresist layer 305 is formed on the hard mask layer 304 located in the optoelectronic conversion region. Specifically, the photoresist layer is spin-coated on the hard mask layer 304, and the photoresist layer is exposed and developed, so as to form a window in the photoresist layer, and the window exposes the underlying transistor region.

[0055] Next, the hard mask layer 304 is dry-etched using the photoresist layer 305 as a mask to remove the hard mask layer 304 formed on the top of the gate electrode 302 and the surface of the semiconductor substrate 300 in the transistor region, and retain the hard mask layer on the sidewalls of the gate electrode 302 and the hard mask layer 304 in the optoelectronic conversion region as the above-mentioned patterned hard mask layer.

[0056] Among them, an anisotropic dry etching process can be used to etch the hard mask layer 304, and the etching direction is perpendicular to the surface of the semiconductor substrate 300. Exemplarily, the dry etching process may include plasma etching, in which reactive radicals in the plasma react chemically with the surface of the material of the hard mask layer 304 to generate volatile products, thereby achieving etching. Alternatively, a reactive ion etching (RIE) process can be used. By applying a radio frequency electric field, the gas is ionized to form a plasma, and the ions bombard the surface of the hard mask layer 304 under the action of the electric field, while the reactive radicals chemically react with the material of the hard mask layer 304 for etching. An ion beam etching (IBE) process can also be used, in which a high-energy ion beam directly bombards the surface of the hard mask layer 304 for etching through physical sputtering.

[0057] The dry etching process etches in the vertical direction. Therefore, in the transistor region, the hard mask layer 304 on the surface of the semiconductor substrate 300 and the hard mask layer 304 on top of the gate electrode 302 are removed because they are perpendicular to the etching direction, while the hard mask layer 304 on the sidewall of the gate electrode 302 is retained because it is parallel to the etching direction. The hard mask layer 304 in the photoelectric conversion region is also retained due to the protection of the photoresist layer 305.

[0058] Furthermore, in the above dry etching process, a preset thickness of the dielectric layer 303 can also be removed. Exemplarily, a dry etching process with high directionality and low etching selectivity can be used for etching, so as to remove the hard mask layer 304 and part of the dielectric layer 303 at the same time. By removing part of the dielectric layer 303 in the dry etching process, the etching time of the subsequent wet etching process can be reduced, and side etching at the bottom of the offset sidewall can be avoided. For details, see the following text.

[0059] Next, as Figure 3C shown, the photoresist layer 305 is removed. Exemplarily, an ashing process, a wet stripping process, or a combination of the two can be used to remove the photoresist layer 305. The ashing process refers to oxidizing and decomposing the photoresist layer through oxygen plasma, and the wet stripping process refers to dissolving the photoresist layer with chemical reagents such as sulfuric acid-hydrogen peroxide solution, organic solvents, alkaline solutions, and ozone solutions.

[0060] Next, step S204 is executed, as Figure 3DAs shown, the dielectric layer 303 is etched based on the patterned hard mask layer 304 to remove the dielectric layer formed on top of the gate electrode 302 and on the surface of the semiconductor substrate 300 in the transistor region, resulting in an offset sidewall 303a composed of the dielectric layer 303 formed on the sidewalls of the gate electrode 302, and a protective layer 303b composed of the dielectric layer 303 formed in the photoelectric conversion region.

[0061] As described above, in the previous process, the dielectric layer was etched using the photoresist layer located in the photoelectric conversion region as a mask. In order to remove the dielectric layer on top of the gate electrode and on the surface of the semiconductor substrate while retaining the dielectric layer on the sidewalls of the gate electrode as an offset sidewall, an anisotropic dry etching process needs to be used to ensure that the etching direction is perpendicular to the surface of the semiconductor substrate. Therefore, in order to ensure the directionality of the plasma during the etching process, high-energy plasma needs to be used to bombard the dielectric layer, which is likely to cause plasma damage to the surface of the semiconductor substrate.

[0062] In the embodiment of the present invention, the dielectric layer 303 on the sidewalls of the gate electrode 302 and the dielectric layer 303 in the photoelectric conversion region are protected by the patterned hard mask layer 304, while the dielectric layer 303 on top of the gate electrode 302 and the dielectric layer 303 on the surface of the semiconductor substrate 300 in the device region are exposed. Therefore, an isotropic wet etching process can be used to etch the dielectric layer 303, thereby avoiding damage to the surface of the semiconductor substrate 300 caused by the high-energy plasma used in dry etching; at the same time, the hard mask layer 304 can better shield the photoelectric conversion region compared to the photoresist layer, avoiding ions from penetrating the mask and injecting into the photoelectric conversion region, which affects the performance of the image sensor.

[0063] Exemplarily, when the material of the dielectric layer 303 is silicon oxide and the material of the hard mask layer 304 is silicon nitride or silicon oxynitride, the etchant used in the wet etching process may include diluted hydrofluoric acid (DHF) or buffered oxide etchant (BOE), etc.

[0064] Optionally, in addition to using the wet etching process, a dry etching process can also be used to etch the dielectric layer, and damage to the surface of the semiconductor substrate 300 can be avoided by reducing the bombardment energy of the plasma, etc. Since the embodiment of the present invention reduces the requirement for etching directionality through the hard mask layer 304, reducing the bombardment energy of the plasma will not affect the morphology of the finally formed offset sidewall 303a.

[0065] When an isotropic etching process is adopted, the etching direction includes not only the vertical direction but also the horizontal direction. If the etching time is too long, there may be lateral etching of the dielectric layer 303 under the hard mask layer 304, resulting in a depression at the bottom of the offset sidewall 303a, that is, the side etching phenomenon occurs. In the embodiment of the present invention, in the previous dry etching process, a preset thickness of the dielectric layer 303 is removed, thereby reducing the etching amount required for wet etching, reducing the wet etching time, and effectively avoiding the occurrence of the side etching phenomenon.

[0066] In addition, it should be noted that in the embodiment of the present invention, it is not required to completely remove the dielectric layer 303 on the top of the gate electrode 302 and the surface of the semiconductor substrate 300 in the device region. A relatively thin dielectric layer 303 may also be retained to protect the semiconductor substrate 300 and the gate electrode 302 in the subsequent ion implantation process. Exemplarily, the thickness of the retained dielectric layer 303 is not greater than 50 angstroms.

[0067] As Figure 3E shown, after the wet etching of the dielectric layer 303 is completed, the remaining hard mask layer 304 can also be removed by a wet etching process. For example, the hard mask layer 304 can be removed by using a hot phosphoric acid solution. Removing the hard mask layer 304 by a wet etching process can avoid plasma damage to the surface of the semiconductor substrate 300.

[0068] Finally, as Figure 3F shown, based on the offset sidewall 303a, a lightly doped ion implantation is performed on the semiconductor substrate 300 in the transistor region to form lightly doped drain regions 306 on both sides of the gate electrode 302. The lightly doped drain (LDD) can reduce the peak electric field near the drain by introducing a lightly doped region between the drain and the channel, thereby reducing the generation and injection of hot carriers, and forming a more gentle electric field gradient by adjusting the doping distribution at the channel edge, enhancing the gate's control ability over the channel, alleviating the short-channel effect, and being able to increase the breakdown voltage and reduce the leakage current.

[0069] During the lightly doped ion implantation process, due to the blocking effect of the offset sidewall 303a on the doped ions, there is a distance between the formed lightly doped drain regions 306 and the channel of the transistor device, and the doped ions will not reduce the width of the channel due to subsequent annealing diffusion. In addition, the relatively thick protective layer 303b in the photoelectric conversion region can protect the photoelectric conversion region from being contaminated by the LDD doped ions, and avoid damage to the surface of the semiconductor substrate 300 in the photoelectric conversion region caused by the ion implantation process.

[0070] Thus far, the process steps implemented according to the manufacturing method of the semiconductor device in the first aspect embodiment of the present invention have been completed. It can be understood that the semiconductor device manufacturing method in this embodiment not only includes the above steps, but may also include other necessary steps before, during, or after the above steps, and all of them are included in the scope of the manufacturing method in this embodiment. For example, main sidewalls can also be formed on both sides of the offset sidewall 303a, and the semiconductor substrate can be ion-implanted based on the main sidewalls to form source and drain electrodes.

[0071] According to the manufacturing method of the semiconductor device provided by the embodiments of the present invention, a patterned hard mask layer is formed on the dielectric layer, and the hard mask layer is used instead of the photoresist layer as a mask during the process of etching the dielectric layer to form an offset sidewall. This can not only avoid plasma damage to the surface of the semiconductor substrate in the transistor region, but also better protect the optoelectronic conversion region.

[0072] The embodiments of the present invention also provide a semiconductor device, which can be prepared by the method in the foregoing embodiments, but is not limited thereto.

[0073] Next, a detailed introduction and description of the semiconductor device of the present invention will be given. It is worth mentioning that, in order to avoid repetition, only a brief description will be given for the same components and structures as those in the foregoing embodiments, and the specific explanations and descriptions can refer to the descriptions in Embodiment 1.

[0074] Specifically, as Figure 3F shown, the semiconductor device of the embodiment of the present invention includes a semiconductor substrate 300. The semiconductor substrate 300 includes an optoelectronic conversion region and a transistor region. A gate electrode 302 is formed on the semiconductor substrate 300 in the transistor region; the optoelectronic conversion region and the transistor region are isolated by a shallow trench isolation structure 301; offset sidewalls 303a are formed on both sides of the gate electrode 302, and lightly doped drain regions 306 are formed in the semiconductor substrate 300 on both sides of the offset sidewalls 303a; a protective layer 303b is formed on the surface of the semiconductor substrate 300 in the optoelectronic conversion region.

[0075] The semiconductor device of the embodiment of the present invention is manufactured by the above method, and thus also has similar advantages.

[0076] In the third aspect embodiment of the present invention, an electronic device is also provided, including the aforementioned semiconductor device, and the semiconductor device is prepared according to the aforementioned method.

[0077] The electronic device of this embodiment can be any electronic product or device such as a mobile phone, tablet computer, notebook computer, netbook, game console, television, VCD, DVD, navigator, digital photo frame, camera, video camera, voice recorder, MP3, MP4, PSP, etc., or can also be any intermediate product including a circuit. The electronic device of the embodiment of the present invention has better performance due to the use of the above-mentioned semiconductor device.

[0078] The present invention has been described through the above embodiments. However, it should be understood that the above embodiments are only for the purpose of exemplification and illustration, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the scope of protection required by the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalent scope.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The manufacturing method includes: providing a semiconductor substrate, the semiconductor substrate including a photoelectric conversion region and a transistor region, a gate electrode being formed on the semiconductor substrate of the transistor region; forming a dielectric layer on the surfaces of the semiconductor substrate and the gate electrode; forming a patterned hard mask layer on the surface of the dielectric layer located on the sidewalls of the photoelectric conversion region and the gate electrode; using a wet etching process to etch the dielectric layer based on the patterned hard mask layer, so as to remove the dielectric layer formed on the top of the gate electrode and on the surface of the semiconductor substrate in the transistor region, obtaining an offset sidewall formed by the dielectric layer formed on the sidewall of the gate electrode, and a protective layer formed by the dielectric layer formed in the photoelectric conversion region; after etching the dielectric layer based on the patterned hard mask layer, the method further includes: using a wet etching process to remove the hard mask layer.

2. The manufacturing method according to claim 1, characterized in that, The forming of the patterned hard mask layer on the surface of the dielectric layer located on the sidewalls of the photoelectric conversion region and the gate electrode includes: depositing a hard mask layer on the dielectric layer; forming a photoresist layer on the hard mask layer located in the photoelectric conversion region; using the photoresist layer as a mask to perform dry etching on the hard mask layer, so as to remove the hard mask layer formed on the top of the gate electrode and on the surface of the semiconductor substrate in the transistor region, obtaining the patterned hard mask layer; and, removing the photoresist layer.

3. The manufacturing method according to claim 2, characterized in that, The dry etching also removes part of the dielectric layer.

4. The manufacturing method according to claim 2, characterized in that, Before forming the photoresist layer after depositing the hard mask layer, the method further includes: performing a scrub cleaning process on the surface of the hard mask layer.

5. The manufacturing method according to claim 1, characterized in that, The dielectric layer includes a silicon oxide layer, and the hard mask layer includes a silicon nitride layer and / or a silicon oxynitride layer.

6. The manufacturing method according to claim 1, characterized in that, After forming the offset sidewall, the method further includes: performing a lightly doped ion implantation on the semiconductor substrate of the transistor region based on the offset sidewall, so as to form lightly doped drain regions on both sides of the gate electrode.

7. A semiconductor device, characterized in that, The semiconductor device is manufactured by using the method according to any one of claims 1-6.

8. An electronic device, characterized in that, The electronic device includes the semiconductor device according to claim 7.

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