Method for determining microfluidic cooling structures

Abstract

The invention relates to a method and a device for determining whether a cooling structure (6, 7) which can be manufactured is used for cooling a semiconductor device (9, 13). The invention relates to a computer-executable method for operating a semiconductor device (6, 6 '), where the method receives as input (10) at least one of i) physical parameters of the semiconductor device, where the physical parameters are physical characteristics related to the semiconductor device, and ii) a digital array (1) indicating a spatial power distribution of the semiconductor device, where the digital array (1) is a digital array (2) indicating a spatial power distribution of the semiconductor device. Wherein the method comprises the following steps: 1) using a topology optimization algorithm to determine (11) a cooling structure (6, 7) on the basis of the received input (10); and 2) based on the determined cooling structure (6, 6 ') can be physically manufactured (9) to provide a file type containing the determined cooling structure (6, 6') as output (12) in a data format, where the file type containing the determined cooling structure is a vector file type. It further provides a semiconductor device formed using the method of the invention, a corresponding electronic design automation tool.

Description

[0001] Field of the Invention

[0002] The present invention relates to a method, and more particularly to a computer-implemented method for determining a manufacturable cooling structure for cooling a semiconductor device, to a semiconductor device, and to an electronic design automation tool. Background Art Background of the Invention

[0004] Since the early 2000s, each successive node size in semiconductor manufacturing has resulted in an increase in the amount of heat energy generated per unit area. Capturing this heat energy is necessary as overheating of a semiconductor device typically negatively impacts device performance, efficiency and reliability: high temperatures lead to increased leakage currents which cause power losses, increased sheet resistance due to self-heating degradation; higher device temperatures and temperature swings directly correlate to decreased mean time before failure. In addition to silicon logic devices such as central processing units (CPUs), graphics processing units (GPUs), tensor processing units (TPUs), field programmable gate arrays (FPGAs) and other application specific integrated circuits (ASICs), the trend of rising heat flux and its negative impact on performance and reliability also holds true for power electronics, optoelectronics and RF electronics on silicon and other semiconductors such as GaAs, SiC, GaN, etc.

[0005] Due to the increased heat flux, capturing the thermal energy becomes more challenging. The traditional remote cooling paradigm requires the heat energy generated in the nano-sized hot spot to travel through a semiconductor die, then through packaging layers and thermal interfaces before it finally reaches a thermal sink. A large distance between the heat source and the thermal sink results in increased thermal resistance. Second, all of the layers and interfaces introduce a barrier to heat transfer, which introduces additional thermal resistance. As a result, a large temperature difference occurs between the hot spot of the semiconductor device and the thermal sink.

[0006] Microscale fluid cooling is a well-known technique for extracting highly concentrated thermal energy from semiconductor devices. Microscale features can benefit from a high surface to volume ratio, which can improve convective heat transfer. Second, microscale fluid cooling is usually operated in a laminar flow regime. The fully developed flow in the laminar flow regime is characterized by a fixed Nusselt number. As a result, a fixed Nusselt number will result in an increased heat transfer coefficient due to reduced feature size. The combination of these features allows microscale fluid cooling to extract heat fluxes on the order of 1 kW / cm2 while maintaining a temperature rise below 60K.

[0007] The high heat extraction capabilities of microscale fluid cooling enable high heat flux extraction from the footprint of the semiconductor device compared to traditional air and fluid cooling techniques. This eliminates the need to spread the thermal energy over a larger surface area; instead, a microfluidic heat sink can be the same size as the silicon wafer. Furthermore, the cooling structure can be integrated directly into the semiconductor device to eliminate poor heat transfer due to layers and interfaces between the heat source and heat sink. This so-called direct cooling approach has been extensively studied for decades.

[0008] However, despite the high heat extraction capability of microfluidic cooling, pressure drop is often a consideration. Smaller features enable higher heat transfer, but result in a high pressure drop. This effect is particularly pronounced for large area wafers. If the water resistance becomes too high, the maximum flow rate will be limited, resulting in a high coolant temperature rise. Therefore, optimizing the cooling design to minimize the hot spot temperature of the wafer under the constraint of a maximum pressure drop can be a challenging problem.

[0009] Current approaches typically rely on parametric optimization: using a regular heat sink, pin, channel structure or other repeating structure whose shape can be defined by parameters such as width, radius, spacing, diameter, etc. Optimizing these parameters to maximize heat transfer and minimize pressure drop is a well-studied problem and many solutions exist.

[0010] However, most of these parametric optimization methods assume a uniform heat flux, where a real semiconductor has a rather non-uniform heat flux. This type of problem cannot be easily adapted using the parametric optimization method because it does not allow for branching and merging of channels in areas that could be beneficial. However, despite the significant advantages of this type of structure, optimizing its design remains challenging. Designing this type of structure based on trial and error is a time-consuming process even for designers who are skilled in the art. Therefore, a platform is needed that can dynamically modify the layout of a cooling channel beyond the limitations of a parametric model.

[0011] It is an object of the present invention to at least alleviate some of the disadvantages associated with methods known from the prior art for determining a cooling structure for cooling a semiconductor device. Summary of the invention

[0012] SUMMARY OF THE INVENTION

[0013] According to a first aspect of the invention, there is provided a computer-implemented method for determining a manufacturable cooling structure for cooling a semiconductor device during operation, comprising the steps of claim 1. Further features and embodiments of the method of the invention are described in the dependent patent claims.

[0014] The present invention relates to a computer-executable method for determining a manufacturable cooling structure for cooling a semiconductor device during operation, wherein the method receives at least one of the following as input: i) a physical parameter of the semiconductor device, wherein the physical parameter is related to a physical characteristic of the semiconductor device, and ii) a digital array indicating a spatial power distribution of the semiconductor device, wherein the method includes the following steps: 1) using an optimization algorithm to determine a cooling structure based on the received input, and 2) based on the determined cooling structure being actually manufacturable, providing the determined cooling structure as output in a data format.

[0015] The input provided to the method includes a digital array (or matrix) indicating a spatial power distribution of the semiconductor device, wherein the digital array (or matrix) indicating a spatial power distribution can be embodied as a spatial power distribution map of the semiconductor device. The semiconductor device can be embodied as a silicon logic device, such as a CPU, GPU, TPU, FPGA, ASIC, XPU, ASIC, or as a separate device, such as a transistor or diode, as a power integrated circuit, or as an optoelectronic device. The spatial power distribution map can be provided as a regularly spaced grid, wherein each cell of the grid represents a heat flux or average power dissipation of each cell (of the semiconductor device). The spatial power distribution map can also include a shaping function to reconstruct a continuous spatial power distribution map. The granularity of the spatial power distribution map can vary, particularly depending on the semiconductor device it can represent. Typical cell sizes can extend from several microns and up to several millimeters. Cells can also be spaced in a non-uniform manner, and cells may overlap, such as a background heat flux, which has several higher heat flux areas located near areas with higher power dissipation. Such non-uniformly spaced spatial power distribution maps can also be reconstructed from a plan view of an integrated circuit, where the functional blocks in the plan view are mapped to a spatial power distribution map. The spatial power distribution map can also be provided by mapping temperature to a function of spatial power distribution: in this way, a simulated (or measured) temperature of a semiconductor device can be converted to a spatial power distribution map.

[0016] The method further receives physical parameters of the semiconductor device as input. The physical parameters may include material properties of a die on which the device logic is arranged and a coolant for the cooling liquid of the cooling structure to be determined, as well as other relevant dimensions, such as the thickness of the die. The die thickness may be between a few micrometers and up to several millimeters. However, in most cases, a value between 0.3 and 2 millimeters is considered typical. Another physical parameter that may be selected is the separation between the heat source and the convection cooling structure to be determined. The optimized cooling structure may be directly integrated into the semiconductor device, and the semiconductor device, for example, is embodied as a silicon wafer, and the cooling structure is etched into the side of the die opposite to the side on which the device logic is arranged. Alternatively, the cooling structure may be bonded or attached to the heat generating semiconductor device (the cooling structure may be bonded or attached to the heat generating semiconductor device via a bonding interface and / or via an attachment layer and / or via a thermal interface material). In this case, the optimization algorithm for determining the cooling structure can be configured to take into account the physical parameters of the bonding interface and / or the physical parameters of the attachment layer and / or the physical parameters of the thermal interface material between the two structures. In particular, the optimization algorithm can be configured to take into account any one or more of the following: the thermal conductivity of the bonding interface, and / or the thermal conductivity of the attachment layer, and / or the thermal conductivity of the thermal interface material, and / or the thickness of the bonding interface, and / or the thickness of the attachment layer, and / or the thickness of the thermal interface material, and / or a thermal boundary resistance of the bonding interface, and / or a thermal boundary resistance of the attachment layer, and / or a thermal boundary resistance of the thermal interface material.

[0017] The method according to the first aspect of the invention may also receive as input a plurality of digital arrays indicating a spatial power distribution / spatial power distribution diagram, and / or a plurality of different numerical assignments of the physical parameters. In this way, the optimization algorithm may be implemented multiple times, for example, on each of the plurality of digital arrays indicating a spatial power distribution. A user may be presented with different cooling structures determined in different operations of the optimization algorithm, and the user may determine the correct solution, or the optimal design of the cooling structure may be automatically selected from the different cooling structures, for example, by selecting a cooling structure having a minimum loss of a loss function used by the optimization algorithm.

[0018] The method according to the first aspect of the invention may determine a (microfluidic) cooling structure which may be integrated into a two-layer system comprising a solid state material layer with device logic, or which may be integrated with a multi-layer semiconductor device, or which may be integrated into a 2.5D semiconductor device comprising a chiplet and a main computing die on a common substrate, or which may be, for example, 3D integrated into a multi-layer semiconductor device. The provided physical parameters provide details of the various embodiments used during optimization.

[0019] After the optimization algorithm has converged, the following steps may be performed. First, the user may be presented with a graph of the optimization of the cooling structure, the corresponding temperature map on the surface of the semiconductor device assuming it is cooled by the determined cooling structure, a fluid layer, the total pressure drop and flow rate, and the pressure drop distribution through the fluid channels of the cooling structure.

[0020] Using the final geometry of the cooling structure, a sequence of simulations may be performed with varying flow rates. At each flow rate, metrics such as pressure drop, flow rate, and maximum temperature may be recorded. The data generated in the simulations may be displayed in graphs that assist the user in deciding how to compare the selected topology against other cooling methods. Typical graphs may include the pressure drop versus flow rate, temperature rise versus flow rate, thermal resistance versus pumping power, efficiency coefficient versus maximum heat flux, maximum heat flux versus pumping power, thermal performance factor (TPF), which is a rate of improvement of heat transfer ratio versus friction factor increment, or any other performance benchmark. In addition to the data points collected from the simulations, data points from a library of previously calculated or experimentally measured results may be added to the graphs to compare the performance against existing designs. Physical parameters provided as input to the method according to the first aspect of the invention may also include the location of temperature sensors, which may be physically placed at specified locations on the fabricated semiconductor device having the determined (optimized) cooling structure. During simulation, the temperature may be provided at the specified location and compared to the actual measured temperature using a temperature sensor on the fabricated semiconductor device; in this way, the accuracy of the simulation may be evaluated.

[0021] The determined cooling structure is provided in a file type suitable for manufacturing. To be comparable to optical lithography, for example, the cooling structure may be provided in a file type such as a GDSII, CIF, DXF or OASIS. Because these file types are vector-based and the topological optimization of the cooling structure may be performed on a grid, this conversion may be considered a pixel-to-vector conversion; in other words, the method of the present invention may include the step of converting the file type of the determined cooling structure from a vector-based file to a pixel-based file.

[0022] The method may further include a filtering step, wherein the filtering step includes applying a filter to the determined cooling structure to ensure that all features comply with one or more predetermined manufacturing constraints. For example, the method may include applying a filter to the determined cooling structure to determine the minimum distance between any two adjacent sidewalls (preferably between all adjacent sidewalls) in the determined cooling structure, and to determine whether the distance between the adjacent sidewalls is greater than a predetermined threshold distance (the predetermined threshold distance is preferably equal to a predetermined minimum feature size). If the distance between the adjacent sidewalls is less than the predetermined threshold distance, the sidewalls may be shifted to ensure that the constraints are complied with, that is, the adjacent sidewalls may be shifted so that the distance between them is at least equal to (or greater than) the predetermined threshold distance. In other examples, the method may include applying a filter to the determined cooling structure to determine whether any feature (e.g., solid feature) of the determined cooling structure has a size below a predetermined minimum threshold size; for example, the method may include applying a filter to the determined cooling structure to determine whether any feature (e.g., solid feature) of the determined cooling structure has a width below a predetermined minimum threshold width. The method may further include a step of removing any feature (e.g., solid feature) from the cooling structure that is determined to have a size below the predetermined minimum threshold size (e.g., removing any feature (e.g., solid feature) from the cooling structure that is determined to have a width below the predetermined minimum threshold width).

[0023] As described above, in one embodiment, the determined cooling structure is provided as a file type; in this case, the determined cooling structure may be a two-dimensional cooling design. The method may further include a step of extruding the two-dimensional cooling design into a three-dimensional structure. Advantageously, a three-dimensional structure will be comparable to additional fabrication such as 3D printing or electrodeposition. Preferably, in the extrusion steps, a height of the extrusion corresponds to a channel height used in the simulation step performed as part of the optimization algorithm to determine the cooling structure. Preferably, a solid substrate is added below the extruded cooling structure. The three-dimensional structure can be further adjusted to take into account manufacturing limitations such as, for example, DRIE etch delay, laser sidewall taper, or CNC milling radius. In addition, a housing with an inlet and an outlet can also be added to the three-dimensional structure. The three-dimensional structure can be provided in a file type such as STEP, STL, OBJ, GCODE, AMF, VRML, PLY, or 3MF.

[0024] In one embodiment of the method according to the invention, the physical parameters include i) dimensional parameters of the semiconductor device, which are embodied as at least width, length, and thickness of the semiconductor device, and / or ii) material properties of a die of the semiconductor device having device logic on the die, and / or iii) material properties of a cooling fluid of the cooling structure, wherein the cooling fluid may be a fluid embodied as water, or as a water-ethylene glycol mixture, or as a refrigerant, or as a dielectric coolant, or as a mineral oil, and / or iv) material properties of a physical connection between a cooling structure die having the cooling structure and a die of the semiconductor device having device logic on the die. The cooling fluid, instead of a liquid, may also be embodied as air or as another suitable gas.

[0025] In another embodiment of the method according to the present invention, the cooling structure determined using the optimization algorithm is assembled to be physically manufactured at least partially on the die of the semiconductor device having the device logic, and / or the cooling structure determined using the optimization algorithm is assembled to be physically manufactured at least partially on the cooling structure die, wherein the cooling structure die is assembled to be bonded and / or attached to the die of the semiconductor device having the device logic.

[0026] In another embodiment of the method according to the invention, the digital array indicating a spatial power distribution of the semiconductor device is embodied as a two-dimensional array of power dissipated per unit area of ​​the semiconductor device.

[0027] In another embodiment of the method according to the present invention, the method further receives at least one region of the semiconductor device as at least one design constraint as input, and the optimization algorithm is constrained to determine a cooling structure, wherein at least one region of the cooling structure relative to at least one region of the semiconductor device does not have a cooling structure component.

[0028] The design constraints may include defining fixed areas of the die of the semiconductor device that should remain solid, such as the edge of the die, or certain areas of out-of-plane interconnection, such as apertures in a multilayer semiconductor device, or connections for RF antenna components may be present on the die. Other design constraints may be, for example, minimum feature size, which may depend on the size of a filter used in the final system to achieve clogging prevention. In particular, a minimum feature size between 25 microns and 250 microns may help prevent clogging; therefore, in a preferred embodiment, the design constraints include a minimum feature size between 25 microns and 250 microns. Preferably, the design constraints include a minimum feature size between 50 microns and 100 microns.

[0029] In one embodiment, the design constraints may include a requirement for a solid border near the edge of the wafer. For example, in the case where the cooling structure determined using the optimization algorithm is configured to be integrated as part of the semiconductor device, then preferably the design constraints include a requirement for a solid border near the edge of the wafer having a width between 20 microns and 2 millimeters; the solid border may be suitable for containing coolant inside the wafer. Preferably, the design constraints include a requirement for a solid border near the edge of the wafer having a width between 100 microns and 500 microns. Preferably, the total width of the border on both sides and the interior region should be substantially equal to, or exactly equal to, the width of the semiconductor device.

[0030] In another embodiment of the method according to the present invention, a loss function and / or optimization constraint used by the optimization algorithm is based on at least one of the following: i) pressure, ii) flow rate, iii) maximum temperature, iv) average temperature, v) intermediate temperature, vi) temperature gradient, and wherein the optimization algorithm performs extremization, in particular minimization or maximization, of the loss function, and the loss function is in particular limited by the at least one optimization constraint.

[0031] For example, the optimization constraints used by the optimization algorithm may include one or more of the following: a maximum pressure drop of 0.25 and 2 bar on the cooling structure, and / or a maximum flow rate of 0.5 and 5 liters per kilowatt of heat extracted from the wafer per minute. More preferably, the optimization constraints used by the optimization algorithm may include one or more of the following: a maximum pressure drop of 0.5 bar and a maximum flow rate of 1.5 liters per kilowatt of heat extracted from the wafer per minute.

[0032] An objective function / loss function / cost function may be defined for the optimization achieved by the optimization algorithm. This may reduce the maximum temperature, the average temperature, the temperature gradient, the pressure drop, the flow rate, or a combination of these parameters. These parameters may additionally also act as constraints, such as fixing the bulk flow rate and limiting the pressure drop while minimizing the temperature rise.

[0033] In another embodiment of the method according to the present invention, the optimization algorithm uses a two and a half dimensional model during optimization, wherein the optimization algorithm is configured to assume a parabolic flow profile in an out-of-plane dimension of the cooling structure during determination of the cooling structure. The optimization algorithm may also assume a temperature profile in the fluid and a linear temperature profile in the semiconductor material in the out-of-plane dimension of the cooling structure during optimization. Multiple layers of the two-dimensional models may be coupled by including out-of-plane thermal and mass transfer relationships to simulate more complex structures with varying material properties at reduced computational cost.

[0034] In a further embodiment of the method according to the invention, the optimization algorithm uses at least one manufacturing constraint, in particular a lithography constraint and an etching constraint of a manufacturing process related to the determined cooling structure as a further optimization constraint.

[0035] Manufacturing constraints may be set depending on the method used to realize the final cooling structure. In the lithography case, the manufacturing constraints may include a minimum feature size depending on the lithography system used. In a preferred manner of manufacturing / realizing the final cooling structure, the final cooling structure is patterned using optical lithography on a photosensitive mask. The photosensitive mask is provided and the pattern of the cooling structure is transferred to the photosensitive mask (this typically includes exposing portions of the photosensitive mask to light so as to create the pattern of the cooling structure on the photosensitive mask; the portions of the mask exposed to light will solidify or melt, thereby creating the pattern on the photosensitive mask). A particular limitation of optical lithography is a minimum feature size of 2 microns. The cooling structure is then etched into an underlying substrate, such as a silicon wafer, or grown with copper, nickel or palladium using a deposition technique. In particular, etching techniques such as deep reactive ion etching (DRIE) or wet etching are more suitable. When deep reactive ion etching (DRIE) is used to create the channel, a vertical sidewall profile can be assumed. For DRIE, a preferred maximum channel aspect ratio is between 5 and 40; more preferably, the maximum channel aspect ratio is between 7 and 15. When a channel depth limit is defined / selected for the cooling structure, the optimization algorithm will avoid creating features that exceed this aspect ratio. In addition, during etching or deposition methods, narrow features can be achieved at a slower rate than wider features. The etch lag during DRIE can be integrated into the system so that a smaller depth is implemented for narrower features compared to wider openings. For laser processing, a beam radius and sidewall curvature can be considered. The angle of the sidewall profile after manufacturing can be included as a manufacturing limitation to limit the minimum feature size and improve the simulation accuracy. A preferred taper angle of the sidewall profile is between 1 degree and 10 degrees. For CNC processing, a minimum end grinding radius can be defined. Manufacturing limitations can also be received as input by the method according to the first aspect of the present invention. In this case, the final cooling structure is realized / manufactured by etching multiple thin sheets that are subsequently bonded together to create a final cooling structure comprising a multi-layer stack, and a manufacturing constraint may be imposed that there are no independent features, but rather all features of each layer should be connected to be included in the design.

[0036] In another embodiment of the method according to the present invention, the optimization algorithm determines the number of inlets and outlets of the cooling structure and the positions of the determined inlets and outlets by considering the packaging methodology constraints. A constraint can be used to define a minimum distance between the inlets and outlets to consider the required space to establish a seal between the manifold and the microstructure. A preferred minimum distance constraint is between 1 and 10 mm. A more preferred minimum distance constraint is between 2 and 5 mm. Another constraint can be used for the minimum width of the inlets and outlets. A preferred minimum width constraint is between 0.1 and 2 mm. A more preferred minimum inlet and outlet width constraint is between 0.5 and 1 mm. The same pressure can be assumed on all inlets, and the same pressure can be assumed on all outlets.

[0037] The channel layout design of the cooling structure to be determined may be limited to two dimensions due to manufacturing limitations from the lithography and etching processes, ignoring the significant performance gains achieved when the optimization algorithm is allowed to exploit the three dimensions. Similarly, the design of a multi-manifold that requires connecting the external piping system to the inlets and outlets in the channel layout of the cooling structure may be a challenge in itself. In general, it is important to place the inlets and outlets without being troubled by a significant pressure drop in the multi-manifold. The design of both the multi-manifold and the channel layout of the cooling structure can be integrated into a single optimization framework that accepts the manufacturing limitations of each device. The optimization algorithm can determine a two-dimensional geometry for the channel layout of the cooling structure, and / or the optimization algorithm can determine another single or multiple two-dimensional layers that together form the multi-manifold; and / or the optimization algorithm can determine a full three-dimensional geometry for the multi-manifold. In this way, the channel layout of the cooling structure can exploit the three dimensions through the multi-manifold. The optimization of the number of inlets and outlets of the cooling structure can also be realized independently of a possible optimization of the manifold into which the inlets and outlets converge individually. The structure of the manifold can also be predetermined or determined by the method according to the first aspect of the invention.

[0038] In another embodiment of the method according to the invention, the optimization algorithm for determining the cooling structure based on the received input comprises the following steps: 1) determining a grid, in particular embodied as a regularly spaced grid or as a grid based on a digital array indicating a spatial power distribution and / or based on the at least one design constraint and / or based on the manufacturing constraint, 2) mapping the digital array indicating a spatial power distribution to the grid, and optionally mapping the at least one design constraint to the grid, 3) starting with an initial geometry of the cooling structure on the grid, adapting a current geometry of the cooling structure in an iterative method until a final geometry of the cooling structure is determined, wherein At each optimization iteration in , the following sub-steps may be implemented: i) simulating a physical behavior of the cooling structure having the current geometry using at least modeling equations, in particular the Nevi-Stoke equations and the heat transfer equations, and the physical parameters, ii) determining at least one current value of the loss function based on the simulated physical behavior, iii) determining at least one gradient of the optionally constrained loss function with respect to the change pattern of the geometry of the cooling structure away from the current geometry, in particular using an adjoint method and iv) providing the determined at least one gradient to a set, in particular programming equations, which updates the current geometry in such a way that the optionally constrained loss function is further maximized. Due to the optimization algorithm, in the region where the heat flux exceeds 200 W / cm2, cooling features with minimum acceptable feature sizes are established with the highest surface area for heat transfer, wherein in the region where the heat flux is below 50 W / cm2, a lower surface area with larger feature sizes for heat transfer is established to minimize pressure drop.

[0039] Optimization can start by dividing a design space for determining the cooling structure into a fine grid. This can be a 2D grid to reduce the computational cost, where it is assumed that the flow profile is approximately completed in the three dimensions, or in a fully 3D manner. The grid can be selected to be fine enough to resolve the smallest features expected under the design and manufacturing constraints, or a homogenization method can be used to approximate smaller features with a coarser grid. In addition, according to the Reynolds number that can be estimated as a priori based on the macro design parameters (pressure drop or flow rate) of the optimization, the grid can be fine enough to resolve most of the vortices generated in the simulated flow. The smallest vortices in the flow can be modeled using a large nest flow simulation incorporated into the Smagorinsky turbulence model or any other turbulence model. The grid can be a uniformly spaced grid, or the grid can be adapted to the spatial power distribution map / the digital array indicating a spatial power distribution. It can be expected that when finer features in the region are identified during the optimization, a possible way to adapt the grid to the spatial power distribution map is by refining the grid in the region with higher heat flux. In addition, the optimization algorithm is formulated using concepts from functional analysis to identify and adjust for the non-uniform grid allocation. That is, the geometry defined by the density field is not simply interpreted by the optimization algorithm as an array of numbers, but rather a function space in the optimization algorithm and the members of the dot product are converted to inner products of the function space, which account for the non-uniform nature of the grid based on discretization. This ensures that the optimization algorithm produces an optimized cooling structure design and is not biased by the presence of grid elements of different sizes. In addition, gradient regions can be introduced between fine and coarse grid regions when transitioning between varying heat fluxes. The spatial power allocation map, boundary conditions, and design constraints can be mapped to the grid using projection methods or interpolation techniques based on a nearest neighbor algorithm, range search, or nested grids.

[0040] An optimized geometry of the cooling structure based on the (user) input of the method according to the first aspect of the invention can then be determined. This can be done in an iterative method using the geometry of the cooling structure as the optimization variable in an optimization method. Different geometry optimization methods can be used for this purpose, all under the umbrella of so-called topological optimization methods, wherein the geometry can be arbitrarily varied in the number of holes therein. Topological optimization methods can be classified according to the parameterization of the geometry: density methods define the geometry with a continuous field varying between one representing the fluid phase and zero representing the solid phase, quasi-combinatorial methods use contours of a scalar function as boundaries of the geometry, and phase field methods use a smooth step function as the boundary separating the fluid and solid phases. Regardless of the approach, the geometry defining the fluid and solid phases may be embodied in equations that model the relevant physical phenomena: the Navier-Stokes equations and the heat transfer equations, which model the thermal convection occurring in the channels, and the thermal conduction in the substrate layer or layers (the heat transfer equations model the thermal conduction and convection, and the Navier-Stokes equations model the fluid behavior). At each optimization iteration, the physical equations may be solved to evaluate several performance metrics, such as pressure drop, maximum temperature, or heat dissipation, for a current geometry estimate. Likewise at each optimization iteration, the gradients of the performance metrics with respect to changes in the geometry may be calculated using the adjoint method and fed to a set of nonlinear programmed equations that may, in particular, update the geometry of the cooling structure to one with better performance. If desired, high frequency modes of the geometry parameterization may be filtered out to improve the stability of the optimization. This step may be achieved by a convolution procedure as a solution of a partial differential equation, or by using a more rigorous parameterization.

[0041] The information of the spatial power distribution map can be used to speed up the optimization. Indeed, higher heat flux areas will require a higher solid-fluid surface area and vice versa for lower heat flux areas. As such, the initial geometry used by the optimization algorithm can reflect this as a priori knowledge; the optimization can therefore start from a better starting point.

[0042] Solving the fluid equations (Nevi-Stokes equations) may require special care due to the potentially high inertial forces of the fluid / cooling liquid / coolant in the cooling structure. The nonlinear nature of the equations requires a nonlinear solver that starts with an initial estimate of the solution and iterates until convergence to an equilibrium solution that satisfies the equations. Commonly used nonlinear solvers such as the Newton method are insufficient and do not converge when starting from an initial estimate far from the equilibrium. Whether or not the initial estimate is required, a strategy is required to ensure convergence. Several approaches can achieve this goal: homotopy methods, parameter continuity methods, damped Newton methods, complete approximation schemes, etc.

[0043] The above-mentioned solvers (physical equations, such as Navier-Stokes equations and heat transfer equations, adjoint methods for obtaining gradients, filtering) can be replaced by reduced order models (hereinafter ROMs). ROMs can be generated using the following methods: via data from previous / real-time simulations, via physical / empirical approximations, or using a combination of these. More specifically, the ROMs can be trained given a set of simulation (topology optimization) data by applying an appropriate orthogonal decomposition (hereinafter POD) or by using a neural network or deep reinforcement learning or any other artificial intelligence or machine learning motivation method. A ROM can be used to accelerate the analysis of a semiconductor device with a determined (optimized) cooling structure. In an electronic design automation tool, for example, a ROM can be used to quickly simulate the behavioral perspective of a semiconductor device with a determined cooling structure without solving computationally expensive physical equations, such as Navier-Stokes equations and / or heat transfer equations.

[0044] More specifically, in the case of the POD-ROM, the ROM can be trained in such a way that it can replicate the optimization procedure. To do so, for each optimization iteration, the solution of the degrees of freedom (velocity, pressure, and temperature and / or density field) from the full order model (FOM) can be stored (in a non-dimensional form) in a vector. The vector can then be stored as a row in a matrix whose rows represent a different optimization iteration and whose columns represent the degrees of freedom of the problem. The solution can then be decomposed into its singular values ​​and vectors (POD models) by performing an incremental (real-time) singular value decomposition (SVD). Each of the singular values ​​can represent a different energy level in the system, so that the highest level can correspond to a POD model (hereinafter POM) containing bulk information about the solution, while the lowest level can correspond to a POM containing detailed information about the solution. The POM combination constitutes an optimization vector basis that may project a solution or the problem (system of equations) itself. In fact, it is possible to consider the unknown degrees of freedom as a linear combination of a subset of the singular vector basis (a truncated dimension determined based on various criteria: energy, maximum element, a posterior error, etc.). This in turn allows to perform a Geleken projection of the system of equations on the selected subset of POMs, which will yield a truncated linear system of equations constituting the ROM. Solving the system of coefficients for the above projection allows to compute the solution of the system by reprojecting these coefficients onto the POM basis. One of the advantages of this type of ROM is that it can be used either in real-time or as a post-processing tool. The former, i.e., real-time use, allows to speed up a large number of optimization iterations based on a few FOM iterations of the same problem, while the latter, i.e., post-processing use, implies that a ROM trained on a problem defined by a set of parameters can also be used on another problem of a neighboring parameter combination, given that the physical state remains the same (e.g., similar Reynolds number, layered / perturbed system, etc.). This type of ROM can also be used as a digital twin as part of an electronic design automation loop to allow an integration of the cooling solution while avoiding a significant increase in simulation time.

[0045] In another embodiment of the method according to the invention, the initial geometry of the cooling structure is determined based on a digital array indicating a spatial power distribution.

[0046] According to a second aspect of the present invention, there is provided a semiconductor device comprising a cooling structure determined using a method according to the first aspect of the present invention, wherein the cooling structure is manufactured using optical lithography. More particularly, optical lithography is used to transfer the cooling structure to a photomask, which is then used to etch into the underlying substrate or to locally deposit material onto the underlying substrate.

[0047] In one embodiment of the semiconductor device according to the present invention, the device logic of the semiconductor device is disposed on one side of a die of the semiconductor device, and wherein the cooling structure is disposed on an opposite side of the die with respect to the side on which the device logic is disposed.

[0048] In another embodiment of the semiconductor device according to the present invention, the semiconductor device includes a first die on which the device logic of the semiconductor device is arranged, and the semiconductor device includes a second die on which the cooling structure is arranged, wherein a physical connection between the first die and the second die is embodied as a bonding or attachment between the first die and the second die.

[0049] According to a third aspect of the present invention, an electronic design automation tool is provided, wherein the electronic design automation tool includes program code, which, when executed on a computing device, causes the computing device to implement a method according to the first aspect of the present invention, and wherein the electronic design automation tool also includes program code, which, when executed on a computing device, causes the computing device to implement a plane configuration and / or post-layout analysis of a plane configuration diagram of the device logic of a semiconductor device, and wherein the electronic design automation tool is configured to determine a digital array indicating a spatial power distribution of the semiconductor device based at least on the plane configuration diagram and using post-layout analysis, and wherein the program code of the electronic design automation tool for determining a cooling structure is configured to use the thus determined digital array indicating a spatial power distribution as input.

[0050] Program code for executing a method according to the first aspect of the present invention may alternatively be provided in a separate cooling structure design automation tool that may be independent of the electronic design automation tool. Symmetries and boundary conditions of a semiconductor device for which a cooling structure is to be determined may be defined in the electronic design automation tool (or alternatively in the cooling structure design automation tool). Symmetries may be defined to reduce the design space for finding an optimal design for the cooling structure. For example, if the spatial power allocation diagram has certain symmetries, the optimization domain may be reduced to reduce the computational resources required to run the optimization algorithm.

[0051] Two important steps are generally identifiable at the chip design level: floorplan, or routing, which determines the physical locations of transistors, or blocks of transistors, on the integrated circuit, and post-layout analysis, which determines the power dissipation and resulting temperature map of the integrated circuit (IC) based on the floorplan. Due to the temperature-dependent nature of semiconductor devices, the power dissipation of the IC depends on the temperature, and the temperature depends on the power dissipation. Here, a temperature map can be established iteratively or under a set of assumptions. In an electronic design automation tool according to a third aspect of the invention, a method according to the first aspect of the invention can be configured to interact with floorplan and post-layout analysis in the following way: Based on the floorplan determined by floorplan and certain assumptions on temperature, the spatial power allocation map can be calculated in the post-layout analysis. The spatial power allocation map can be provided to a routine of the electronic design automation tool, wherein the routine executes a method according to the first aspect of the invention and it generates a cooling structure. Using the resulting temperature obtained after cooling the IC with the determined cooling structure, an updated spatial power allocation map can be calculated. If the resulting value is within certain limits and passes these requirements, it is accepted.

[0052] Alternatively, the optimization algorithm of the method according to the first aspect of the present invention can be used in an iterative manner in conjunction with the plane configuration and post-layout analysis in the electronic design automation tool. For each plane configuration or sequence of plane configurations, first, a spatial power allocation diagram can be obtained, for which a cooling structure can be determined, and then it can be determined whether the specified IC and cooling structure together meet the required specifications. The electronic design optimization and cooling design optimization can be repeated in an iterative process of the electronic design automation tool to find a combined optimization for the electronic and cooling designs. The two optimizations can follow a separate set of optimization parameters, or an overall loss function can be defined for the two optimization steps.

[0053] When the semiconductor device can operate under varying conditions, multiple separate spatial power allocation diagrams can represent different operating conditions. For the design of a cooling structure, a set of spatial power allocation diagrams can therefore be provided to the method according to the first aspect of the present invention, or to the electronic design automation tool according to the third aspect of the present invention as input. The electronic design automation tool can determine a representative spatial power allocation diagram that will meet the design purpose under all or most operating conditions. A possible way to obtain such a representative spatial power allocation diagram is to iterate all input spatial power allocation diagrams, and for each cell of a grid set on all input spatial power allocation diagrams, the maximum value of any one of the input spatial power allocation diagrams on the cell is regarded as a representative value. For optimization purposes, the resulting spatial power allocation diagram can be regarded as a worst-case spatial power allocation diagram.

[0054] Instead of using a fixed spatial power allocation diagram, a transient spatial power allocation diagram may be provided as input to a method according to the first aspect of the invention, or to an electronic design automation tool according to the third aspect of the invention. A transient spatial power allocation diagram may be viewed as a time series of multiple spatial power allocation diagrams, and may be viewed in a manner similar to that previously described, i.e., finding a corresponding maximum worst case spatial power allocation diagram corresponding to the maximum value of each cell found over the complete time range of the data set. After optimization, a temperature time series may be reconstructed based on the transient spatial power allocation diagram.

[0055] In one embodiment, the cooling structure includes a buffer zone. The buffer zone is an artificial extension of the simulation domain without any solid structures, i.e., the coolant can flow without any interference. This region is needed because we need to allow the coolant enough space so that the flow can fully develop. Preferably, the buffer zone is located at an inlet of the cooling structure, for example, near the coolant inlet boundary - the coolant inlet boundary is the portion of the simulation domain boundary where the coolant enters the simulation domain to prevent the inlet temperature from being directly imposed at the channel level. Having a buffer zone at the inlet of the cooling structure ensures that the heat sinks near the inlet are not inadvertently affected by the inlet temperature, thereby avoiding unintended cooling effects. In addition, the buffer zone can enhance the stability of the Navier-Stokes solver. In particular, additional heat sinks at the inlet of the cooling structure can block the flow of cooling fluid due to the optimization of the optimization algorithm, especially if the additional heat sinks are located adjacent to the boundary of the simulation domain (the boundary of the simulation domain refers to the limit or edge of the computational domain or space generated by the simulation) leading to solver instability and failure of the simulation - the buffer zone can help resolve.

[0056] The 2.5D representation of the cooling structure (in the simulation domain) is constrained to the wafer boundary (the wafer boundary is the physical edge or perimeter of the silicon wafer or die) and lacks a natural outlet to allow the cooling fluid flow to become fully developed or undisturbed (a fully developed or undisturbed flow is one in which the velocity component of the flow does not change with the direction of the flow), resulting in abrupt termination of the cooling fluid flow and occasional backflow due to stability challenges of the undeveloped / disturbed flow pattern - which results in flow interruption of the cooling fluid at the outlet of the cooling structure. In one embodiment, a flow stability mechanism is incorporated into the Navier-Stokes equations to minimize / reduce flow interruption at the outlet of the cooling structure. The flow stability mechanism may include a boundary term on the outlet of the cooling structure, added to the variational formulation of the Navier-Stokes equations:

[0057]

[0058] Where "h" is the mesh element size, "Re" is the Reynolds number, Γ N is the exit boundary, “u” is the velocity domain, “v” is the test function of the velocity domain, and “t” is the boundary Γ N The tangent vector of . BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Exemplary embodiments of the present invention will be disclosed in the description and illustrated in the accompanying drawings, in which:

[0060] Figure 1 An embodiment of a method for determining a manufacturable cooling structure for cooling a semiconductor device during operation is schematically illustrated;

[0061] Figure 2 A schematic diagram of a microfluidic cooling structure having a split design multi-manifold is shown;

[0062] Figure 3 A schematic diagram of a microfluidic cooling structure designed with a multi-manifold;

[0063] Figure 4 A method according to the present invention is schematically depicted;

[0064] Figure 5 A semiconductor device having a cooling structure disposed on a separate die is schematically illustrated;

[0065] Figure 6 Schematically illustrating a spatial power allocation diagram and a corresponding overlay diagram of a determined cooling structure;

[0066] Figure 7 schematically illustrates a cross-sectional view of a semiconductor device having an integrated microfluidic cooling structure determined using a method according to a first aspect of the present invention;

[0067] Figure 8 Schematically illustrating a multilayer semiconductor device having a microfluidic cooling structure determined using a method according to a first aspect of the present invention;

[0068] Fig. 9 Schematically depicting a multilayer semiconductor device on a substrate having a microfluidic cooling structure determined using a method according to a first aspect of the present invention;

[0069] Fig.10 Schematically depicting a multilayer semiconductor device on a substrate with an additional wafer on the substrate having a microfluidic cooling structure determined using a method according to a first aspect of the invention;

[0070] Fig.11Schematically illustrating a multilayer semiconductor device having a plurality of heat generating elements, which has a microfluidic cooling structure determined using a method according to a first aspect of the present invention;

[0071] Fig.12 schematically illustrates a multilayer semiconductor device having a plurality of microfluidic layers, which has a microfluidic cooling structure determined using a method according to a first aspect of the present invention; and

[0072] Fig.13 Schematically depicts a cross-sectional view of a wafer separated from a microfluidic cooling structure by an intermediate thermal interface, the wafer having the microfluidic cooling structure identified using a method according to a first aspect of the present invention. DETAILED DESCRIPTION

[0073] Detailed description of preferred embodiments

[0074] Figure 1 An embodiment of a computer-implemented method for determining a manufacturable cooling structure for cooling a semiconductor device during operation is schematically illustrated. The method receives as input a digital array 1 indicating a spatial power distribution of the semiconductor device. The digital array 1 is converted into a spatial power distribution Figure 1 '. Restriction 2 can be added to the spatial power allocation Figure 1 ', where the restriction is given by Figure 1 The four black dots and black stripes near the circumference of the middle figure are schematically drawn. The inlet / outlet 3 of a multi-manifold is composed of Figure 1 Via the inlet / outlet ports 3 , the cooling fluid enters a - subsequently defined - cooling structure. Figure 1 In the embodiment of FIG. 1 , it is assumed that the locations for the inlet / outlet 3 are predetermined. Next, the potential symmetry 4 in the spatial power distribution diagram is determined. Such symmetry 4 is often present in practice as an integrated circuit, for example, and often includes a repeating structure of basic circuit elements. Identifying symmetry can help simplify the calculations used to determine a cooling structure. Figure 1 In the embodiment of FIG. 5 , for example, two axes of symmetry are shown, and the determination of the cooling structure can be carried out only for one of the four quadrants shown, i.e. for a reduced area 5. The (simulated) cooling behavior of the determined cooling structure 6 ′ on the portion of the semiconductor device corresponding to the reduced area 5 is represented as a temperature Figure 7 8. If the cooling behavior of the determined cooling structure 6' is determined to be sufficient, for example, the entire cooling structure 6 can be determined by utilizing the previously determined symmetry and boundary conditions. The cooling structure 6 is provided in a file format suitable for manufacturing. The manufactured cooling structure 9 can be used to cool the semiconductor device to which it is adapted.

[0075] Figure 2 A microfluidic cooling structure with a separately designed manifold is schematically shown. The geometry of the microfluidic channels of the cooling structure 6 is the result of a 2D / 2.5D topological optimization, and the inlet manifold 3' and outlet manifold 3" of the cooling structure are determined by a 3D topological optimization with fixed delivery / extraction openings. In this case, the problems of cooling structure design and manifold design are independent in the sense that their topological optimization can be run in parallel, since their common interface (the above-mentioned openings) has an a priori fixed geometry and position.

[0076] Figure 3 A microfluidic cooling structure designed together with a manifold is schematically shown. Both the channels of the cooling structure 6 and the inlet manifold 3' and outlet manifold 3" of the cooling system are the result of a common 3D topological optimization with free delivery / extraction openings for the manifolds. Two different geometric parameterizations can be used, one for the cooling structure and one for the manifolds, to allow the manufacture of each individual component. The advantage of the decomposition of the topological optimization in 2D channels and 3D inlet-outlet manifolds is that the optimization of the 2D channels uses the entire physical equations (Navier-Stokes equations and heat transfer equations), while the optimization of the 3D inlet-outlet manifold only uses the Navier-Stokes equations; the decomposed topological optimizations are therefore coupled to enable the optimization algorithm to design a more optimal geometry compared to a separate design of one of the manifold and the cooling structure.

[0077] Figure 4 A method according to the invention is schematically illustrated. The method receives as input 10 at least one of the following: i) physical parameters of the semiconductor device, wherein the physical parameters are related to physical characteristics of the semiconductor device, and ii) a digital array indicating a spatial power distribution of the semiconductor device, determines 11 a cooling structure based on the received input 10, and provides the determined cooling structure as output 12 in a file format / data format suitable for manufacturing.

[0078] Figure 5 A semiconductor device having a cooling structure disposed on a separate die is schematically depicted. The device logic 13 of the semiconductor device is disposed on a first die, and the fabricated cooling structure 9 is disposed on a second die. The second die may be bonded or attached to the first die to enable cooling of the device logic 13, for example, to be embodied as an integrated circuit. Alternatively, both the device logic and the cooling structure may share a single die disposed on opposite sides of the single die.

[0079] Figure 6A spatial power allocation map received as input and a corresponding decision (optimization) of the cooling structure provided as output of the method according to the first aspect of the invention are schematically illustrated. Figure 6 The numbers in the legend relate to heat flux in Watts per square millimeter. Areas with higher heat flux have narrower channels to provide more surface area and thus heat transfer, while cooler areas with lower heat flux have wider channels to allow the cooling fluid to flow through with a smaller pressure difference. The left panel schematically illustrates a low Reynolds number (viscosity) case, while the right panel illustrates a high Reynolds (inertia) case. For the latter, the produced heat sink is shorter in the downstream direction and the flow follows a more curved flow pattern, while for the former, the produced heat sink is longer in the downstream direction and the flow follows a more straight flow pattern. The obvious visual difference between the two optimized channel geometries clearly shows the need for a customized design suitable for each different application.

[0080] Figure 7 A cross-sectional view of a semiconductor device with an integrated microfluidic cooling structure is schematically shown. The semiconductor device can be modeled as a 2-layer system with an integrated microfluidic cooling structure layer 25 and a solid material layer 14. The two layers together represent the total thickness 14' of the semiconductor device. Power is dissipated on opposite sides of the microfluidic cooling structure layer in the active area of ​​the semiconductor device including the device logic 13. The microfluidic cooling structure layer includes gaps 9' through which fluid can pass through the solid area 9". The determination of the optimal allocation of gaps and solid areas is performed by a method according to the first aspect of the invention.

[0081] Figure 8 A multi-layer semiconductor device is schematically shown. Figure 7 In addition to the active area 13 of the semiconductor device modeled in the embodiment of the present invention, a redistribution layer (RDL) 15 may also be modeled. The RDL layer includes a plurality of conductive and / or dielectric elements 16, 16', 16", 16'". Each layer may have uniform material properties 16 or non-uniform properties 16', 16", 16'". A layer may have apertures extending through the layer 17, 17', and lateral metal traces 18. Each component of the multi-layer system and the complete structure of the RDL layer 15 can be modeled with their individual material properties to form an extended conduction model to more accurately capture the heat conduction close to the heat source (e.g., the device logic 13) and thereby improve the cooling structure determined by a method according to the first aspect of the present invention.

[0082] Fig. 9 A multilayer semiconductor device on a substrate is schematically shown. The multilayer semiconductor device shown corresponds to Figure 8The embodiment shown. During determination of the cooling structure by a method according to the first aspect of the invention, the solder bumps 19 and the underlying substrate 20 may also be considered (as part of an extended conduction model). The substrate 20 may be a printed circuit board (PCB) or an interposer. Additional inhomogeneities in the substrate 20, such as layers with varying material properties 21, 21', may be included during determination of the cooling structure.

[0083] Fig.10 Schematically depicts a multilayer semiconductor device on a substrate with additional chiplets on the substrate. Fig. 9 In addition to the multilayer structure shown, additional chiplets 22, 22' may be considered during the determination of the cooling structure according to a method according to the first aspect of the invention. These chiplets may, for example, be memory chips placed laterally next to the central computing die. These chiplets may be as follows Figures 7 to 9 The same level of granularity and layers as described above can be modeled. Furthermore, the power dissipation in the chiplets can also be included in the optimization method according to the method of the first aspect of the invention. Furthermore, a microfluidic cooling can also be integrated inside the chiplets, or a fixed heat transfer coefficient can be assumed on the top surface 23, 23' of the chiplets 22, 22' to simulate a conventional heat sink or cold plate placed on top of the chiplets.

[0084] Fig.11 A schematic diagram of a multilayer semiconductor device having a plurality of heat generating elements is shown. Figures 7 to 10 An embodiment of Fig.11 In the embodiment, the plurality of layers 15', 15", 15"', 15"" of the heat generating elements 24, 24', 24", 24"' are stacked. A conduction model used in the method according to the first aspect of the present invention can be extended to include the plurality of layers 15', 15", 15"', 15"". During the optimization performed by the method according to the first aspect of the present invention, the temperatures on all the plurality of heat generating layers can be considered in a loss function, and the design of the microfluidic cooling structure can be optimized to minimize Fig.11 The temperature of each heat generating layer in the multilayer stack is shown.

[0085] Fig.12 A schematic diagram of a multilayer semiconductor device having multiple microfluidic layers. Fig.11In the illustrated embodiment, multiple microfluidic cooling structure layers 25, 25', 25", 25'" are stacked vertically between heat generating elements. The method according to the first aspect of the present invention can simultaneously optimize the appearance of the microfluidic cooling structure layers 25, 25', 25", 25'" based on the power distribution (spatial power distribution diagram) and the corresponding temperatures of the multiple heat generating layers. Limitation 2 may include positioning of solid materials in the microfluidic layer, such as an aperture 17" through a solid layer 17"' to provide electrical connections between the multiple layers.

[0086] Fig.13 A schematic cross-sectional view of a wafer separated from a microfluidic cooling structure by an intermediate thermal interface is shown. The wafer 26 of the semiconductor device can be a single-layer wafer or a multi-layer wafer. The wafer 26 is separated from the microfluidic cooling structure 9 by an intermediate thermal interface 27. A method according to a first aspect of the present invention can take both the wafer 26 and the intermediate thermal interface 27 into consideration in order to determine an optimized shape of the cooling channel of the cooling structure 9.

[0087] Without departing from the scope of the invention as defined by the appended claims, it will be apparent to those skilled in the art that various modifications and variations of the embodiments of the invention described herein may be made. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments.

Claims

1. A computer-implemented method for determining a manufacturable cooling structure (6, 6') for cooling a semiconductor device (9, 13), wherein the method receives as input (10) at least the following items: i) physical parameters of the semiconductor device, wherein the physical parameters are related to physical characteristics of the semiconductor device, and wherein the physical parameters include i) dimensional parameters of the semiconductor device, wherein the dimensional parameters are embodied as at least width, length, and thickness of the semiconductor device, and / or ii) material characteristics of a die of the semiconductor device having device logic (13) on the die, and / or iii) material characteristics of a cooling fluid of the cooling structure (6, 6'), and / or iv) material characteristics of a physical connection between a cooling structure die (9) having the cooling structure and a die of the semiconductor device having device logic (13) on the die; and ii) a digital array (1) indicating a spatial power distribution of the semiconductor device, wherein the digital array (1) indicating a spatial power distribution of the semiconductor device is embodied as a two-dimensional array (1') of power dissipated per unit area of ​​the semiconductor device; The method comprises the following steps: 1) using a topology optimization algorithm to determine (11) a cooling structure (6, 6') based on the received input (10), wherein the topology optimization algorithm performs a maximum value of a loss function, wherein The loss function is based on at least one of: i) pressure, ii) flow rate, iii) maximum temperature, iv) average temperature, v) median temperature, vi) temperature gradient; and 2) providing a file type containing the determined cooling structure (6, 6') in a data format as an output (12), based on which the determined cooling structure (6, 6') can be physically manufactured (9), wherein the file type containing the determined cooling structure is a vector-based file type.

2. The computer-implemented method of claim 1, further comprising a step of forming a vector-based file type by converting a pixel-based file type to a vector-based file type.

3. The computer-implemented method of claim 1 or 2, wherein the topology optimization algorithm is a non-parametric topology optimization algorithm.

4. The computer-implemented method of any one of the preceding claims, wherein the cooling fluid is embodied as water, or as a water-glycol mixture, or as a refrigerant, or as a dielectric coolant, or as mineral oil.

5. The computer-implemented method according to any one of the preceding claims, wherein using the topology optimization algorithm for determining (11) the cooling structure based on received input comprises the following steps: 1) determining a grid, in particular embodied as a regularly spaced grid or as a grid based on a digital array indicating a spatial power distribution and / or based on at least one design constraint and / or based on manufacturing constraints, 2) mapping the digital array indicating a spatial power allocation to the grid, and optionally mapping the at least one design constraint to the grid, 3) Starting with an initial geometry of the cooling structure on the grid, a current geometry of the cooling structure is adapted in an iterative method until a final geometry of the cooling structure is determined.

6. A computer-implemented method according to claim 5, wherein at each optimization iteration the following sub-steps can be implemented: i) simulating a physical behavior of the cooling structure having the current geometry using at least modeling equations, in particular the Nevi-Stokes equations and the heat transfer equations, and the physical parameters, ii) determining at least one current value of the loss function based on the simulated physical behavior, iii) determining at least one gradient of the loss function, optionally constrained, with respect to a variation of the geometry of the cooling structure away from the current geometry, in particular using an adjoint method and iv) providing the determined at least one gradient to a set, in particular programming equations, which update the current geometry in such a way that the optionally constrained loss function is further maximized.

7. The computer-implemented method of any of the preceding claims, wherein the cooling structure (6, 6') determined using the optimization algorithm is configured to be physically fabricated at least partially on the die of the semiconductor device having device logic (13).

8. A computer-implemented method according to any of the preceding claims, wherein the cooling structure includes an area at an edge of the semiconductor device without cooling channels, and wherein the optimization algorithm is configured to optimize the width of the area; and wherein a sealing bond can be provided on the area to bond the cooling structure to the semiconductor device.

9. The computer-implemented method of claim 8, wherein the region has a width between 20 micrometers and 2 millimeters.

10. A computer-implemented method according to any one of the preceding claims, wherein the cooling structure (6, 6') determined using the optimization algorithm is configured to be physically manufactured at least partially on the cooling structure die, wherein the cooling structure die is configured to be bonded to the die of the semiconductor device having device logic by an adhesive interface, and / or wherein the cooling structure die is configured to be attached to the die of the semiconductor device having device logic by an attachment layer, and / or wherein the cooling structure die is configured to be attached to the die of the semiconductor device having device logic by a thermal interface material.

11. The computer-implemented method of claim 10, wherein the optimization algorithm is configured to optimize the topology of a cooling structure by considering the thickness and / or thermal conductivity of the bonding interface between the cooling structure and the semiconductor device, and / or by considering the thickness and / or thermal conductivity of the attachment layer between the cooling structure and the semiconductor device, and / or by considering the thickness and / or thermal conductivity of the thermal interface material between the cooling structure and the semiconductor device.

12. A computer-implemented method according to any one of the preceding claims, wherein the method further receives as input at least one region of the semiconductor device as at least one design constraint (2), and wherein the optimization algorithm is constrained to determine a cooling structure (6, 6') having no cooling structure components in at least one region of the cooling structure corresponding to the at least one region of the semiconductor device.

13. A computer-implemented method according to any of the preceding claims, wherein the optimization algorithm uses a two and a half dimensional model during optimization, wherein the optimization algorithm is configured to assume a parabolic flow profile in an out-of-plane dimension of the cooling structure during the determination (11) of the cooling structure (6, 6').

14. The computer-implemented method according to any of the preceding claims, wherein the optimization algorithm uses at least one manufacturing constraint, in particular lithography constraints and etching constraints of a manufacturing process related to the determined cooling structure (6, 6') as a further optimization constraint.

15. The computer-implemented method according to any one of the preceding claims, wherein the optimization algorithm determines a number of inlets (3') and outlets (3") of the cooling structure (6, 6') and the positions of the determined inlets and outlets by taking into account packaging methodology constraints.

16. The computer-implemented method of claim 5, wherein the initial geometry of the cooling structure (6, 6') is determined based on a digital array (1) indicating a spatial power distribution.

17. A computer-implemented method according to any of the preceding claims, wherein the digital array (1) indicating a spatial power allocation diagram depicts the heat flux of the semiconductor device; and wherein the output (12) is a cooling structure, wherein areas of the cooling structure corresponding to areas of the spatial power allocation diagram with higher heat flux have narrower channels than areas of the cooling structure corresponding to areas of the spatial power allocation diagram with smaller heat flux.

18. The computer-implemented method of claim 17, wherein areas of the cooling structure corresponding to areas of the spatial power allocation diagram having smaller heat fluxes have wider channels to allow cooling liquid to flow through at a lower pressure differential than channels in those areas of the cooling structure corresponding to areas of the spatial power allocation diagram having higher heat fluxes.

19. The computer-implemented method of any one of the preceding claims, wherein the cooling structure determined in the output file type is a two-dimensional cooling design, and the method further comprises the step of extruding the two-dimensional cooling design into a three-dimensional structure.

20. The computer-implemented method of any preceding claim, further comprising a step of applying a filter to the determined cooling structure to ensure that all features of the cooling structure comply with one or more predetermined manufacturing constraints.

21. The computer-implemented method of claim 20, wherein the one or more predetermined manufacturing constraints include a minimum channel width, and / or a minimum feature width.

22. The computer-implemented method of any preceding claim, wherein the optimization algorithm is configured to recognize and adjust for non-uniform grid distributions such that the optimization algorithm is not biased by grid elements having different sizes.

23. The computer-implemented method of any preceding claim, wherein the optimization algorithm comprises a flow stabilization mechanism that reduces flow disruptions at the outlet of the cooling structure.

24. The computer-implemented method of any preceding claim, wherein the semiconductor device is a semiconductor device that exhibits non-uniform heat distribution during operation.

25. An electronic design automation tool, wherein the electronic design automation tool includes program code, when it is executed on a computing device, causing the computing device to implement a method for determining a cooling structure (6, 6') according to any one of claims 1 to 24, and wherein the electronic design automation tool also includes program code, when it is executed on a computing device, causing the computing device to implement a floor plan and / or post-layout analysis of a floor plan of device logic of a semiconductor device, and wherein the electronic design automation tool is configured to determine a digital array (1) indicating a spatial power distribution of the semiconductor device based at least on the floor plan and using post-layout analysis, and wherein the program code of the electronic design automation tool for determining a cooling structure is configured to use the digital array indicating a corresponding determination of a spatial power distribution as input.

26. A semiconductor device (9, 13) comprising a cooling structure (9) determined using the method according to any one of claims 1 to 24, wherein the cooling structure is produced using photolithography.

27. The semiconductor device (9, 13) of claim 26, wherein the device logic (13) of the semiconductor device is disposed on one side of a die of the semiconductor device, and wherein the cooling structure is disposed on an opposite side of the die relative to the side on which the device logic is disposed.

28. A semiconductor device (9, 13) according to claim 26, wherein the semiconductor device includes a first die on which the device logic (13) of the semiconductor device is arranged, and wherein the semiconductor device includes a second die on which the cooling structure (9) is arranged, wherein a physical connection between the first die and the second die is embodied as a bonding interface between the first die and the second die, and / or as an attachment layer, and / or as a thermal interface material.

29. A computer-implemented method for determining a manufacturable cooling structure (6, 6') for cooling a semiconductor device (9, 13), wherein the method receives as input (10) at least the following items: i) physical parameters of the semiconductor device, wherein the physical parameters are physical characteristics of the semiconductor device, and ii) a digital array (1) indicating a spatial power distribution of the semiconductor device, wherein the method comprises the following steps: 1) using a topology optimization algorithm to determine (11) a cooling structure (6, 6') based on the received input (10), and 2) providing a file type containing the determined cooling structure (6, 6') in a data format as an output (12), based on which the determined cooling structure (6, 6') can be physically manufactured (9), wherein the file type containing the determined cooling structure is a vector-based file type.

30. A computer-implemented method for determining a manufacturable cooling structure (6, 6') for cooling a semiconductor device (9, 13), wherein the method receives as input (10) at least the following: i) physical parameters of the semiconductor device, wherein the physical parameters are related to physical characteristics of the semiconductor device, and wherein the physical parameters include i) dimensional parameters of the semiconductor device, wherein the dimensional parameters are embodied as at least width, length, and thickness of the semiconductor device, and / or ii) material characteristics of a die of the semiconductor device having device logic (13) on the die, and / or iii) material characteristics of a cooling fluid of the cooling structure (6, 6'), and / or iv) material characteristics of a physical connection between a cooling structure die (9) having the cooling structure and a die of the semiconductor device having device logic (13) on the die; and ii) a digital array (1) indicating a spatial power distribution of the semiconductor device, wherein the digital array (1) indicating a spatial power distribution of the semiconductor device is embodied as a two-dimensional array (1') of power dissipated per unit area of ​​the semiconductor device; The method comprises the following steps: 1) using a topology optimization algorithm to determine (11) a cooling structure (6, 6') based on the received input (10), wherein the topology optimization algorithm performs a maximum value of a loss function, wherein The loss function is based on at least one of: i) pressure, ii) flow rate, iii) maximum temperature, iv) average temperature, v) median temperature, vi) temperature gradient; and 2) providing a file type containing the determined cooling structure (6, 6') in a data format as an output (12), based on which the determined cooling structure (6, 6') can be physically manufactured (9); The topology optimization algorithm used to determine (11) the cooling structure based on the received input comprises the following steps: 1) determining a grid, in particular embodied as a regularly spaced grid or as a grid based on a digital array indicating a spatial power distribution and / or based on at least one design constraint and / or based on manufacturing constraints, 2) mapping the digital array indicating a spatial power allocation to the grid, and optionally mapping the at least one design constraint to the grid, 3) Starting with an initial geometry of the cooling structure on the grid, a current geometry of the cooling structure is adapted in an iterative method until a final geometry of the cooling structure is determined.

31. The computer-implemented method of claim 29 or 30, wherein the semiconductor device is a semiconductor device that exhibits non-uniform heat distribution during operation.

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