Laser on-demand scrambling for two-level systems in superconducting qubits

Abstract

Methods and systems are provided for mitigating the effects of defects in a quantum processor. The mitigation system uses an iterative process that applies light pulses and checks for qubit relaxation time to eliminate or minimize two level system (TLS) interactions with qubits. The system applies a first light pulse to illuminate a quantum processor having one or more qubits. The system receives quantum bit relaxation times measured at different electric field frequencies after applying the first light pulse. The system applies a second light pulse to illuminate the quantum processor upon determining that the received qubit relaxation time indicates the presence of a strongly coupled TLS in the quantum processor.

Description

Technical Field

[0001] The present disclosure relates generally to quantum computing and, more particularly, to laser on-demand scrambling of superconducting qubits. Background Art

[0002] A quantum bit (qubit) is a basic element for information encoding in a quantum computer. A two-level system or TLS is a pseudo-quantum system that can be coupled to a qubit and cause decoherence. TLS is one of the main decoherence sources in superconducting quantum circuits. Typically, TLS includes two sets: a larger set of low-frequency two-level undulators (pools) and several discrete two-level systems that are close to resonance with the qubit transition. If TLS interacts strongly with the qubit, the qubit becomes inoperable due to frequency shift and decoherence.

[0003] The properties of these TLS are not fully understood, but are thought to arise from crystal defects, surface defects, or atomic-level defects in the material that generate microscopic dipoles (atomic or electron traps) that interact with the qubit (e.g., couple to the qubit's electric field). TLS are always present and randomly distributed.

[0004] The two-level system can be off-resonant or on-resonance with the qubit. On-resonance TLS is much more harmful than off-resonance TLS. These strongly coupled TLS on resonance have a significant adverse effect on the reliability of the gates in the processor. This is true for processors based on fixed frequency qubits and processors based on flux tunable qubits. Summary of the invention

[0005] Some embodiments of the present disclosure provide methods and systems for mitigating the effects of defects present in a quantum processor. In some embodiments, the mitigation system uses an iterative process of applying light pulses and checking qubit relaxation times to eliminate or minimize two-level system (TLS) interactions with qubits. The system applies a first light pulse to illuminate a quantum processor having one or more qubits. The light pulse is used to scramble the entirety of the TLS coupled to the quantum processor. The system is characterized by qubit relaxation times measured at different qubit frequencies after applying the first light pulse. The system applies a second light pulse to illuminate the quantum processor when it is determined that the received qubit relaxation time indicates that a strongly coupled TLS exists in the quantum processor.

[0006] In some embodiments, the system may determine whether to apply a second light pulse based on a TLS configuration of the quantum processor, the TLS configuration being determined based on the received qubit relaxation times at different qubit frequencies. The system may determine whether to apply the second light pulse based on whether the TLS is interacting with the qubit based on the TLS configuration. Subsequently, a third light pulse may be applied, and subsequent light pulses thereafter. Light pulses will continue to be applied until the quantum processor is characterized by an acceptable TLS configuration.

[0007] In some embodiments, the system receives performance parameters (e.g., coherence properties) of one or more qubits in the quantum processor to identify qubits that do not meet a performance threshold. The received qubit relaxation time includes the relaxation time of the identified qubit. In embodiments that may be combined with the previous embodiments, the first light pulse and the second light pulse are local to the identified qubit and illuminate only the identified qubit without illuminating other qubits. In some embodiments, the first light pulse and the second light pulse are global to the quantum processor and illuminate multiple qubits in the quantum processor.

[0008] Two-level systems are one of the most fundamental problems in superconducting qubits because they are the main source of decoherence. The ability to focus light on a specific qubit could allow for rapid improvements in the coherence of the qubit, rather than relying on time-consuming processes such as heating up the entire quantum processor.

[0009] The foregoing summary is intended to serve as a brief introduction to some embodiments of the present disclosure. This is not meant to be an introduction or overview of all the subject matter disclosed in this document. The following detailed description and the drawings referenced in the detailed description will further describe the embodiments described in the summary as well as other embodiments. Therefore, in order to understand all the embodiments described by this document, a summary, detailed description and drawings are provided. In addition, the subject matter claimed is not limited by the illustrative details in the summary, detailed description and drawings, but is defined by the appended claims, because the subject matter claimed may be embodied in other specific forms without departing from the spirit of the present subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings are drawings of illustrative embodiments. They do not show all embodiments. Additionally or alternatively, other embodiments may be used. Details that may be obvious or unnecessary may be omitted to save space or for more effective description. Some embodiments may be practiced using additional components or steps and / or not using all components or steps shown. When the same number appears in different drawings, it refers to the same or similar components or steps.

[0011] Figure 1 A two-level system (TLS) mitigation system consistent with an illustrative embodiment that uses illumination to mitigate the effects of TLS in a quantum processor.

[0012] Figure 2 A method for measuring the performance of a quantum bit consistent with an illustrative embodiment is shown. The method can be used by a measurement system.

[0013] Figure 3 An example TLS frequency landscape is shown consistent with an illustrative embodiment.

[0014] Figure 4 A quantum processor having qubits illuminated by an optical fiber is shown consistent with an illustrative embodiment.

[0015] Figure 5 Spectral plots of a qubit in a quantum processor before and after illumination are shown, consistent with an illustrative embodiment.

[0016] Figure 6 A process for iteratively applying illumination to a quantum processor for eliminating strongly coupled TLS interactions, consistent with an illustrative embodiment, is conceptually shown.

[0017] Figure 7 A block diagram of components of a data processing system is shown in accordance with an illustrative embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] In the following detailed description, many specific details are set forth by way of example in order to provide a thorough understanding of the relevant description. However, it should be understood that the description can be practiced without these details. In other examples, well-known methods, procedures, components and / or circuit arrangements have been described at a relatively high level without details in order to avoid unnecessarily obscuring various aspects of the description.

[0019] Because strong coupling TLS is significantly harmful to the performance of qubits in a large number of subcircuits, it is prominent to develop methods to shift their frequencies to non-resonance.TLSs are shown to be tunable in frequency by electric fields and by material strain, because TLSs tend to drift slowly in frequency over time (spectral diffusion) in the time scale of hours to days. Therefore, TLS can be alleviated by waiting for its diffusion in large quantities.TLS can also be removed from qubits by heating or thermally cycling the entire processor until several Kelvins. Heating the entire processor is a very time-consuming process because it usually takes a long time (e.g., several hours) and involves a complete recalibration of the processor. Heating the entire processor is also a random global process that cannot be used for a specific qubit of the target. It is uncertain that any specific TLS will shift the frequency by global heating. There is also a possibility that the qubit previously fed from the TLS can interact with another TLS after heating.

[0020] Some embodiments provide methods and systems for mitigating the effects of strongly coupled two-level systems. Specifically, optical illumination is used to scramble the frequency of the two-level system. Scrambling the TLS distribution is used to improve the coherence time and is used to maintain stable quantum processor performance over time. Optical illumination can use telecommunication frequency light at 1310nm and 1550nm. In some embodiments, optical illumination is delivered to a quantum processor or any array of qubits through a dilution refrigerator, where light is selectively focused on a single qubit or is globally applied to all qubits of the quantum processor.

[0021] Figure 1 A TLS mitigation system 100 is shown that uses illumination to mitigate the effects of TLS in a quantum processor 110. As shown, a TLS mitigation controller 120 controls a qubit measurement system 130 and an illumination system 140. The qubit measurement system 130 is used to detect or identify TLS in the quantum processor 110. The illumination system 140 is used to apply electromagnetic pulses to the quantum processor 110 that can change the frequency of one or more TLS (e.g., light).

[0022] The measurement system 130 provides performance parameters of the qubits in the quantum processor 110, including the decoherence time (or relaxation time) of the qubits at different electric field frequencies. In some embodiments, the performance parameters of the qubits at different frequencies are captured. The mitigation controller 120 can use these captured performance parameters of the qubit to generate a spectrum diagram for the qubit. The spectrum diagram can be used as a TLS pattern to identify frequencies at which TLS is strongly coupled to the qubit (e.g., by identifying frequencies at which the decoherence time of the qubit is reduced by more than 25%)

[0023] Illumination system 140 is used to provide light pulses to quantum processor 110. The light pulses can scramble the frequency landscape of the TLSs so that the TLSs will not couple strongly with the qubit, e.g., become non-resonant, so that the decoherence time of the qubit is at least 75% of the ideal or expected relaxation time.

[0024] The TLS mitigation controller 120 may use the TLS profile generated based on the measurements provided by the measurement system 130 to determine when and how to apply light pulses to the quantum processor 110 and when and how to control the illumination system 140 accordingly.

[0025] In some embodiments, one or more laser sources are used to scramble the frequency of TLS. Laser pulses are used to change the TLS situation of a superconducting quantum processor on a very short time scale (e.g., less than one second). In some embodiments, very short laser pulses can be applied to instantaneously shift the TLS frequency. The recovery time from the laser pulse is on a time scale of seconds (or less) compared to the hours that may be involved in heating the entire quantum processor. The light pulses can be visible light or infrared light.

[0026] Figure 2 A method for measuring the performance of a qubit is conceptually illustrated. A microwave pulse 200 of calibrated amplitude, frequency, and duration is applied to the qubit to place the qubit in its excited state. After the microwave pulse is applied, the state of the qubit is measured at a plurality of different delay times. The measurements are repeated and averaged to give a characteristic exponential decay curve 210. (The vertical axis of the decay curve 210 refers to the ratio of measurements made on the qubit in which the qubit was found to be in an excited state at a given delay time, so 1.0 corresponds to finding the qubit in an excited state in 100% of the cases of measurements made at a given delay time).

[0027] The defect can be resonantly coupled to the qubit and act as a strong energy relaxation channel with a Lorentzian spectral signature. This signature can be used to identify the defect. Figure 3 Example TLS scenarios are shown. The TLS scenarios are based on measurements of flux-tunable qubits that exhibit multiple regions of strong TLS coupling. If a fixed frequency transmission accidentally has a transition frequency in a region close to strong TLS, the qubit performance becomes severely degraded, i.e., has a significantly shortened relaxation or decoherence time. In the accompanying figures, the measured qubit relaxation time (also referred to as T1) is normalized relative to the ideal or expected relaxation time. Therefore, at frequencies with weak or no TLS coupling, the normalized relaxation time is close to 1.0, while at frequencies with strong TLS coupling, the normalized relaxation time can drop significantly (to 0.1 or less).

[0028] Figure 4 A quantum processor with a qubit is shown, which is illuminated by an optical fiber. The quantum processor can be constructed on silicon, sapphire, or other dielectric substrates. In some embodiments, a laser or optical fiber pierces the quantum processor chip to provide illumination. As shown, an optical fiber 400 is attached to a housing 405 above the quantum processor 110. Light pulses can be directed from the outside of the housing to illuminate part or all of the quantum processor 110. Since silicon is transparent to infrared light with a wavelength of 1100nm or longer, the quantum processor can be illuminated from either surface (front or back). The light pulse applied to the quantum processor or qubit can shift or scramble the frequency situation of TLS. It can be shown that after the light pulse, TLS can move in frequency in a random manner. On the other hand, in the absence of an applied light pulse, TLS can remain almost constant for hours.

[0029] Figure 5 Spectrum graphs of qubits in a quantum processor before and after irradiation are shown. The figure shows two spectrum graphs 510 and 520 showing the relaxation times of qubits in a quantum processor at different frequencies. The first spectrum graph 510 is based on measurements of qubits taken before applying a light pulse, and the second spectrum graph 520 is based on measurements of qubits taken after applying a light pulse. As shown, after applying the light pulse, the distribution of qubit relaxation times at different frequencies shifts. This is because the TLS in the quantum processor has been scrambled by the applied light pulse. Based on the TLS situation as shown by the spectrum graph 520, the TLS mitigation controller 120 can determine that (i) at the frequency of interest, TLS will not significantly weaken the operation of the qubit, or (ii) the qubit is still weakened by TLS at the frequency of interest, so that additional light pulses are needed to further scramble TLS. This determination can be determined by whether the relaxation time of the qubit has dropped to a specific threshold ratio (e.g., 0.75 or 75%) below the expected relaxation time.

[0030] Since the laser operates very fast, the process of TLS frequency scrambling by laser irradiation can be iterated several times to find the ideal TLS configuration in which all severe or strongly coupled TLS interactions have been eliminated. This will significantly improve the functionality of the quantum processor. The ability to quickly cycle through TLS configurations and find the optimal configuration has a significant impact on the performance on any large-scale fixed-frequency quantum processor.

[0031] Figure 6A process 600 for iteratively applying irradiation to a quantum processor for eliminating strongly coupled TLS interactions consistent with an illustrative embodiment is conceptually shown. The TLS mitigation system 100 or the TLS mitigation controller 120 can perform the process to mitigate the harmful effects of TLS for preparing the quantum processor for use. The process rearranges the TLS situation by rapidly cycling through the TLS configuration. The characteristics of the qubits are measured to determine whether scrambling by irradiation can improve processor performance. An iterative search is performed to find a good global TLS configuration for different qubits across the quantum processor. In some embodiments, one or more processing units (e.g., processors) of a computing device implementing the TLS mitigation controller 120 perform the process 600 by executing instructions stored in a computer-readable medium.

[0032] The system measures (at block 605) the coherence properties of all qubits. Figure 2 Example methods for measuring qubits are described.

[0033] The system determines (at block 610) whether one or more qubits do not meet a performance criterion. The system may receive performance parameters (e.g., coherence properties) of one or more qubits in the quantum processor to identify qubits that do not meet a performance threshold. If no qubits do not meet a performance criterion, the system proceeds to 650 to calibrate the quantum processor, thus preparing it for use. If at least one qubit does not meet a performance criterion, the process proceeds to 620.

[0034] At block 620, the system illuminates one or more qubits in the processor. The system may apply a global light pulse to the processor such that multiple qubits in the quantum processor are illuminated. The system may also use local light pulses confined to qubits that are identified as experiencing bad TLS interactions.

[0035] The system performs (at block 630) spectroscopy (e.g., Stark spectroscopy, which is a method of obtaining small rapid frequency tuning of a qubit through the AC Stark effect) on the qubits of the processor to obtain a spectrum plot as a TLS profile. The TLS profile of a qubit is a collection of qubit relaxation times measured across different probe frequencies. The system receives or captures qubit relaxation times measured at different qubit frequencies, including relaxation times measured before and after a light pulse. In some embodiments, the system may perform multiple sweeps of frequency to obtain multiple sets of relaxation times. Because the system identifies qubits that do not meet performance requirements, and the received qubit relaxation times will include relaxation times for the identified faulty qubits.

[0036] The system determines (at box 640) whether the TLS situation is acceptable, for example, whether there is a good global TLS configuration across different qubits of the quantum processor, or whether there is strong coupling TLS in the quantum processor. If the TLS situation is acceptable, the process proceeds to 650 to calibrate the quantum processor, thus preparing it for use. If the TLS situation is unacceptable, for example, there is strong coupling between the qubits and TLS to cause severe degradation of the decoherence time (for example, less than 75% of the expected qubit relaxation time), the process returns to 620 to apply laser pulses again and measure qubit performance. In other words, the system applies a first light pulse to illuminate the quantum processor, and then determines whether to apply a second light pulse to illuminate the quantum processor based on the current TLS configuration or situation. This is an iterative process of applying light pulses and checking qubit relaxation times to eliminate or minimize TLS interactions with qubits.

[0037] The present application may use systems, methods and / or computer program products at any possible level of integrated technical detail. The computer program product may include a computer-readable storage medium (or multiple media) having computer-readable program instructions thereon, which are used to cause a processor to perform various aspects of the present disclosure.

[0038] Computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. Computer readable storage medium can be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer readable storage medium includes the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device such as a punch card or a raised structure in a groove with instructions recorded thereon, and any suitable combination of the foregoing. Computer readable storage medium as used herein should not be interpreted as a transient signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated by a waveguide or other transmission medium (e.g., a light pulse by an optical fiber cable), or an electrical signal transmitted by a wire.

[0039] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). The network may include a copper transmission cable, an optical transmission fiber, a wireless transmission, a router, a firewall, a switch, a gateway computer, and / or an edge server. The network adapter card or the network interface in each computing / processing device receives the computer-readable program instructions from the network, and forwards the computer-readable program instructions for storage in the computer-readable storage medium in the corresponding computing / processing device. The computer-readable program instructions for performing the operation of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcodes, firmware instructions, state setting data, configuration data for an integrated circuit device, or source code or object code written in any combination of one or more programming languages ​​(including object-oriented programming languages, such as Smalltalk, C++, etc.) and procedural programming languages ​​(such as "C" programming languages ​​or similar programming languages). The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as an independent software data package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider via the Internet). In some embodiments, an electronic circuit device including, for example, a programmable logic circuit device, a field programmable gate array (FPGA), or a programmable logic array (PLA) may execute the computer-readable program instructions by utilizing the state information of the computer-readable program instructions to personalize the electronic circuit so as to perform various aspects of the present disclosure.

[0040] Various aspects of the present disclosure are described herein with reference to the flowchart illustration and / or block diagram of the method, device (system) and computer program product according to the embodiment of the present disclosure. It will be understood that each frame of the flowchart illustration and / or block diagram and the combination of frames in the flowchart illustration and / or block diagram can be implemented by computer-readable program instructions. These computer-readable program instructions can be provided to the processor of a computer or other programmable data processing device to produce a machine, so that the instructions executed by the processor of a computer or other programmable data processing device create a mode for implementing the function / action specified in one or more frames of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, which can guide a computer, a programmable data processing device and / or other equipment to run in a particular manner, so that the computer-readable storage medium with instructions stored therein includes a product, and the product includes instructions for implementing various aspects of the function / action specified in one or more frames of the flowchart and / or block diagram.

[0041] Computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operating steps to be executed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, so that the instructions executed on the computer, other programmable apparatus, or other device implement the functions / actions specified in one or more blocks of the flowchart and / or block diagram. Figure 6 ) illustrate possible implementation architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each box in a flowchart or block diagram may represent a module, segment, or portion of an instruction, which includes one or more executable instructions for implementing (multiple) specified logical functions. In some alternative embodiments, the functions noted in the box may not occur in the order noted in the accompanying drawings. For example, two boxes shown in succession may actually be executed substantially simultaneously, or the boxes may sometimes be executed in reverse order, depending on the functions involved. It will also be noted that each box illustrated in the block diagram and / or flowchart and the combination of boxes in the block diagram and / or flowchart may be implemented by a dedicated hardware-based system that performs a specified function or action or performs a combination of dedicated hardware and computer instructions.

[0042] Figure 7 1 is a block diagram of components of data processing systems 700 and 750 that may be used to implement TLS mitigation controller 120 according to an illustrative embodiment of the present disclosure. It should be understood that Figure 7 This is only a description of one implementation and does not imply any limitation on the environments in which different embodiments may be implemented. Many modifications to the depicted environment may be made based on design and implementation requirements.

[0043] Data processing systems 700 and 750 represent any electronic device capable of executing machine-readable program instructions. Data processing systems 700 and 750 may represent smart phones, computer systems, PDAs, or other electronic devices. Examples of computing systems, environments, and / or configurations that may be represented by data processing systems 700 and 750 include, but are not limited to, personal computer systems, server computer systems, thin clients, fat clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, network PCs, small computer systems, and distributed cloud computing environments that include any of the above systems or devices.

[0044] Data processing systems 700 and 750 may include Figure 7 The set of internal components 705 and the set of external components 755 are shown in FIG. The set of internal components 705 includes one or more processors 720, one or more computer-readable RAMs 722 and one or more computer-readable ROMs 724 on one or more buses 726, and one or more operating systems 728 and one or more computer-readable tangible storage devices 730. One or more operating systems 728 and programs such as those used to perform process 600 are stored on one or more computer-readable tangible storage devices 730 for execution by one or more processors 720 via one or more RAMs 722 (which typically include cache memory). Figure 7 In the illustrated embodiment, each of the computer-readable tangible storage devices 730 is a disk storage device of an internal hard drive. Alternatively, each of the computer-readable tangible storage devices 730 is a semiconductor memory device such as ROM 724, EPROM, flash memory, or any other computer-readable tangible storage device that can store computer programs and digital information.

[0045] The internal components 705 collection also includes an R / W drive or interface 732 to read from and write to one or more portable computer-readable tangible storage devices 786, such as a CD-ROM, DVD, memory stick, tape, disk, optical disk, or semiconductor storage device. Instructions for performing the process 600 may be stored on one or more of the respective portable computer-readable tangible storage devices 786, read via the respective R / W drive or interface 732, and loaded into the respective hard disk drive 730.

[0046] The internal components 705 collection may also include a network adapter (or switch port card) or interface 736, such as a TCP / IP adapter card, a wireless Wi-Fi interface card, or a 3G or 4G wireless interface card or other wired or wireless communication link. The instructions of the process or program described above can be downloaded from an external computer (e.g., a server) via a network (e.g., the Internet, a local area network or other wide area network) and a corresponding network adapter or interface 736. The instructions and data of the described program or process are loaded from the network adapter (or switch port adapter) or interface 736 into the corresponding hard disk drive 730. The network may include copper wire, optical fiber, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers.

[0047] The external components 755 set may include a computer display monitor 770, a keyboard 780, and a computer mouse 784. The external components 755 set may also include a touch screen, a virtual keyboard, a touch pad, a pointing device, and other human-computer interface devices. The internal components 705 set also includes a device driver 740 to interface with the computer display monitor 770, the keyboard 780, and the computer mouse 784. The device driver 740, the R / W driver or interface 732, and the network adapter or interface 736 include hardware and software (stored in the storage device 730 and / or ROM 724).

[0048] The description of various embodiments of the present description has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements existing in the market, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method comprising: applying a first light pulse to a quantum processor comprising one or more qubits; receiving qubit relaxation times measured at different qubit frequencies after applying the first light pulse; as well as Upon determining that the received qubit relaxation time indicates the presence of a strongly coupled two-level system (TLS) in the quantum processor, a second light pulse is applied to illuminate the quantum processor.

2. The method of claim 1, wherein the optical pulses scramble the frequency profile of the TLS.

3. A method according to any one of the preceding claims, wherein the presence of strongly coupled TLS in the quantum processor is indicated by a threshold ratio of the received qubit relaxation time being less than an expected qubit relaxation time at a frequency of interest.

4. A method according to any one of the preceding claims, wherein the threshold ratio is 0.

75.

5. The method of any of the preceding claims, further comprising receiving performance parameters of one or more qubits in the quantum processor to identify qubits that do not meet a performance threshold, wherein the received qubit relaxation times include relaxation times of the identified qubits.

6. The method of claim 5, wherein the first light pulse and the second light pulse are local to the identified quantum bit.

7. A method according to any one of the preceding claims, wherein the first light pulse and the second light pulse are global to the quantum processor and illuminate a plurality of qubits in the quantum processor.

8. A computer program product comprising: One or more non-transitory computer-readable storage devices and program instructions stored on at least one of the one or more non-transitory storage devices, the program instructions being executable by a processor, the program instructions comprising a set of instructions for: applying a first light pulse to illuminate a quantum processor comprising one or more qubits; receiving qubit relaxation times measured at different qubit frequencies after applying the first light pulse; as well as Upon determining that the received qubit relaxation time indicates the presence of a strongly coupled two-level system (TLS) in the quantum processor, a second light pulse is applied to illuminate the quantum processor.

9. The computer program product of claim 8, wherein the optical pulses are used to scramble the frequency landscape of the TLS.

10. A computer program product according to any one of the preceding claims 8 to 9, wherein the presence of strongly coupled TLS in the quantum processor is indicated by a threshold ratio of the received qubit relaxation time being less than an expected qubit relaxation time at a frequency of interest.

11. The computer program product of claim 10, wherein the threshold ratio is 0.

75.

12. A computer program product according to any of the preceding claims 8 to 11, wherein the set of instructions further comprises receiving performance parameters of one or more qubits in the quantum processor to identify qubits that do not meet a performance threshold, wherein the received qubit relaxation time comprises a relaxation time of the identified qubit.

13. The computer program product of claim 12, wherein the first light pulse and the second light pulse are local to the identified qubit and illuminate only the identified qubit and not other qubits.

14. The computer program product of any preceding claim 8 to 13, wherein the first light pulse and the second light pulse are global to the quantum processor and illuminate a plurality of qubits in the quantum processor.

15. A system comprising: A quantum processor comprising one or more quantum bits; A two-level system (TLS) mitigation controller, the TLS mitigation controller configured to perform actions, the actions comprising: applying a first light pulse to illuminate a quantum processor comprising one or more qubits; receiving qubit relaxation times measured at different qubit frequencies after applying the first light pulse; and Upon determining that the received qubit relaxation time indicates the presence of a strongly coupled TLS in the quantum processor, applying a second light pulse to illuminate the quantum processor.

16. The system of claim 15, wherein the light pulses are used to scramble the TLS in the quantum processor.

17. A system according to any of the preceding claims 15 to 16, wherein the presence of strongly coupled TLS in the quantum processor is indicated by a threshold ratio of the received qubit relaxation time being less than an expected qubit relaxation time at a frequency of interest. The system of claim 17 , wherein the threshold ratio is 0.

75.

19. The system of any of claims 15 to 18, wherein the actions further comprise receiving performance parameters of one or more qubits in the quantum processor to identify qubits that do not meet a performance threshold, wherein the received qubit relaxation times comprise relaxation times of the identified qubits.

20. The system of claim 19, wherein the first light pulse and the second light pulse are local to the identified qubit and illuminate only the identified qubit and not other qubits.

21. The system of any preceding claim 15 to 20, wherein the first light pulse and the second light pulse are global to the quantum processor and illuminate a plurality of qubits in the quantum processor.

22. A method comprising: Providing a quantum processor including one or more quantum bits; A TLS mitigation controller is configured to perform actions including: applying a first light pulse to illuminate a quantum processor comprising one or more qubits; receiving qubit relaxation times measured at different electric field frequencies after applying the first light pulse; and A second light pulse is applied to illuminate the quantum processor upon determining that the received qubit relaxation time indicates the presence of a strongly coupled TLS in the quantum processor.

23. The method of claim 22, wherein the presence of strongly coupled TLS in the quantum processor is indicated by a threshold ratio of the received qubit relaxation time being less than an expected qubit relaxation time at a frequency of interest. The method of claim 23 , wherein the threshold ratio is 0.

75.

25. The method of any of claims 22 to 24, wherein the actions further comprise receiving performance parameters of one or more qubits in the quantum processor to identify qubits that do not meet a performance threshold, wherein the received qubit relaxation times comprise relaxation times of the identified qubits.

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