Hybrid low power rail-to-rail amplifier with leakage control

Abstract

An amplifier includes first and second input transistors, a first current mirror, a second current mirror, and a third current mirror. An input terminal of the first current mirror is coupled to a drain of the first input transistor, an input terminal of the second current mirror is coupled to a drain of the second input transistor, and an input terminal of the third current mirror is coupled to an output terminal of the first current mirror. An output terminal of the first current mirror and an output terminal of the third current mirror are coupled to an output of the amplifier. The amplifier also includes a third input transistor and a fourth input transistor, where a drain of the third input transistor is coupled to the input terminal of the third current mirror and a drain of the fourth input transistor is coupled to the output of the amplifier.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of U.S. patent application serial number 17 / 964,608 filed in the U.S. Patent Office on October 12, 2022, the entire contents of which are incorporated herein as if fully set forth in their entirety below and for all applicable purposes. background Technical Field

[0004] Aspects of the present disclosure relate generally to amplifiers, and more particularly to hybrid amplifiers. Background Art

[0005] The receiver may include one or more amplifiers for amplifying one or more signals received by the receiver. For example, in a memory system (e.g., a double data rate (DDR) memory system), the receiver may include one or more amplifiers for amplifying one or more signals (e.g., data signals) received from a memory chip (e.g., a DDR memory) or a memory controller. Summary of the invention

[0006] The following content presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an exhaustive overview of all contemplated implementations, and is not intended to identify key or important elements of all implementations, nor is it intended to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is presented later.

[0007] A first aspect relates to a system. The system includes an amplifier. The amplifier includes: a first input transistor, wherein the gate of the first input transistor is coupled to the first input terminal of the amplifier; and a second input transistor, wherein the gate of the second input transistor is coupled to the second input terminal of the amplifier. The amplifier also includes: a first current mirror, wherein the input terminal of the first current mirror is coupled to the drain of the first input transistor; and a second current mirror, wherein the input terminal of the second current mirror is coupled to the drain of the second input transistor, and the output terminal of the second current mirror is coupled to the output terminal of the amplifier. The amplifier also includes a third current mirror, wherein the input terminal of the third current mirror is coupled to the output terminal of the first current mirror, and the output terminal of the third current mirror is coupled to the output terminal of the amplifier. The amplifier also includes a third input transistor, wherein the gate of the third input transistor is coupled to the first input terminal of the amplifier, and the drain of the third input transistor is coupled to the input terminal of the third current mirror. The amplifier also includes a fourth input transistor, wherein the gate of the fourth input transistor is coupled to the second input terminal of the amplifier, and the drain of the fourth input transistor is coupled to the output terminal of the amplifier.

[0008] A second aspect relates to a method for amplifying a signal. The method includes: driving a first input transistor and a second input transistor with the signal; multiplying a first current from the first input transistor using a first current mirror to obtain a multiplied first current; and multiplying a second current from the second input transistor using a second current mirror to obtain a multiplied second current. The method also includes: driving a third input transistor and a fourth input transistor with the signal; combining a third current from the third input transistor with the multiplied first current to obtain a combination of the third current and the multiplied first current; and combining a fourth current from the fourth input transistor with the multiplied second current to obtain a combination of the fourth current and the multiplied second current. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 Examples of multiple chips according to certain aspects of the present disclosure are shown.

[0010] Figure 2 Examples of a transmitter, a receiver, and a link between the transmitter and the receiver are shown in accordance with certain aspects of the present disclosure.

[0011] Figure 3A An example of a transconductance amplifier according to certain aspects of the present disclosure is shown.

[0012] Figure 3B An exemplary implementation of a current mirror in a transconductance amplifier according to certain aspects of the present disclosure is shown.

[0013] Figure 4A An example of a current mirror amplifier according to certain aspects of the present disclosure is shown.

[0014] Figure 4B An exemplary implementation of a current mirror in a current mirror amplifier according to certain aspects of the present disclosure is shown.

[0015] Figure 5 An example of a hybrid amplifier according to certain aspects of the present disclosure is shown.

[0016] Figure 6 An exemplary implementation of a current mirror in a hybrid amplifier according to certain aspects of the present disclosure is shown.

[0017] Figure 7 An example of a current mirror with an adjustable current mirror factor according to certain aspects of the present disclosure is shown.

[0018] Fig. 8A An example of a hybrid amplifier with a leakage controlled switch in a first mode is shown, in accordance with certain aspects of the present disclosure.

[0019] Figure 8B An example of a hybrid amplifier with a leakage controlled switch in a second mode is shown in accordance with certain aspects of the present disclosure.

[0020] Figure 8C Another example of a hybrid amplifier with a leakage controlled switch in a first mode according to certain aspects of the present disclosure is shown.

[0021] Fig.8D Another example of a hybrid amplifier with a leakage controlled switch in a second mode in accordance with certain aspects of the present disclosure is shown.

[0022] Fig. 9 An exemplary implementation of a leakage control switch according to certain aspects of the present disclosure is shown.

[0023] Fig. 10A An exemplary implementation of a first variable resistor according to certain aspects of the present disclosure is shown.

[0024] Fig. 10B An exemplary implementation of a second variable resistor according to certain aspects of the present disclosure is shown.

[0025] Fig.11 An exemplary implementation of a NAND gate according to certain aspects of the present disclosure is shown.

[0026] Fig.12 is a flow chart illustrating a method for amplifying a signal according to certain aspects of the present disclosure. DETAILED DESCRIPTION

[0027] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. In order to provide a comprehensive understanding of the various concepts, the specific embodiments include specific details. However, it is apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, in order to avoid obscuring such concepts, well-known structures and components are shown in block diagram form.

[0028] Figure 1 An example of a first chip 110 and a second chip 120 according to certain aspects is shown. The first chip 110 and the second chip 120 can be mounted on a substrate 125 (e.g., a printed circuit board, a ceramic substrate, etc.). However, it should be understood that in some specific implementations, the first chip 110 and the second chip 120 need not be mounted on a substrate.

[0029] Figure 1 Also shown are a plurality of links 130 (also referred to as channels) coupled between the first chip 110 and the second chip 120 to facilitate chip-to-chip (i.e., die-to-die) communication between the chips 110 and 120. The links 130 may include transmission lines (e.g., metal traces) on the substrate 125 and / or transmission lines embedded in the substrate 125. In this example, each of the chips 110 and 120 may include one or more transmitters (also referred to as drivers) for transmitting signals to the other of the chips 110 and 120 via one or more of the links 130, and each of the chips 110 and 120 may include one or more receivers for receiving signals from the other of the chips 110 and 120 via one or more of the links 130. Each of these receivers may include one or more amplifiers.

[0030] In one example, the first chip 110 may include one or more processors and a memory controller, and the second chip 120 may include a memory circuit (e.g., a double data rate (DDR) memory), or vice versa. In this example, the memory controller may be configured to provide access to the memory circuit to the one or more processors, as discussed further below. However, it should be understood that the present disclosure is not limited to memory and may be applied to other applications.

[0031] Figure 2 Shown by Figure 1An example of chip-to-chip communication of a link 230 among the plurality of links 130 shown. In this example, a first chip 110 includes a transmitter 210 (also referred to as a driver), a first pad 220 coupled to a first output 214 of the transmitter 210, and a second pad 222 coupled to a second output 216 of the transmitter 210. A second chip 120 includes a receiver 240, a first pad 242, and a second pad 244. The receiver 240 includes an amplifier 250, wherein a first input 252 of the amplifier 250 is coupled to the first pad 242, and a second input 254 of the amplifier 250 is coupled to the second pad 244. The link 230 may be a differential link including a first transmission line 232 and a second transmission line 234. The first transmission line 232 is coupled between the first pad 220 of the first chip 110 and the first pad 242 of the second chip 120. The second transmission line 234 is coupled between the second pad 222 of the first chip 110 and the second pad 244 of the second chip 120.

[0032] In operation, the transmitter 210 receives a signal (e.g., a data signal) at the input terminal 212 and transmits the signal to the second chip 120 via the link 230. In one example, the transmitter 210 may transmit the signal as a differential signal including a first signal and a second signal, wherein the first signal is transmitted via the first transmission line 232 and the second signal is transmitted via the second transmission line 234. However, it should be understood that the present disclosure is not limited to this example.

[0033] In one example, the first chip 110 includes a memory controller (e.g., a DDR memory controller), and the transmitter 210 is included in a physical layer (PHY) (e.g., a DDR PHY) or an I / O interface that interfaces the memory controller with the second chip 120. In this example, the signal sent by the transmitter 210 may include data, addresses, and / or commands to be sent to a memory circuit (e.g., a DDR memory) on the second chip 120. In another example, the first chip 110 includes a memory circuit (e.g., a DDR memory) coupled to the transmitter 210. In this example, the signal sent by the transmitter 210 may include data to be transmitted to the memory controller on the second chip 120 (e.g., data read from the memory circuit).

[0034] The amplifier 250 in the receiver 240 receives the signal from the transmitter 210 via the link 230, amplifies the signal, and outputs the amplified signal at the output 256. For the example in which the second chip 120 includes a memory circuit, the amplifier 250 may output the amplified signal to a read / write circuit (not shown) in the memory circuit. In this example, the read / write circuit may write the data in the signal to one or more memory cells in the memory circuit. For the example in which the second chip 120 includes a memory controller, the amplifier 250 may output the amplified signal to the memory controller. In this example, the memory controller may forward the data in the signal to one or more processors on the second chip 120. For the example in which the signal from the transmitter 210 is a differential signal including a first signal and a second signal, the amplifier 250 may receive the first signal at the first input 252 and the second signal at the second input 254.

[0035] It should be appreciated that the receiver 240 may include one or more additional components (not shown) in addition to the amplifier 250. For example, in some implementations, the receiver 240 may include one or more output buffers (not shown) coupled to the output 256 of the amplifier 250. It should also be appreciated that the amplifier 250 is not limited to memory and may be used in other applications where an amplifier is desired.

[0036] Amplifier 250 can be implemented using various types of amplifiers. One type of amplifier is a cascode amplifier (e.g., a folded cascode amplifier). However, a cascode amplifier may include a stack of four or more transistors between a power rail and a low rail (e.g., a ground rail), which may require a relatively large supply voltage to keep the transistors operating in a saturation region. Therefore, it may be difficult to operate a cascode amplifier at low power at a low supply voltage.

[0037] Another type of amplifier that can be used is a transconductance amplifier. In this regard, Figure 3A An example of a transconductance amplifier 310 according to certain aspects is shown. The transconductance amplifier 310 may also be referred to as an operational transconductance amplifier (OTA). The transconductance amplifier 310 includes a first input transistor 320, a second input transistor 325, a supply current circuit 326, and a current mirror 330. Figure 3A In the example of , each of the input transistors 320 and 325 is implemented with a respective n-type transistor (eg, an n-type field effect transistor (NFET), also referred to as an n-type metal oxide semiconductor (NMOS) transistor).

[0038] The current mirror 330 has an input terminal 332 and an output terminal 334 . The current mirror 330 is configured to mirror (ie, replicate) a current flowing through the input terminal 332 at the output terminal 334 .

[0039] Supply current circuit 326 is configured to control current flow from a supply rail having supply voltage Vdd. As discussed further below, supply current circuit 326 may be implemented with current limiting resistors (also referred to as clamping resistors), current source transistors, and the like.

[0040] exist Figure 3A In the example of FIG. 1 , the gate of the first input transistor 320 is coupled to the first input terminal 312 of the transconductance amplifier 310, and the drain of the first input transistor 320 is coupled to the input terminal 322 of the current mirror 330. The gate of the second input transistor 325 is coupled to the second input terminal 314 of the transconductance amplifier 310, and the drain of the second input transistor 325 is coupled to the output terminal 316 of the transconductance amplifier 310. The supply current circuit 326 is coupled between the sources of the input transistors 320 and 325 and a low rail (e.g., a ground rail). As used herein, a "low rail" has a lower potential than the supply rail and may be coupled to ground or another potential lower than the supply voltage Vdd. The output terminal 316 of the transconductance amplifier 310 is located between the output terminal 334 of the current mirror 330 and the drain of the second input transistor 325.

[0041] In operation, the transconductance amplifier 310 receives a differential input signal (e.g., a differential voltage) including a first input signal inp at a first input terminal 312 and a second input signal inn at a second input terminal 314. In some implementations, the input terminals may also be pseudo-differential. The first input transistor 320 generates a first current at the drain of the first input transistor 320 based on the first input signal inp, and the second input transistor 325 generates a second current at the drain of the second input transistor 325 based on the second input signal inn. The current mirror 330 mirrors the first current at the output terminal 334 of the current mirror 330, which is coupled to the output terminal 316 of the transconductance amplifier 310. Therefore, the first current and the second current are combined at the output terminal 316 of the transconductance amplifier 310. In this example, the voltage gain of the transconductance amplifier 310 may be approximately equal to the transconductance of the transconductance amplifier 310 and the load resistance at the output terminal 316.

[0042] Figure 3BAn exemplary implementation of a current mirror 330 and a supply current circuit 326 according to certain aspects is shown. In this example, the current mirror 330 includes a first current mirror transistor 338 and a second current mirror transistor 340, wherein each of the current mirror transistors 338 and 340 is implemented with a respective p-type transistor (e.g., a p-type field effect transistor (PFET), also referred to as a p-type metal oxide semiconductor (PMOS) transistor). The source of the first current mirror transistor 338 is coupled to the supply rail, the drain of the first current mirror transistor 338 is coupled to the input terminal 332, and the gate of the first current mirror transistor 338 is coupled to the drain of the first current mirror transistor 338. The source of the second current mirror transistor 340 is coupled to the supply rail, the drain of the second current mirror transistor 340 is coupled at the output terminal 334, and the gate of the second current mirror transistor 340 is coupled to the gate of the first current mirror transistor 338.

[0043] In operation, current mirror 330 mirrors (ie, copies) the current flowing through first current mirror transistor 338 to second current mirror transistor 340. In one example, current mirror transistors 338 and 340 may have approximately the same channel width so that the currents flowing through current mirror transistors 338 and 340 are approximately equal.

[0044] exist Figure 3B In the example of , the supply current circuit 326 is implemented with a resistor 328 (also referred to as a current limiting resistor or clamping resistor). In this example, the resistance of the resistor 328 helps control the current flow from the supply rail. For example, a lower resistance can be used for the resistor 328 to increase the current flow, and a higher resistance can be used for the resistor 328 to reduce the current flow. However, it should be understood that the supply current circuit 326 is not limited to this example. For example, in other specific implementations, the supply current circuit 326 may include a current source transistor, where the current flow is controlled by the gate bias voltage of the current source transistor.

[0045] To support high data rates, a low resistance may be used for resistor 328. The low resistance increases the current flow to transconductance amplifier 310, which increases the bandwidth of transconductance amplifier 310. However, due to the higher current, this also increases the power consumption of transconductance amplifier 310. For situations where transconductance amplifier 310 supports both high and low data rates, the increased current may result in reduced power efficiency at the low data rate (which may not require the increased bandwidth).

[0046] Another type of amplifier that can be used is the current mirror amplifier. In this regard, Figure 4AAn example of a current mirror amplifier 410 according to certain aspects is shown. The current mirror amplifier 410 may also be referred to as a current mirror OTA or another term. As discussed further below, the current mirror amplifier 410 uses one or more current mirrors to provide current multiplication (ie, current gain) in the amplifier.

[0047] The current mirror amplifier 410 includes a first input transistor 420, a second input transistor 425, a supply current circuit 426, a first current mirror 430, a second current mirror 440, and a third current mirror 450. Figure 4A In the example of , each of the input transistors 420 and 425 is implemented with a respective p-type transistor (eg, a p-type field effect transistor (PFET), also referred to as a p-type metal oxide semiconductor (PMOS) transistor).

[0048] The first current mirror 430 has an input terminal 432 and an output terminal 434. The first current mirror 430 is configured to mirror the current flowing through the input terminal 432 at the output terminal 434, wherein the current at the output terminal 434 is equal to the current at the input terminal 432 multiplied by a current mirror factor of the first current mirror 430. Thus, in this example, the first current mirror 430 provides current multiplication based on the current mirror factor of the first current mirror 430.

[0049] The second current mirror 440 has an input terminal 442 and an output terminal 444. The second current mirror 440 is configured to mirror the current flowing through the input terminal 442 at the output terminal 444, wherein the current at the output terminal 444 is equal to the current at the input terminal 442 multiplied by the current mirror factor of the second current mirror 440. Thus, in this example, the second current mirror 440 provides current multiplication based on the current mirror factor of the second current mirror 440. In some aspects, the current mirror factor of the second current mirror 440 may be approximately equal to the current mirror factor of the first current mirror 430.

[0050] The third current mirror 450 has an input terminal 452 and an output terminal 454. The third current mirror 450 is configured to mirror the current flowing through the input terminal 452 at the output terminal 454. In some aspects, the current at the output terminal 454 can be approximately equal to the current at the input terminal 452.

[0051] The supply current circuit 426 is configured to control the flow of current from the supply rail. As discussed further below, the supply current circuit 426 may be implemented with a current limiting resistor (also referred to as a clamping resistor), a current source transistor, or the like.

[0052] exist Figure 4AIn the example of FIG. 4 , the gate of the first input transistor 420 is coupled to the first input terminal 412 of the current mirror amplifier 410, and the drain of the first input transistor 420 is coupled to the input terminal 432 of the first current mirror 430. The gate of the second input transistor 425 is coupled to the second input terminal 414 of the current mirror amplifier 410, and the drain of the second input transistor 425 is coupled to the input terminal 442 of the second current mirror 440. The supply current circuit 426 is coupled between the supply rail and the sources of the input transistors 420 and 425. The output terminal 434 of the first current mirror 430 is coupled to the input terminal 452 of the third current mirror 450, the output terminal 454 of the third current mirror 450 is coupled to the output terminal 416 of the current mirror amplifier 410, and the output terminal 444 of the second current mirror 440 is coupled to the output terminal 416 of the current mirror amplifier 410.

[0053] In operation, the current mirror amplifier 410 receives a differential input signal (e.g., a differential voltage) including a first input signal inp at a first input terminal 412 and a second input signal inn at a second input terminal 414. In some implementations, the input terminals may also be pseudo-differential. The first input transistor 420 generates a first current at the drain of the first input transistor 420 based on the first input signal inp, and the second input transistor 425 generates a second current at the drain of the second input transistor 425 based on the second input signal inn. The first current mirror 430 multiplies the first current by a current mirror factor of the first current mirror 430 and provides the multiplied first current to the third current mirror 450. The third current mirror 450 mirrors the multiplied first current at an output terminal 454 of the third current mirror 450, which is coupled to the output terminal 416 of the current mirror amplifier 410. The second current mirror 440 multiplies the second current by a current mirror factor of the second current mirror 440 and provides the multiplied second current to the output terminal 416 of the current mirror amplifier 410. Therefore, the multiplied first current and the multiplied second current are provided to the output terminal 416 of the current mirror amplifier 410 and are thus combined at the output terminal 416 of the current mirror amplifier 410. In this example, the voltage gain of the current mirror amplifier 410 may be approximately equal to the transconductance of the current mirror amplifier 410 and the load resistance at the output terminal 416.

[0054] Figure 4BAn exemplary implementation of a first current mirror 430, a second current mirror 440, a third current mirror 450, and a supply current circuit 426 according to certain aspects is shown. In this example, the first current mirror 430 includes a first current mirror transistor 436 and a second current mirror transistor 438, wherein each of the current mirror transistors 436 and 438 is implemented with a respective n-type transistor. The drain of the first current mirror transistor 436 is coupled to the input terminal 432, the source of the first current mirror transistor 436 is coupled to a low rail (e.g., ground), and the gate of the first current mirror transistor 436 is coupled to the drain of the first current mirror transistor 436. The drain of the second current mirror transistor 438 is coupled to the output terminal 434, the source of the second current mirror transistor 438 is coupled to a low rail (e.g., ground), and the gate of the second current mirror transistor 438 is coupled to the gate of the first current mirror transistor 436. In one example, the current mirror factor of the first current mirror 430 may be based on a ratio of a channel width of the second current mirror transistor 438 to a channel width of the first current mirror transistor 436 .

[0055] In this example, the second current mirror 440 includes a third current mirror transistor 446 and a fourth current mirror transistor 448, wherein each of the current mirror transistors 446 and 448 is implemented with a respective n-type transistor. The drain of the third current mirror transistor 446 is coupled to the input terminal 442, the source of the third current mirror transistor 446 is coupled to a low rail (e.g., ground), and the gate of the third current mirror transistor 446 is coupled to the drain of the third current mirror transistor 446. The drain of the fourth current mirror transistor 448 is coupled to the output terminal 444, the source of the fourth current mirror transistor 448 is coupled to a low rail (e.g., ground), and the gate of the fourth current mirror transistor 448 is coupled to the gate of the third current mirror transistor 446. In one example, the current mirror factor of the second current mirror 440 may be based on a ratio of a channel width of the fourth current mirror transistor 448 to a channel width of the third current mirror transistor 446.

[0056] In this example, the third current mirror 450 includes a fifth current mirror transistor 456 and a sixth current mirror transistor 458, wherein each of the current mirror transistors 456 and 458 is implemented with a respective p-type transistor. The source of the fifth current mirror transistor 456 is coupled to the supply rail, the drain of the fifth current mirror transistor 456 is coupled to the input terminal 452, and the gate of the fifth current mirror transistor 456 is coupled to the drain of the fifth current mirror transistor 456. The source of the sixth current mirror transistor 458 is coupled to the supply rail, the drain of the sixth current mirror transistor 458 is coupled at the output terminal 454, and the gate of the sixth current mirror transistor 458 is coupled to the gate of the fifth current mirror transistor 456. In one example, the current mirror transistors 456 and 458 may have approximately the same channel width so that the currents flowing through the current mirror transistors 456 and 458 are approximately equal.

[0057] exist Figure 4B In the example of FIG. 4 , the supply current circuit 426 is implemented with a resistor 428 (also referred to as a current limiting resistor or clamping resistor) coupled between the source of the first input transistor 420 and the second input transistor 425 and the supply rail. In this example, the resistance of the resistor 428 helps control the flow of current from the supply rail. However, it should be understood that the supply current circuit 426 is not limited to this example. For example, in other specific implementations, the supply current circuit 426 may include a current source transistor, where the current flow is controlled by the gate bias voltage of the current source transistor.

[0058] To support high data rates, a high current mirror factor may be used for each of the first current mirror 430 and the second current mirror 440. For a given input, the high current mirror factor increases the current at the output terminals 434 and 444 of the first current mirror 430 and the second current mirror 440, which increases the transconductance and thus the bandwidth of the current mirror amplifier 410. However, due to the higher current, this also increases the power consumption of the current mirror amplifier 410. For situations where the current mirror amplifier 410 supports both high and low data rates, the increased current may result in reduced power efficiency at low data rates (which may not require the increased bandwidth).

[0059] Various aspects of the present disclosure provide a hybrid amplifier including elements of a transconductance amplifier (e.g., transconductance amplifier 310) and elements of a current mirror amplifier (e.g., current mirror amplifier 410). For example, a hybrid amplifier according to certain aspects may include elements of a transconductance amplifier having n-type input transistors and elements of a current mirror amplifier having p-type input transistors. Various features of hybrid amplifiers according to various aspects of the present disclosure are discussed in further detail below.

[0060] Figure 5An example of a hybrid amplifier 510 according to certain aspects of the present disclosure is shown. The hybrid amplifier 510 has a first input terminal 512, a second input terminal 514, and an output terminal 516. The hybrid amplifier 510 can be used, for example, to implement Figure 2 In this example, the first input terminal 512 corresponds to the first input terminal 252, the second input terminal 514 corresponds to the second input terminal 254, and the output terminal 516 corresponds to the output terminal 256. However, it should be understood that the hybrid amplifier 510 is not limited to this example.

[0061] exist Figure 5 In the example, the hybrid amplifier 510 includes Figure 4A The exemplary current mirror amplifier 410 shown in FIG. 1 is a first input terminal 412 ( Figure 4A ) is coupled to a first input terminal 512 of the mixing amplifier 510, and a second input terminal 414 ( Figure 4A ) is coupled to the second input terminal 514 of the mixing amplifier 510, and the output terminal 416 ( Figure 4A ) is coupled to the output terminal 516 of the mixing amplifier 510. Figure 4A The current mirror amplifier 410 is described, and thus, for the sake of brevity, a detailed description of the current mirror amplifier 410 is not repeated here. In the following discussion, the supply current circuit 426 is referred to as the first supply current circuit 426 .

[0062] The hybrid amplifier 510 also includes elements of a transconductance amplifier (eg, transconductance amplifier 310), including a third input transistor 520, a fourth input transistor 525, and a second supply current circuit 526. For example, the third input transistor 520 may correspond to Figure 3A The first input transistor 320 shown, the fourth input transistor 525 may correspond to Figure 3A The second input transistor 325 shown in FIG. 1 and the second supply current circuit 526 may correspond to Figure 3A The supply current circuit 326 is shown. In some aspects, the third current mirror 450 of the current mirror amplifier 410 can also serve as Figure 3A The current mirror 330 of the transconductance amplifier 310 is shown.

[0063] In this example, each of the third input transistor 520 and the fourth input transistor 525 is implemented with a corresponding n-type transistor. Thus, in this example, the first input transistor 420 and the second input transistor 425 are p-type transistors, while the third input transistor 520 and the fourth input transistor 525 are n-type transistors. As discussed further below, using both p-type input transistors and n-type input transistors helps to extend the input voltage range of the hybrid amplifier 510 compared to amplifiers that only use input transistors of the same transistor channel type.

[0064] exist Figure 5 In the example of , the gate of the third input transistor 520 is coupled to the first input terminal 512 of the mixing amplifier 510, and the drain of the third input transistor 520 is coupled to the input terminal 452 of the third current mirror 450. The gate of the fourth input transistor 525 is coupled to the second input terminal 514 of the mixing amplifier 510, and the drain of the fourth input transistor 525 is coupled to the output terminal 516 of the mixing amplifier 510. The supply current circuit 526 is coupled between the sources of the third input transistor 520 and the fourth input transistor 525 and a low rail (e.g., a ground rail). The supply current circuit 526 can be implemented with a current limiting resistor, a current source transistor, etc.

[0065] In operation, the mixing amplifier 510 receives a differential input signal (e.g., a differential voltage) including a first input signal inp at a first input terminal 512 and a second input signal inn at a second input terminal 514. In some implementations, the input terminals may also be pseudo-differential. The first input transistor 420 generates a first current at the drain of the first input transistor 420 based on the first input signal inp, the second input transistor 425 generates a second current at the drain of the second input transistor 425 based on the second input signal inn, the third input transistor 520 generates a third current at the drain of the third input transistor 520 based on the first input signal inp, and the fourth input transistor 525 generates a fourth current at the drain of the fourth input transistor 525 based on the second input signal inn.

[0066] The first current mirror 430 multiplies the first current from the first input transistor 420 by the current mirror factor of the first current mirror 430 and provides the multiplied first current to the input terminal 452 of the third current mirror 450. The third current from the third input transistor 520 is also provided to the input terminal 452 of the third current mirror 450 (which is coupled to the third input transistor 520). Therefore, the input terminal 452 of the third current mirror 450 receives the combination of the multiplied first current and the third current. The third current mirror 450 mirrors the combination of the multiplied first current and the third current at the output terminal 454 of the third current mirror 450, which is coupled to the output terminal 516 of the mixing amplifier 510. Therefore, the output terminal 454 of the third current mirror 450 provides the combination of the multiplied first current and the third current to the output terminal 516 of the mixing amplifier 510.

[0067] The second current mirror 440 multiplies the second current from the second input transistor 425 by the current mirror factor of the second current mirror 440 and provides the multiplied second current to the output terminal 516 of the mixing amplifier 510. The fourth current from the fourth input transistor 525 is also provided to the output terminal 516 of the mixing amplifier 510. Therefore, the output terminal 516 receives a combination of the multiplied second current and the fourth current.

[0068] Thus, the multiplied first current, the multiplied second current, the third current, and the fourth current combine at the output 516 of the mixing amplifier 510. In this example, the voltage gain of the mixing amplifier 510 may be approximately equal to the transconductance of the mixing amplifier 510 and the load resistance at the output 516.

[0069] As discussed above, using different transistor channel types for the first input transistor 420 and the second input transistor 425 and the third input transistor 520 and the fourth input transistor 525 helps to extend the input voltage range of the hybrid amplifier 510. Figure 5 In the example shown, the first input transistor 420 and the second input transistor 425 (which are p-type in this example) can mainly drive the mixing amplifier 510 at a low input voltage (e.g., a voltage lower than the threshold voltage of the third input transistor 520 and the fourth input transistor 525), and the third input transistor 520 and the fourth input transistor 525 (which are n-type in this example) can mainly drive the mixing amplifier 510 at a high input voltage (e.g., a voltage higher than the supply voltage Vdd minus the threshold voltage of the first input transistor 420 and the second input transistor 425). Although in Figure 5In the example shown, the first input transistor 420 and the second input transistor 425 are p-type and the third input transistor 520 and the fourth input transistor 525 are n-type, but it should be understood that the present disclosure is not limited to this example. For example, in some specific implementations, the first input transistor 420 and the second input transistor 425 may be n-type, and the third input transistor 520 and the fourth input transistor 525 may be p-type. Generally speaking, the first input transistor 420 and the second input transistor 425 have a different transistor channel type than the third input transistor 520 and the fourth input transistor 525.

[0070] Figure 6 An exemplary implementation of the first current mirror 430, the second current mirror 440, the third current mirror 450, the first supply current circuit 426, and the second supply current circuit 526 according to certain aspects is shown. In this example, the first current mirror 430 includes the first current mirror transistor 436 and the second current mirror transistor 438 discussed above, the second current mirror 440 includes the third current mirror transistor 446 and the fourth current mirror transistor 448 discussed above, and the third current mirror 450 includes the fifth current mirror transistor 456 and the sixth current mirror transistor 458 discussed above. Since the above reference according to certain aspects Figure 4B Current mirror transistors 436 , 438 , 446 , 448 , 456 , and 458 are described, and thus a detailed description of current mirror transistors 436 , 438 , 446 , 448 , 456 , and 458 will not be repeated here for the sake of brevity.

[0071] In this example, the first supply current circuit 426 includes the above reference Figure 4B In the following discussion, resistor 428 is referred to as first resistor 428. In this example, second supply current circuit 526 includes second resistor 610 (also referred to as current limiting resistor or clamping resistor) coupled between the sources of third input transistor 520 and fourth input transistor 520 and a low rail (e.g., ground rail).

[0072] exist Figure 6 In the example shown in , hybrid amplifier 510 includes a stack of two transistors between the supply rail and the low rail. In contrast, a cascode amplifier (e.g., a folded cascode amplifier) ​​may have a stack of four or more transistors between the rails. The smaller stack of transistors between the rails in hybrid amplifier 510 allows hybrid amplifier 510 to operate at a lower supply voltage than a cascode amplifier.

[0073] The exemplary hybrid amplifier 510 may allow for a large voltage swing at the output 516 (eg, approximately a rail-to-rail output voltage swing assuming a small voltage drop across transistors 458 and 448). Figure 6 In the example of FIG. 5 , the IR voltage drop across the first resistor 428 has little effect on the output voltage swing of the hybrid amplifier 510 . This is because the first resistor 428 is not located between the supply voltage and the output terminal 516 of the hybrid amplifier 510 .

[0074] In some aspects, the first resistor 428 may be implemented with a corresponding variable resistor having an adjustable (ie, programmable) resistance. In addition, the second resistor 610 may be implemented with a corresponding variable resistor having an adjustable (ie, programmable) resistance. Fig. 10A and Fig. 10B Exemplary implementations of variable resistors are discussed further below. In certain aspects, the resistance of the first resistor 428 and the resistance of the second resistor 610 are controlled by a control circuit 650 .

[0075] In one example, the hybrid amplifier 510 may support a plurality of data rates including a first data rate and a second data rate, wherein the first data rate (e.g., a low data rate) is lower than the second data rate (e.g., a high data rate). Figure 2 In the example of amplifier 250 shown, transmitter 210 can transmit data signals at any one of a plurality of data rates (e.g., based on the use case). In this example, control circuit 650 can set (i.e., program) the resistance of first resistor 428 and the resistance of second resistor 610 based on the current data rate of the signal being received by hybrid amplifier 510.

[0076] For example, the control circuit 650 may set the resistance of the first resistor 428 to a first resistance value for a first data rate (e.g., a low data rate) and to a second resistance value for a second data rate (e.g., a high data rate), wherein the second resistance value is lower than the first resistance value. Thus, in this example, the control circuit 650 sets the resistance of the first resistor 428 to be lower for the second data rate (e.g., a high data rate) than for the first data rate (e.g., a low data rate). The lower resistance at the second data rate (e.g., a high data rate) increases the current from the power rail, which helps increase the bandwidth of the hybrid amplifier 510, thereby allowing the hybrid amplifier 510 to operate at a higher data rate. In this example, the control circuit 650 sets the resistance of the first resistor 428 to be higher for the first data rate (e.g., a low data rate) than for the second data rate (e.g., a high data rate). The higher resistance at the first data rate (e.g., a low data rate) reduces the current from the power rail, which helps reduce power consumption at the first data rate. The current (and therefore the power) can be reduced for the first data rate because the hybrid amplifier 510 can operate with a smaller bandwidth at the lower data rate. Thus, by setting (i.e., programming) the resistance of the first resistor 428 based on the data rate, the control circuit 650 facilitates the hybrid amplifier 510 to operate at a high data rate while reducing the power at a low data rate to improve the power efficiency at the low data rate.

[0077] In this example, the control circuit 650 may also set the resistance of the second resistor 610 to a third resistance value for a first data rate (e.g., a low data rate), and set the resistance of the second resistor 610 to a second resistance value for a second data rate (e.g., a high data rate), wherein the fourth resistance value is lower than the third resistance value. Therefore, in this example, the control circuit 650 sets the resistance of the second resistor 610 to be lower for the second data rate (e.g., a high data rate) compared to the first data rate (e.g., a low data rate). As discussed above, this helps the hybrid amplifier 510 operate at a high data rate while reducing the power of the low data rate to improve power efficiency at the low data rate. The third resistance value may be the same or different from the first resistance value, and the fourth resistance value may be the same or different from the second resistance value.

[0078] In some aspects, the first current mirror 430 may have an adjustable (i.e., programmable) current mirror factor, and the second current mirror 440 may have an adjustable (i.e., programmable) current mirror factor. In the discussion below, the current mirror factor of the first current mirror 430 is referred to as the first current mirror factor, and the current mirror factor of the second current mirror 440 is referred to as the second current mirror factor.

[0079] For examples where the hybrid amplifier 510 supports multiple data rates including a first data rate (e.g., a low data rate) and a second data rate (e.g., a high data rate), the control circuit 650 may set the first mirror factor based on the current data rate of the signal being received by the hybrid amplifier 510. For example, the control circuit 650 may set the first current mirror factor to a first factor value for the first data rate (e.g., the low data rate) and set the first current mirror factor to a second factor value for the second data rate (e.g., the high data rate), wherein the second factor value is greater than the first factor value.

[0080] Thus, in this example, the control circuit 650 sets the first current mirror factor to a higher factor value for the second data rate (e.g., high data rate) compared to the first data rate (e.g., low data rate). The higher factor value for the second data rate (e.g., high data rate) increases the current multiplication of the first current mirror 430. The increased current multiplication (i.e., current gain) increases the current at the output terminal 434 of the first current mirror 430, which helps increase the bandwidth of the hybrid amplifier 510, thereby allowing the hybrid amplifier 510 to operate at a higher data rate (i.e., frequency). The lower factor value for the first data rate (e.g., low data rate) reduces the current multiplication of the first current mirror 430, which helps reduce power consumption at the first data rate. Thus, by setting (i.e., programming) the first current mirror factor based on the data rate, the control circuit 650 helps the hybrid amplifier 510 operate at a high data rate while reducing the power at the low data rate to improve power efficiency at the low data rate.

[0081] In this example, the control circuit 650 may also set the second current mirror factor to a third factor value for a first data rate (e.g., a low data rate), and set the second current mirror factor to a fourth factor value for a second data rate (e.g., a high data rate), wherein the fourth factor value is greater than the third factor value. Thus, in this example, the control circuit 650 sets the second current mirror factor to a higher value for the second data rate (e.g., a high data rate) than for the first data rate (e.g., a low data rate). As discussed above, this helps the hybrid amplifier 510 operate at a high data rate while reducing power at a low data rate to improve power efficiency at the low data rate. The third factor value may be the same or different from the first factor value, and the fourth factor value may be the same or different from the second factor value.

[0082] Figure 7An exemplary implementation of a first current mirror 430 and a second current mirror 440 having a programmable current mirror factor according to certain aspects is shown. In this example, the first current mirror 430 also includes a first current mirror switch 720 and a seventh current mirror transistor 710 coupled in series between the output terminal 434 and the low rail. In this example, the control circuit 650 can set the first current mirror factor to a first factor value by opening (i.e., turning off) the first current mirror switch 720, and set the first current mirror factor to a second factor value by closing (i.e., turning on) the first current mirror switch 720. Turning on the first current mirror switch 720 couples the seventh current mirror transistor 710 in parallel with the second current mirror transistor 438, which increases the first current mirror factor.

[0083] exist Figure 7 In the example of , the second current mirror 440 also includes a second current mirror switch 725 and an eighth current mirror transistor 750 coupled in series between the output terminal 444 and the low rail. In this example, the control circuit 650 can set the second current mirror factor to a third factor value by opening (i.e., turning off) the second current mirror switch 725, and set the second current mirror factor to a fourth factor value by closing (i.e., turning on) the second current mirror switch 725. Turning on the second current mirror switch 725 couples the eighth current mirror transistor 750 in parallel with the fourth current mirror transistor 448, which increases the second current mirror factor.

[0084] It should be understood that each of current mirrors 430 and 440 may include one or more additional switches (not shown) and one or more additional current mirror transistors (not shown) to allow control circuit 650 to selectively set the current mirror factor of each of current mirrors 430 and 440 to more than two factor values.

[0085] In some aspects, the hybrid amplifier 510 may be placed in a disabled mode (also referred to as an idle or standby mode) to save power when the hybrid amplifier 510 is not in use (e.g., the transmitter 210 is not transmitting to the receiver 240). In the disabled mode, it is desirable to reduce leakage current through the hybrid amplifier 510 to reduce power losses in the disabled mode (i.e., to reduce standby power). In this regard, the hybrid amplifier 510 may include a switch and / or other device for cutting off leakage paths in the hybrid amplifier 510 in the disabled mode to reduce power losses due to current leakage.

[0086] Fig. 8A and Figure 8B An example is shown in which the hybrid amplifier 510 includes a first switch 810 , a second switch 815 , a third switch 820 , a fourth switch 825 , a fifth switch 830 , and a sixth switch 835 . Fig. 8A810, 815, 820, 825, 830 and 835 are shown in the on / off state in the enabled mode (also referred to as the active mode), and Figure 8B The on / off states of switches 810, 815, 820, 825, 830, and 835 in the disabled mode are shown.

[0087] The first switch 810 is coupled between the drain of the second current mirror transistor 438 and the output terminal 434, and the second switch 815 is coupled between the drain of the fourth current mirror transistor 448 and the output terminal 444. In the enable mode, the control circuit 650 closes (i.e., turns on) the first switch 810 and the second switch 815, as shown in FIG. Fig. 8A In the disable mode, the control circuit 650 disconnects (ie, turns off) the first switch 810 and the second switch 815. Disconnecting the first switch 810 and the second switch 815 cuts off the leakage path through the first current mirror 430 and the second current mirror 440.

[0088] The third switch 820 is coupled between the gate of the fifth current mirror transistor 456 and the drain of the fifth current mirror transistor 456. In the enable mode, the control circuit 650 closes (ie, turns on) the third switch 820. Fig. 8A In the disabled mode, the control circuit 650 disconnects (ie, turns off) the third switch 820. Disconnecting the third switch 820 cuts off the feedback path between the gate and the drain of the fifth current mirror transistor 456.

[0089] The fourth switch 825 is coupled between the power supply rail and the gates of the fifth current mirror transistor 456 and the sixth current mirror transistor 458. In the enabled mode, the control circuit 650 opens (i.e., turns off) the fourth switch 825. In the disabled mode, the control circuit 650 closes (i.e., turns on) the fourth switch 825, which shorts the source and gate of the fifth current mirror transistor 456 and the source and gate of the sixth current mirror transistor 458. Therefore, the fifth current mirror transistor 456 and the sixth current mirror transistor 458 are turned off in the disabled mode, which helps to prevent leakage current from flowing through the fifth current mirror transistor 456 and the sixth current mirror transistor 458. In the disabled mode, the third switch 820 is opened (i.e., turned off), which blocks the leakage current between the gate and the drain of the fifth current mirror transistor 456.

[0090] The fifth switch 830 is coupled between the first resistor 428 and the supply rail, and the sixth switch 835 is coupled between the second resistor 610 and the low rail (e.g., the ground rail). In the enable mode, the control circuit 650 closes (i.e., turns on) the fifth switch 830 and the sixth switch 835, as shown in FIG. Fig. 8AIn the disabled mode, the control circuit 650 opens (ie, turns off) the fifth switch 830 and the sixth switch 835. This cuts off the leakage current path through the first resistor 428 and the second resistor 610 in the disabled mode.

[0091] In some methods, a pull-down switch is coupled between the output of the amplifier and a low rail (e.g., a ground rail), wherein the pull-down switch is closed (i.e., turned on) in the disable mode to pull the output of the amplifier low in the disable mode. However, the pull-down switch may create a leakage current path from the output to the low rail (e.g., the ground rail) in the disable mode, which increases the leakage current in the disable mode. Fig. 8A and Figure 8B In the example of , the pull-down switch is replaced with a NAND gate 850, which effectively cuts off the leakage path from the output terminal 516 to the low rail.

[0092] The NAND gate 850 has a first input 852, a second input 854, and an output 856. The first input 852 of the NAND gate 850 is coupled to the output 516 of the mixing amplifier 510, and the output 856 of the NAND gate 850 is coupled to the input of the inverter 860. In this example, the control circuit 650 selectively enables / disables the NAND gate 850 by controlling the logic state at the second input 854 of the NAND gate 850.

[0093] In the enable mode, the control circuit 650 outputs a logic one to the second input terminal 854 of the NAND gate 850. Fig. 8A This causes NAND gate 850 to act as an inverter coupled to output 516 of hybrid amplifier 510. In the enabled mode, inverter 860 undoes the inversion of NAND gate 850 so that the output of inverter 860 has the same polarity as output 516.

[0094] In the disable mode, the control circuit 650 outputs a logic zero to the second input terminal 854 of the NAND gate 850. Figure 8B This causes NAND gate 850 to output a logic one at output 856 of NAND gate 850 in the disable mode, which causes inverter 860 to output a logic zero in the disable mode.

[0095] In the enabled mode, the control circuit 650 may close or open the current mirror switches 720 and 725, depending on, for example, whether the hybrid amplifier 510 is operating at the first data rate or the second data rate, as discussed above. In the disabled mode, the control circuit 650 opens the current mirror switches 720 and 725 to cut off the current leakage path through the current mirrors 430 and 440.

[0096] In this example, the first current mirror 430 also includes a first current mirror switch 720 and a seventh current mirror transistor 710 coupled in series between the output terminal 434 and the low rail. In this example, the control circuit 650 can set the first current mirror factor to a first factor value by opening (i.e., turning off) the first current mirror switch 720, and set the first current mirror factor to a second factor value by closing (i.e., turning on) the first current mirror switch 720. Turning on the first current mirror switch 720 couples the seventh current mirror transistor 710 to the output terminal 434.

[0097] It should be understood that the present disclosure is not limited to Fig. 8A and Figure 8B 810 and the exemplary positions of the second switch 815 are shown. In this regard, Figure 8C and Fig.8D An example is shown in which a first switch 810 is coupled between the second current mirror transistor 438 and the low rail and a second switch 815 is coupled between the fourth current mirror transistor 448 and the low rail. In general, the first switch 810 and the second current mirror transistor 438 may be coupled in series between the output terminal 434 and the low rail, and the second switch 815 and the fourth current mirror transistor 448 may be coupled in series between the output terminal 444 and the low rail. Figure 8C The on / off state of switches 810 and 815 in an enabled mode is shown, and Fig.8D The on / off status of switches 810 and 815 are shown in a disabled mode.

[0098] Fig. 8A and Figure 8B An example is also shown in which a first current mirror switch 720 is coupled between the seventh current mirror transistor 710 and the low rail and a second current mirror switch 725 is coupled between the eighth current mirror transistor 750 and the low rail. In general, the first current mirror switch 720 and the seventh current mirror transistor 710 may be coupled in series between the output terminal 434 and the low rail, and the second current mirror switch 725 and the eighth current mirror transistor 750 may be coupled in series between the output terminal 444 and the low rail.

[0099] Fig. 9 810, second switch 815, third switch 820, fourth switch 825, fifth switch 830, and sixth switch 835 are shown in accordance with certain aspects. In this example, first switch 810 includes first transistor 910 and second switch 815 includes second transistor 915. Fig. 9In the example shown, each of the first transistor 910 and the second transistor 915 is an n-type transistor. In this example, the control circuit 650 inputs an enable signal ("En") to the gates of the first transistor 910 and the second transistor 915 to control the on / off state of the first transistor 910 and the second transistor 915. In the enable mode, the enable signal is high (i.e., logic one), which causes the first transistor 910 and the second transistor 915 to be turned on in the enable mode. In the disable mode, the enable signal is low (i.e., logic zero), which causes the first transistor 910 and the second transistor 915 to be turned off in the disable mode.

[0100] exist Fig. 9 In the example of , the third switch 820 is implemented by a transmission gate including a third transistor 920 and a fourth transistor 925. Fig. 9 In the example of , the third transistor 920 is an n-type transistor and the fourth transistor 925 is a p-type transistor. In this example, the control circuit 650 inputs an enable signal ("En") to the gate of the third transistor 920 and inputs the inversion of the enable signal ("Enb") to the gate of the fourth transistor 925. In the enable mode, the enable signal is high (i.e., logic one) and the inversion of the enable signal is low (i.e., logic zero), which causes the third transistor 920 and the fourth transistor 925 to be turned on in the enable mode. In the disable mode, the enable signal is low (i.e., logic zero) and the inversion of the enable signal is high (i.e., logic one), which causes the third transistor 920 and the fourth transistor 925 to be turned off in the disable mode.

[0101] exist Fig. 9 In the example of , the fourth switch 825 includes a fifth transistor 930 implemented with a p-type transistor. In this example, the control circuit 650 inputs an enable signal ("En") to the gate of the fifth transistor 930. In the enable mode, the enable signal is high, which turns off the fifth transistor 930 in the enable mode. In the disable mode, the enable signal is low, which turns on the fifth transistor 930 in the disable mode.

[0102] exist Fig. 9In the example of , the fifth switch 830 includes a sixth transistor 935 and the sixth switch 835 includes a seventh transistor 940. In this example, the sixth transistor 935 is a p-type transistor and the seventh transistor 940 is an n-type transistor. In this example, the control circuit 650 inputs the inversion of the enable signal ("Enb") to the gate of the sixth transistor 935 and inputs the enable signal ("En") to the gate of the seventh transistor 940. In the enable mode, the enable signal is high (i.e., logic one) and the inversion of the enable signal is low (i.e., logic zero), which causes the sixth transistor 935 and the seventh transistor 940 to be turned on in the enable mode. In the disable mode, the enable signal is low (i.e., logic zero) and the inversion of the enable signal is high (i.e., logic one), which causes the sixth transistor 935 and the seventh transistor 940 to be turned off in the disable mode.

[0103] exist Fig. 9 In the example of FIG. 6 , the control circuit 650 inputs an enable signal (“En”) to the second input terminal 854 of the NAND gate 850. In the enable mode, the enable signal is high, which causes the NAND gate 850 to act as an inverter in the enable mode. In the disable mode, the enable signal is low, which causes the NAND gate 850 to output one at the output terminal 856 of the NAND gate 850 in the disable mode.

[0104] exist Fig. 9 In the example of FIG. 1 , the first current mirror switch 720 includes an eighth transistor 950, and the second current mirror switch 725 includes a ninth transistor 955. In this example, each of the eighth transistor 950 and the ninth transistor 955 is a corresponding n-type transistor. The control circuit 650 may input a control signal (“cntrl”) to the gates of the eighth transistor 950 and the ninth transistor 955. To set the first current mirror factor to the first factor value and the second current mirror factor to the third factor value, the control circuit 650 sets the control signal to low to turn off the current mirror switches 720 and 725. As discussed above, the first factor value and the third factor value may be the same or different. To set the first current mirror factor to the second factor value and the second current mirror factor to the fourth factor value, the control circuit 620 sets the control signal to high to turn on the current mirror switches 720 and 725, which increases the first current mirror factor and the second current mirror factor. As discussed above, the second factor value and the fourth factor value may be the same or different. In the disable mode, the control circuit 650 may set the control signal to low to turn off the current mirror switches 720 and 725 in the disable mode.

[0105] Fig. 10AAn exemplary implementation of the first resistor 428 according to certain aspects is shown. In this example, the first resistor 428 includes resistors 1010, 1015, and 1020 coupled in series, a first transistor 1025, and a second transistor 1030. In this example, each of the first transistor 1025 and the second transistor 1030 is implemented with a corresponding p-type transistor. However, it should be understood that the present disclosure is not limited to this example.

[0106] The resistor 1010 is coupled between the source and drain of the first transistor 1025, and the resistors 1010 and 1015 are coupled in series between the drain and source of the second transistor 1030. In this example, the control circuit 650 can adjust (i.e., program) the resistance of the first resistor 428 by controlling the on / off state of the first transistor 1025 and the second transistor 1030. For example, when the control circuit 650 turns off the first transistor 1025 and the second transistor 1030, the resistance of the first resistor 428 is approximately equal to the sum of the resistances of the resistors 1010, 1015, and 1020. When the control circuit 650 turns on the first transistor 1025 and turns off the second transistor 1030, the resistance of the first resistor 428 is approximately equal to the sum of the resistances of the resistors 1015 and 1020. When the control circuit 650 turns on the second transistor 1030, the resistance of the first resistor 428 is approximately equal to the resistance of the resistor 1020.

[0107] Fig. 10B An exemplary implementation of the second resistor 610 according to certain aspects is shown. In this example, the second resistor 610 includes resistors 1050, 1055, and 1060 coupled in series, a first transistor 1065, and a second transistor 1070. In this example, each of the first transistor 1065 and the second transistor 1070 is implemented with a corresponding n-type transistor. However, it should be understood that the present disclosure is not limited to this example.

[0108] The resistor 1060 is coupled between the drain and source of the first transistor 1065, and the resistors 1060 and 1055 are coupled in series between the drain and source of the second transistor 1070. In this example, the control circuit 650 can adjust (i.e., program) the resistance of the second resistor 610 by controlling the on / off state of the first transistor 1065 and the second transistor 1070. For example, when the control circuit 650 turns off the first transistor 1065 and the second transistor 1070, the resistance of the second resistor 610 is approximately equal to the sum of the resistances of the resistors 1050, 1055, and 1060. When the control circuit 650 turns on the first transistor 1065 and turns off the second transistor 1070, the resistance of the second resistor 610 is approximately equal to the sum of the resistances of the resistors 1050 and 1055. When the control circuit 650 turns on the second transistor 1070, the resistance of the second resistor 610 is approximately equal to the resistance of the resistor 1050.

[0109] It should be understood that the first resistor 428 and the second resistor 610 are not limited to Fig. 10A and Fig. 10B In the example shown, the first resistor 428 and the second resistor 610 may be implemented with various types of variable resistors.

[0110] Fig.11 An exemplary implementation of a NAND gate 850 according to certain aspects is shown. In this example, the NAND gate 850 includes a first p-type transistor 1110 and a second p-type transistor 1120 coupled in parallel between a supply rail and an output terminal 856. The NAND gate 850 also includes a first n-type transistor 1130 and a second n-type transistor 1140 coupled in series between the output terminal 856 and a low rail (e.g., a ground rail). In this example, a first input terminal 852 is coupled to a gate of the first p-type transistor 1110 and a gate of the first n-type transistor 1130, and a second input terminal 854 is coupled to a gate of the second p-type transistor 1120 and a gate of the second n-type transistor 1140.

[0111] exist Fig. 8A , Figure 8B and Fig. 9 In the example shown, the first input terminal 852 is coupled to the output terminal 516 of the mixing amplifier 510. Fig.11 In the example in FIG. 8 , the first input terminal 852 is coupled to the gates of the first p-type transistor 1110 and the first n-type transistor 1130 , which helps prevent leakage current from the output terminal 516 of the hybrid amplifier 510 to the low rail via the NAND gate 850 .

[0112] Fig.12A method 1200 for amplifying a signal is illustrated. The signal may be a differential signal, a pseudo differential signal, or another type of signal. The method 1200 may be performed by the mixing amplifier 510.

[0113] At block 1210, a first input transistor and a second input transistor are driven with a signal. For example, the first input transistor may correspond to the first input transistor 420, and the second input transistor may correspond to the second input transistor 425. For examples where the signal is a differential signal including a first signal and a second signal, the first signal may be input to a gate of the first input transistor and the second signal may be input to a gate of the second input transistor.

[0114] At block 1220, the first current from the first input transistor is multiplied using a first current mirror to obtain a multiplied first current. For example, the first current mirror may correspond to first current mirror 430. In this example, the first current mirror may multiply the first current by a current mirror factor of the first current mirror.

[0115] At block 1230, the second current from the second input transistor is multiplied using a second current mirror to obtain a multiplied second current. For example, the second current mirror may correspond to second current mirror 440. In this example, the second current mirror may multiply the second current by a current mirror factor of the second current mirror.

[0116] At block 1240, the third input transistor and the fourth input transistor are driven with a signal. For example, the third input transistor may correspond to the third input transistor 520, and the fourth input transistor may correspond to the fourth input transistor 525. For examples where the signal is a differential signal including a first signal and a second signal, the first signal may be input to the gate of the third input transistor and the second signal may be input to the gate of the fourth input transistor. In some aspects, the third input transistor and the fourth input transistor may be a different transistor type than the first input transistor and the second input transistor. For example, the first input transistor and the second input transistor may be p-type transistors, and the third input transistor and the fourth input transistor may be n-type transistors, or vice versa.

[0117] At block 1250, the third current from the third input transistor is combined with the multiplied first current to obtain a combination of the third current and the multiplied first current. For example, the third current and the multiplied first current may be combined at a node coupled to an output terminal of the first current mirror (e.g., output terminal 434) and a drain of the third input transistor.

[0118] At block 1260, the fourth current from the fourth input transistor is combined with the multiplied second current to obtain a combination of the fourth current and the multiplied second current. For example, the fourth current and the multiplied second current may be combined at a node coupled to an output terminal of the second current mirror (e.g., output terminal 444) and a drain of the fourth input transistor.

[0119] The method 1200 may also include directing the combination of the third current and the multiplied first current to an output terminal using a third current mirror. For example, the output terminal may correspond to the output terminal 516, and the third current mirror may correspond to the third current mirror 450. For example, the third current mirror may direct the combination of the third current and the multiplied first current to an output terminal (e.g., the output terminal 516) by mirroring the combination of the third current and the multiplied first current at an output terminal (e.g., the output terminal 454) of the third current mirror coupled to the output terminal (the output terminal 516). The method may also include providing a combination of the fourth current and the multiplied second current to the output terminal. For example, the output terminal may be coupled to a node that combines the fourth current with the multiplied second current.

[0120] It should be understood that any one or more of the transistors discussed above can be physically implemented on a chip using multiple transistors integrated on the chip. For example, a transistor can be implemented using multiple transistors, wherein the channels of the multiple transistors are coupled in series and / or in parallel, and the gates of the multiple transistors are coupled together.

[0121] Specific implementation examples are described in the following numbered clauses:

[0122] 1. A system, comprising:

[0123] An amplifier, wherein the amplifier comprises:

[0124] a first input transistor, wherein a gate of the first input transistor is coupled to a first input terminal of the amplifier;

[0125] a second input transistor, wherein a gate of the second input transistor is coupled to a second input terminal of the amplifier;

[0126] a first current mirror, wherein an input terminal of the first current mirror is coupled to a drain of the first input transistor;

[0127] a second current mirror, wherein an input terminal of the second current mirror is coupled to the drain of the second input transistor and an output terminal of the second current mirror is coupled to the output of the amplifier;

[0128] a third current mirror, wherein an input terminal of the third current mirror is coupled to an output terminal of the first current mirror, and an output terminal of the third current mirror is coupled to the output terminal of the amplifier;

[0129] a third input transistor, wherein a gate of the third input transistor is coupled to the first input of the amplifier and a drain of the third input transistor is coupled to the input terminal of the third current mirror; and

[0130] a fourth input transistor, wherein a gate of the fourth input transistor is coupled to the second input of the amplifier and a drain of the fourth input transistor is coupled to the output of the amplifier.

[0131] 2. A system according to clause 1, wherein:

[0132] The first input transistor comprises a first p-type transistor;

[0133] The second input transistor comprises a second p-type transistor;

[0134] The third input transistor comprises a first n-type transistor; and

[0135] The fourth input transistor includes a second n-type transistor.

[0136] 3. A system according to clause 1 or 2, wherein the amplifier further comprises a first resistor, wherein the first resistor is coupled between a first rail and a source of the first input transistor, and the first resistor is coupled between the first rail and a source of the second input transistor.

[0137] 4. The system of clause 3, wherein the first resistor comprises a variable resistor.

[0138] 5. The system of clause 4, further comprising a control circuit, wherein the control circuit is configured to:

[0139] setting the resistance of the first resistor to a first resistance value for a first data rate; and

[0140] The resistance of the first resistor is set to a second resistance value for a second data rate, wherein the second data rate is higher than the first data rate and the second resistance value is lower than the first resistance value.

[0141] 6. A system according to any of clauses 3 to 5, wherein the amplifier further comprises a second resistor, wherein the second resistor is coupled between the source of the third input transistor and the second rail, and the second resistor is coupled between the source of the fourth input transistor and the second rail.

[0142] 7. The system of clause 6, wherein the second rail has a lower potential than the first rail.

[0143] 8. A system according to clause 6 or 7, wherein:

[0144] The first resistor comprises a first variable resistor; and

[0145] The second resistor includes a second variable resistor.

[0146] 9. A system according to any one of clauses 1 to 8, wherein the first current mirror comprises:

[0147] a first current mirror transistor, wherein a drain of the first current mirror transistor is coupled to the input terminal of the first current mirror, a gate of the first current mirror transistor is coupled to the drain of the first current mirror transistor, and

[0148] The source of the first current mirror transistor is coupled to the rail;

[0149] a second current mirror transistor, wherein a gate of the second current mirror transistor is coupled to the gate of the first current mirror transistor; and

[0150] A first switch is coupled in series with the second current mirror transistor between the output terminal of the first current mirror and the rail.

[0151] 10. The system of clause 9, further comprising a control circuit configured to:

[0152] closing the first switch in an enabled mode; and

[0153] The first switch is opened in the disabled mode.

[0154] 11. The system of clause 9, wherein the first current mirror further comprises:

[0155] a third current mirror transistor, wherein a gate of the third current mirror transistor is coupled to the gate of the first current mirror transistor; and

[0156] A second switch is coupled in series with the third current mirror transistor between the output terminal of the first current mirror and the rail.

[0157] 12. The system of clause 11, further comprising a control circuit configured to:

[0158] closing the first switch in an enabled mode;

[0159] disconnecting the first switch and the second switch in a disabled mode; and

[0160] In the enabled mode:

[0161] opening the second switch for a first data rate; and

[0162] The second switch is closed for a second data rate, wherein the second data rate is higher than the first data rate.

[0163] 13. A system according to any one of clauses 1 to 8, wherein the third current mirror comprises:

[0164] a first current mirror transistor, wherein a drain of the first current mirror transistor is coupled to the input terminal of the third current mirror and a source of the first current mirror transistor is coupled to a rail;

[0165] a second current mirror transistor, wherein a gate of the second current mirror transistor is coupled to a gate of the first current mirror transistor, a drain of the second current mirror transistor is coupled to the output terminal of the third current mirror, and a source of the second current mirror transistor is coupled to the rail; and

[0166] A switch is coupled between the gate of the first current mirror transistor and the drain of the first current mirror transistor.

[0167] 14. The system of clause 13, further comprising a control circuit configured to:

[0168] closing the switch in an enabled mode; and

[0169] The switch is opened in the disabled mode.

[0170] 15. The system of any one of clauses 1 to 14, further comprising a NAND gate having a first input, a second input, and an output, wherein the first input of the NAND gate is coupled to the output of the amplifier.

[0171] 16. The system of clause 15, further comprising a control circuit configured to output a logic one to the second input of the NAND gate in an enabled mode and to output a logic zero to the second input of the NAND gate in a disabled mode.

[0172] 17. A method for amplifying a signal, the method comprising:

[0173] driving a first input transistor and a second input transistor with the signal;

[0174] multiplying the first currents from the first input transistors using a first current mirror to obtain a multiplied first current;

[0175] multiplying the second currents from the second input transistors using a second current mirror to obtain a multiplied second current;

[0176] driving a third input transistor and a fourth input transistor with the signal;

[0177] combining a third current from the third input transistor with the multiplied first current to obtain a combination of the third current and the multiplied first current; and

[0178] A fourth current from the fourth input transistor is combined with the multiplied second current to obtain a combination of the fourth current and the multiplied second current.

[0179] 18. The method according to clause 17, further comprising:

[0180] directing the combination of the third current and the multiplied first current to an output terminal using a third current mirror; and

[0181] The combination of the fourth current and the multiplied second current is provided to the output terminal.

[0182] 19. A method according to clause 17 or 18, wherein:

[0183] The first input transistor comprises a first p-type transistor;

[0184] The second input transistor comprises a second p-type transistor;

[0185] The third input transistor comprises a first n-type transistor; and

[0186] The fourth input transistor includes a second n-type transistor.

[0187] 20. A method according to any of clauses 17 to 19, wherein the signal is a differential signal or a pseudo-differential signal.

[0188] 21. The method of any of clauses 17 to 20, wherein multiplying the first current from the first input transistor using the first current mirror comprises multiplying the first current by a current mirror factor of the first current mirror.

[0189] 22. The method according to clause 21, further comprising:

[0190] setting the current mirror factor to a first factor value for a first data rate; and

[0191] The current mirror factor is set to a second factor value for a second data rate, wherein the second data rate is higher than the first data rate and the second factor value is greater than the first factor value.

[0192] It should be understood that the present disclosure is limited to the exemplary terms used above to describe aspects of the present disclosure. For example, a pad may also be referred to as a pin, an input / output (I / O) pad, or another term. In another example, a link may also be referred to as a channel, a transmission line, an interconnect, a bus, or another term. In another example, a p-type transistor may also be referred to as a p-channel transistor, and an n-type transistor may also be referred to as an n-channel transistor.

[0193] The control circuit 650 may be implemented with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete hardware components (e.g., logic gates), or any combination thereof designed to perform the functions described herein. The processor may perform the functions described herein by executing software including code for performing the functions described herein. The software may be stored on a computer readable storage medium such as RAM, ROM, EEPROM, optical disk, and / or magnetic disk.

[0194] Within this disclosure, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any specific implementation or aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the discussed feature, advantage, or mode of operation. The term "coupled" is used herein to refer to a direct or indirect electrical coupling between two structures. It should also be understood that the term "grounded" can refer to either a DC ground or an AC ground, and thus the term "grounded" covers both possibilities.

[0195] Any reference to an element using designations such as "first," "second," etc. herein does not generally limit the number or order of those elements. Rather, these designations are used herein as a convenient method of distinguishing two or more elements or instances of elements. Thus, reference to a first element and a second element does not mean that only two elements can be used or that the first element must be located before the second element.

[0196] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein, but should be granted the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A system, comprising: An amplifier, wherein the amplifier comprises: a first input transistor, wherein a gate of the first input transistor is coupled to a first input terminal of the amplifier; a second input transistor, wherein a gate of the second input transistor is coupled to a second input terminal of the amplifier; a first current mirror, wherein an input terminal of the first current mirror is coupled to a drain of the first input transistor; a second current mirror, wherein an input terminal of the second current mirror is coupled to the drain of the second input transistor and an output terminal of the second current mirror is coupled to the output of the amplifier; a third current mirror, wherein an input terminal of the third current mirror is coupled to an output terminal of the first current mirror, and an output terminal of the third current mirror is coupled to the output terminal of the amplifier; a third input transistor, wherein a gate of the third input transistor is coupled to the first input of the amplifier and a drain of the third input transistor is coupled to the input terminal of the third current mirror; and a fourth input transistor, wherein a gate of the fourth input transistor is coupled to the second input of the amplifier and a drain of the fourth input transistor is coupled to the output of the amplifier.

2. The system of claim 1, wherein: The first input transistor comprises a first p-type transistor; The second input transistor comprises a second p-type transistor; The third input transistor comprises a first n-type transistor; and The fourth input transistor includes a second n-type transistor.

3. The system of claim 1, wherein the amplifier further comprises a first resistor, wherein the first resistor is coupled between a first rail and a source of the first input transistor, and the first resistor is coupled between the first rail and a source of the second input transistor. The system of claim 3 , wherein the first resistor comprises a variable resistor.

5. The system of claim 4, further comprising a control circuit, wherein the control circuit is configured to: setting the resistance of the first resistor to a first resistance value for a first data rate; and The resistance of the first resistor is set to a second resistance value for a second data rate, wherein the second data rate is higher than the first data rate and the second resistance value is lower than the first resistance value.

6. The system of claim 3, wherein the amplifier further comprises a second resistor, wherein the second resistor is coupled between a source of the third input transistor and a second rail, and the second resistor is coupled between a source of the fourth input transistor and the second rail.

7. The system of claim 6, wherein the second rail has a lower potential than the first rail.

8. The system of claim 6, wherein: The first resistor comprises a first variable resistor; and The second resistor includes a second variable resistor.

9. The system of claim 1 , wherein the first current mirror comprises: a first current mirror transistor, wherein a drain of the first current mirror transistor is coupled to the input terminal of the first current mirror, a gate of the first current mirror transistor is coupled to the drain of the first current mirror transistor, and a source of the first current mirror transistor is coupled to a rail; a second current mirror transistor, wherein a gate of the second current mirror transistor is coupled to the gate of the first current mirror transistor; and A first switch is coupled in series with the second current mirror transistor between the output terminal of the first current mirror and the rail.

10. The system according to claim 9, further comprising a control circuit, wherein the control circuit is configured to: closing the first switch in an enabled mode; and The first switch is opened in the disabled mode.

11. The system of claim 9, wherein the first current mirror further comprises: a third current mirror transistor, wherein a gate of the third current mirror transistor is coupled to the gate of the first current mirror transistor; and A second switch is coupled in series with the third current mirror transistor between the output terminal of the first current mirror and the rail.

12. The system according to claim 11, further comprising a control circuit, wherein the control circuit is configured to: closing the first switch in an enabled mode; disconnecting the first switch and the second switch in a disabled mode; as well as In the enabled mode: opening the second switch for a first data rate; as well as The second switch is closed for a second data rate, wherein the second data rate is higher than the first data rate.

13. The system of claim 1 , wherein the third current mirror comprises: a first current mirror transistor, wherein a drain of the first current mirror transistor is coupled to the input terminal of the third current mirror and a source of the first current mirror transistor is coupled to a rail; a second current mirror transistor, wherein a gate of the second current mirror transistor is coupled to a gate of the first current mirror transistor, a drain of the second current mirror transistor is coupled to the output terminal of the third current mirror, and a source of the second current mirror transistor is coupled to the rail; and A switch is coupled between the gate of the first current mirror transistor and the drain of the first current mirror transistor.

14. The system according to claim 13, further comprising a control circuit, wherein the control circuit is configured to: closing the switch in an enabled mode; and The switch is opened in the disabled mode.

15. The system of claim 1, further comprising a NAND gate having a first input, a second input, and an output, wherein the first input of the NAND gate is coupled to the output of the amplifier.

16. The system of claim 15, further comprising a control circuit configured to output a logic one to the second input of the NAND gate in an enable mode and to output a logic zero to the second input of the NAND gate in a disable mode.

17. A method for amplifying a signal, the method comprising: driving a first input transistor and a second input transistor with the signal; multiplying the first currents from the first input transistors using a first current mirror to obtain a multiplied first current; multiplying the second currents from the second input transistors using a second current mirror to obtain a multiplied second current; driving a third input transistor and a fourth input transistor with the signal; combining a third current from the third input transistor with the multiplied first current to obtain a combination of the third current and the multiplied first current; as well as A fourth current from the fourth input transistor is combined with the multiplied second current to obtain a combination of the fourth current and the multiplied second current.

18. The method according to claim 17, further comprising: directing the combination of the third current and the multiplied first current to an output terminal using a third current mirror; as well as The combination of the fourth current and the multiplied second current is provided to the output terminal.

19. The method of claim 17, wherein: The first input transistor comprises a first p-type transistor; The second input transistor comprises a second p-type transistor; The third input transistor comprises a first n-type transistor; and The fourth input transistor includes a second n-type transistor.

20. The method of claim 17, wherein the signal is a differential signal or a pseudo differential signal.

21. The method of claim 17, wherein multiplying the first current from the first input transistor using the first current mirror comprises multiplying the first current by a current mirror factor of the first current mirror.

22. The method according to claim 21, further comprising: setting the current mirror factor to a first factor value for a first data rate; as well as The current mirror factor is set to a second factor value for a second data rate, wherein the second data rate is higher than the first data rate and the second factor value is greater than the first factor value.

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