Wafer level fabrication for multi-chip light emitting devices

Abstract

Light emitting devices are disclosed, and more particularly wafer level fabrication for multi-chip light emitting devices. Light emitting devices include certain LED package structures, such as LED chips, pedestals, and electrical connections, formed by wafer level fabrication prior to separating individual light emitting devices. The method includes bonding an LED wafer having a plurality of LED chips formed thereon to a submount wafer including corresponding metallization patterns, followed by separating individual light emitting devices. Each light emitting device includes an array of LED chips that have been bonded to a submount having electrical connections. The array of LED chips may be electrically coupled in a variety of electrical configurations based on the arrangement of metallization patterns.

Description

Technical Field

[0001] The present disclosure relates to light emitting devices, and more particularly to wafer-level fabrication for multi-chip light emitting devices. Background Art

[0002] Solid-state lighting devices, such as light emitting diodes (LEDs), are increasingly used in both consumer and commercial applications. Advances in LED technology have produced efficient and mechanically robust light sources with long service lives. As a result, modern LEDs have enabled a variety of new display applications and are increasingly used in general lighting applications, often replacing incandescent and fluorescent light sources.

[0003] An LED is a solid-state device that converts electrical energy into light, and typically includes one or more active layers (or active regions) of semiconductor material disposed between oppositely doped n-type and p-type layers. When a bias is applied to the doped layers, holes and electrons are injected into the one or more active layers, where they recombine to produce emission, e.g., visible or ultraviolet light emission. An LED chip typically includes an active region that may be made of, for example, silicon carbide, gallium nitride, gallium phosphide, indium phosphide, aluminum nitride, gallium arsenide-based materials, and / or of organic semiconductor materials.

[0004] LED packages have been developed that can provide mechanical support, electrical connections, and packaging protection for LED emitters. Multi-LED chip packages have also been developed that include an array of LED chips arranged closely together within the package. In such applications, there are challenges in producing high quality light with desired emission characteristics while also providing a suitable packaging arrangement that accommodates multiple LED chips within a single LED package.

[0005] The art continues to seek improved LEDs and solid state lighting devices having desirable lighting characteristics that overcome challenges associated with conventional lighting devices. Summary of the invention

[0006] The present disclosure relates to light emitting devices, and more particularly to wafer-level manufacturing for multi-chip light emitting devices. Such light emitting devices may include certain light emitting diode (LED) packaging structures, such as LED chips, bases, and electrical connectors, formed by wafer-level manufacturing before separating individual light emitting devices. The method includes bonding an LED wafer having multiple LED chips formed thereon to a base wafer including a corresponding metallization pattern, and then separating the individual light emitting devices. Each light emitting device includes an array of LED chips bonded to a base having electrical connectors. The array of LED chips can be electrically coupled in a variety of electrical configurations based on the arrangement of the metallization pattern.

[0007] In one aspect, a method includes: providing an LED wafer, the LED wafer including a plurality of LED chips, each of the plurality of LED chips including an anode contact and a cathode contact; providing a base wafer, the base wafer including a first metallization pattern located on the front side of the base wafer and a second metallization pattern located on the back side of the base wafer, the second metallization pattern being electrically coupled to the first metallization pattern; bonding the LED wafer to the front side of the base wafer so that the anode contact and the cathode contact of each LED chip are electrically coupled to the first metallization pattern; and dividing the LED wafer and the base wafer to form a plurality of light-emitting devices, each of the plurality of light-emitting devices including a substrate formed by the LED wafer, an array of LED chips in the plurality of LED chips, and a base formed by the base wafer. In some embodiments, the LED wafer includes a substrate structure, the substrate structure is subdivided to form each substrate of the plurality of light-emitting devices, and the base wafer includes a base structure, the base structure is subdivided to form each base of the plurality of light-emitting devices. In some embodiments, the substrate structure includes a sapphire wafer, and the plurality of LED chips are formed on the sapphire wafer. In certain embodiments, the base structure includes aluminum oxide or aluminum nitride.

[0008] In some embodiments, the first metallization pattern includes a pair of independent anode metal traces and cathode metal traces, and the pair of independent anode metal traces and cathode metal traces are respectively bonded to the anode contact and cathode contact of each LED chip in the plurality of LED chips. In some embodiments, the second metallization pattern includes a first metal trace forming an anode mounting pad, a second metal trace forming a cathode mounting pad, and a third metal trace forming a portion of a conductive path between the first metal trace and the second metal trace.

[0009] In some embodiments, a spacing between a next adjacent LED chip in the plurality of LED chips is less than or equal to 40 micrometers (μm). In some embodiments, the spacing is in a range of 10 μm to 40 μm. In some embodiments, the plurality of LED chips are subdivided by a common epitaxial LED structure. In some embodiments, bonding the LED wafer to the front side of the base wafer includes thermocompression bonding, eutectic bonding, transient liquid phase bonding, bump bonding, or solder paste bonding of the anode contact and the cathode contact to the first metallization pattern.

[0010] In some embodiments, bonding the LED wafer to the front side of the base wafer includes forming a ceramic bond between the LED wafer and the base wafer. The method may also include forming an underfill material in the gap between the LED wafer and the base wafer. In some embodiments, the LED chip array is electrically coupled in series, in parallel, or in series-parallel. In some embodiments, the second metallization pattern includes: a first metal trace pattern configured to electrically couple the LED chip array of a first light emitting device among a plurality of light emitting devices in a first electrical configuration; and a second metal trace pattern configured to electrically couple the LED chip array of a second light emitting device among a plurality of light emitting devices in a second electrical configuration. In some embodiments, the base structure includes a multilayer ceramic structure.

[0011] On the other hand, a method includes: providing an LED wafer including a plurality of LED chips on a substrate structure; forming a first bottom filling material on the LED wafer; providing a base wafer, the base wafer including a first metallization pattern located on a front side of the base wafer and a second metallization pattern located on a back side of the base wafer, the second metallization pattern being electrically coupled to the first metallization pattern; bonding the LED wafer to the front side of the base wafer so that the plurality of LED chips are electrically coupled to the first metallization pattern; and dividing the LED wafer and the base wafer to form a plurality of light-emitting devices, each of the plurality of light-emitting devices including an LED chip array among a plurality of LED chips and a base formed by the base wafer.

[0012] In some embodiments, the LED wafer includes a plurality of cuts, the plurality of cuts define the boundaries of each LED chip in the plurality of LED chips, and the first bottom fill material is arranged to fill portions of the plurality of cuts. In some embodiments, the first bottom fill material includes a light reflective material, which is configured to reflect or redirect light from the plurality of LED chips. In some embodiments, after the LED wafer is mounted to the base wafer, a first bottom fill material is formed on the LED wafer. In some embodiments, before the LED wafer is mounted to the base wafer, a first bottom fill material is formed on the LED wafer. The method may also include forming a second bottom fill material on the base wafer before the LED wafer is mounted to the base wafer. In some embodiments, the first bottom fill material and the second bottom fill material form a ceramic bond between the LED wafer and the base wafer. In some embodiments, the LED chip array is electrically coupled in series, in parallel, or in series-parallel.

[0013] On the other hand, any of the aforementioned aspects, individually or together, and / or various individual aspects and features as described herein can be combined to obtain additional advantages. Unless otherwise indicated herein, any of the various features and elements disclosed herein can be combined with one or more other disclosed features and elements.

[0014] Those skilled in the art will understand the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of the disclosure, and together with the description, serve to explain the principles of the disclosure.

[0016] Figure 1A FIG. 1 is a top view of a light emitting diode (LED) wafer, with an exploded view showing LED chips formed thereon.

[0017] Figure 1B is a top view of a base wafer, with an exploded view showing a first metallization pattern formed thereon.

[0018] Figure 2A is a cross-sectional view of a manufacturing step for forming a multi-light emitting device, wherein Figure 1A The LED wafer is positioned for mounting to Figure 1B of the base wafer.

[0019] Figure 2B yes Figure 2A Cross-sectional view of a subsequent manufacturing step in which the LED wafer is bonded to the submount wafer.

[0020] Figure 2C yes Figure 2B A cross-sectional view of a subsequent manufacturing step in which the light emitting device has been Figure 2B The vertical dashed lines in the image are separated from each other.

[0021] Figure 3A A cross-sectional view of a manufacturing step for forming a multi-light emitting device similar to Figure 2A The manufacturing steps shown in , and further include one or more bottom filling materials.

[0022] Figure 3B It is used to form a multi-light emitting device Figure 3A A cross-sectional view of a subsequent manufacturing step similar to Figure 2B The manufacturing steps are shown in FIG.

[0023] Figure 3C It is used to form a multi-light emitting device Figure 3B A cross-sectional view of a subsequent manufacturing step similar to Figure 2C The manufacturing steps are shown in FIG.

[0024] Figure 4A yes Figures 1B to 3CA view of a first side of a base wafer, wherein superimposed vertical and horizontal dashed lines form a grid with sixteen distinct device regions, each device region including four pairs of front side metal traces.

[0025] Figure 4B It is from Figure 4A The same direction Figure 4A A view of the base wafer with only the front side metal traces removed, the base structure is shown as transparent to provide a view of the back side metal traces.

[0026] Figure 4C yes Figure 4A A partial view of FIG. 1 showing four pairs of front-side metal traces for a single device area.

[0027] Figure 4D yes Figure 4B A partial view of the backside metal traces showing the location of the vias.

[0028] Figure 4E is a view of a substrate wafer with front metal traces Figure 4C The image is overlaid according to the through-hole alignment Figure 4D on the image.

[0029] Figure 4F shows an equivalent circuit of an LED chip, which can then be mounted to Figure 4E on the front metal trace.

[0030] Figure 5A is with Figure 4C A similar view of the first side of the base wafer, but with different locations of the one or more vias relative to each front side metal trace to accommodate the parallel coupling described below.

[0031] Figure 5B yes Figure 5A A view of the backside of the base wafer.

[0032] Figure 5C A view of the base wafer with front-side metal traces Figure 5A The image is overlaid according to the through-hole alignment Figure 5B on the image.

[0033] Figure 5D shows an equivalent circuit of an LED chip, which can then be mounted to Figure 5C The front metal traces.

[0034] Fig. 6A is with Figure 4C A similar view of the first side of the base wafer, but with the one or more vias positioned differently relative to each front side metal trace to accommodate a series-parallel configuration as described below.

[0035] Figure 6B yes Fig. 6A A view of the backside of the base wafer.

[0036] Figure 6C A view of the base wafer with front-side metal traces Fig. 6A The image is overlaid according to the through-hole alignment Figure 6B on the image.

[0037] Fig.6D shows the equivalent circuit of an LED chip, which can then be mounted to Figure 6C The front metal traces.

[0038] Fig. 7A is with Figure 4C The view provided is similar to a front view of a portion of a base wafer, but the base wafer includes a multi-layer structure with vias and interconnects for routing conductive paths.

[0039] Figure 7B for Fig. 7A FIG. 1 is a backside view of a submount wafer showing two backside metal traces forming anode and cathode mounting pads for corresponding light emitting devices.

[0040] Figure 7C It is along Fig. 7A A cross section taken along section line 7C-7C.

[0041] Fig.7D It is along Fig. 7A A cross section taken along section line 7D-7D. DETAILED DESCRIPTION

[0042] The embodiments set forth below represent necessary information that enables those skilled in the art to practice the embodiments, and illustrate the best way to practice the embodiments. When reading the following description according to the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure, and will recognize that these concepts and applications that are not specifically set forth herein are applied. It should be understood that these concepts and applications fall within the scope of the present disclosure and the appended claims.

[0043] It should be understood that although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items.

[0044] It should be understood that when an element, such as a layer, region or substrate, is referred to as being "on" or extending "on" another element, it can be directly on another element or directly extend to another element, or there can also be an intermediate element. On the contrary, when an element is referred to as "directly on another element" or "directly extending to another element", there is no intermediate element. Similarly, it should be understood that when an element, such as a layer, region or substrate, is referred to as being "above" another element or extending "above" another element, it can be directly above another element or extend directly above another element, or there can also be an intermediate element. On the contrary, when an element is referred to as extending "directly above another element" or "directly above another element", there is no intermediate element. It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to another element, or there can be an intermediate element. On the contrary, when an element is referred to as being "directly connected" or "directly coupled" to another element, there is no intermediate element.

[0045] Relative terms, such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical", may be used herein to describe the relationship of one element, layer or region to another element, layer or region as shown in the figures. It should be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0046] The terms used herein are used only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when used herein, the terms "comprises", "comprising", "includes", and / or "including" specify the presence of the features, wholes, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts, and / or combinations thereof.

[0047] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It should also be understood that, unless explicitly defined as such herein, the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant art, and not interpreted in an idealized or overly formal sense.

[0048] Embodiments are described herein with reference to schematic diagrams of embodiments of the present disclosure. Therefore, the actual sizes of layers and elements may be different, and due to factors such as manufacturing processes and / or tolerances, it is foreseeable that there will be deviations from the illustrated shapes. For example, an area shown or described as a square or rectangle may have circular or curved features, and an area shown as a straight line may have some irregularities. Therefore, the area shown in the accompanying drawings is schematic, and its shape is not intended to illustrate the precise shape of the area of ​​the device, and is not intended to limit the scope of the present disclosure. In addition, for illustrative purposes, the size of a structure or region may be enlarged relative to other structures or regions, and therefore, these sizes or regions are provided to illustrate the general structure of the present subject and may or may not be drawn to scale. Common elements between the drawings may be shown herein as having common element numbers, and may not be repeatedly described subsequently.

[0049] The present disclosure relates to light emitting devices, and more specifically, to wafer-level manufacturing for multi-chip light emitting devices. Such light emitting devices may include certain light emitting diode (LED) packaging structures, such as LED chips, bases, and electrical connectors, formed by wafer-level manufacturing before separating individual light emitting devices. The method includes bonding an LED wafer having multiple LED chips formed thereon to a base wafer including a corresponding metallization pattern, and then separating the individual light emitting devices. Each light emitting device includes an array of LED chips bonded to a base having electrical connectors. The array of LED chips can be electrically coupled in a variety of electrical configurations based on the arrangement of the metallization pattern.

[0050] The light emitting device disclosed herein may include multiple LED chips with certain LED packaging structures (such as a base and electrical connectors) connected together by wafer-level manufacturing. By connecting the multiple LED chips to a base including wafer-level electrical connectors, a single LED chip group that has been bonded to the base using electrical connectors can be divided to form a multi-LED chip light emitting device.

[0051] Before delving into the specific details of various aspects of the present disclosure, an overview of various elements that may be included in an exemplary light emitting device of the present disclosure is provided for context. An LED chip typically includes an active LED structure or region that may have many different semiconductor layers arranged in many different ways. The manufacture and operation of LEDs and their active structures are well known in the art and are only briefly discussed herein. The layers of the active LED structure can be manufactured using known processes, one suitable process being metal organic chemical vapor deposition. The layers of the active LED structure typically include many different layers, and typically include an active layer sandwiched between epitaxial layers of opposite doping types of n-type and p-type, all of which are formed in sequence on a growth substrate. It should be understood that the active LED structure may also include additional layers and elements, including but not limited to buffer layers, nucleation layers, superlattice structures, undoped layers, cladding layers, contact layers, and current diffusion layers and light extraction layers and elements. The active layer may include a single quantum well, a multiple quantum well, a double heterostructure, or a superlattice structure.

[0052] Active LED structures can be made from different material systems, some of which are based on Group III nitride material systems. Group III nitrides refer to those semiconductor compounds formed between nitrogen (N) and elements in Group III of the periodic table, typically aluminum (Al), gallium (Ga), and indium (In). Gallium nitride (GaN) is a common binary compound. Group III nitrides also refer to ternary and quaternary compounds, such as aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN). For Group III nitrides, silicon (Si) is a common n-type dopant, and magnesium (Mg) is a common p-type dopant. Therefore, for Group III nitride-based material systems, the active layer, n-type layer, and p-type layer can include one or more layers of GaN, AlGaN, InGaN, and AlInGaN that are undoped or doped with Si or Mg. Other material systems include silicon carbide (SiC), organic semiconductor materials, and other III-V systems such as gallium phosphide (GaP), gallium arsenide (GaAs), and related compounds.

[0053] The active LED structure can be grown on a growth substrate, which can include many materials, such as sapphire, SiC, aluminum nitride (AlN), GaN, GaAs, glass, or silicon. SiC has certain advantages, such as being more closely lattice-matched to III-nitrides than other substrates, enabling high-quality III-nitride films to be obtained. SiC also has very high thermal conductivity, so that the total output power of III-nitride devices on SiC is not limited by the heat dissipation of the substrate. Sapphire is another common substrate for III-nitrides and also has certain advantages, including lower cost, mature manufacturing processes, and good light-transmitting optical properties.

[0054] Depending on the composition of the active layer and the n-type and p-type layers, different embodiments of the active LED structure can emit light of different wavelengths. In some embodiments, the active LED structure can emit blue light with a peak wavelength range of approximately 430 nanometers (nm) to 480 nm. In other embodiments, the active LED structure can emit green light with a peak wavelength range of 500 nm to 570 nm. In other embodiments, the active LED structure can emit red light with a peak wavelength range of 600 nm to 650 nm. In some embodiments, the active LED structure can emit light with a peak wavelength range in any region of the visible spectrum, such as light with a peak wavelength primarily in the range of from 400 nm to 700 nm.

[0055] In some embodiments, the active LED structure can be configured to emit light outside the visible spectrum, including one or more portions of the ultraviolet (UV) spectrum, infrared (IR) or near IR spectrum. The UV spectrum is generally divided into three wavelength range categories represented by the letters A, B and C. In this way, UV-A light is generally defined as a peak wavelength range from 315nm to 400nm, UV-B is generally defined as a peak wavelength range from 280nm to 315nm, and UV-C is generally defined as a peak wavelength range from 100nm to 280nm. UV LEDs are particularly suitable for applications related to microbial disinfection in air, water, and surfaces, as well as other applications. In other applications, UV LEDs may also be provided with one or more luminescent materials to provide LED packages with a concentrated emission having a wide spectrum and improved color quality for visible light applications. The near IR and / or IR wavelengths used in the LED structure of the present disclosure may have a wavelength higher than 700nm, such as in the range of 750nm to 1100nm or greater.

[0056] The LED chip can also be covered with one or more luminescent or other conversion materials, such as phosphors, so that at least some of the light from the LED chip is absorbed by the one or more phosphors and converted to a spectrum of one or more different wavelengths according to the characteristic emission from the one or more phosphors. In some embodiments, the combination of the LED chip and the one or more phosphors emits a light combination that is generally white. The one or more phosphors can include yellow light (e.g., YAG:Ce), green light (e.g., LuAg:Ce), and red light (e.g., Ca:Ce). i-x-y Sr x Eu y AlSiN 3 ) and combinations thereof. The luminescent materials as described herein may be or include one or more of phosphors, scintillators, luminescent inks, quantum dot materials, fluorescent light strips, and the like. The luminescent material may be provided in any suitable manner, for example, directly coated on one or more surfaces of the LED, dispersed in a sealant material configured to cover one or more LEDs, and / or coated on one or more optical or support elements (e.g., by powder coating, inkjet printing, etc.). In some embodiments, the luminescent material may be down-converted or up-converted, and a combination of down-converted and up-converted materials may be provided. In some embodiments, a plurality of different (e.g., different compositions) luminescent materials configured to produce different peak wavelengths may be configured to receive emissions from one or more LED chips. In some embodiments, one or more phosphors may include a yellow phosphor (e.g., YAG:Ce), a green phosphor (e.g., LuAg:Ce), and a red phosphor (e.g., Ca i-x-y Sr x Eu y AlSiN 3 ) and combinations thereof. One or more luminescent materials can be disposed on one or more portions of the LED chip and / or the base in various configurations.

[0057] As used herein, a layer or region of a light emitting device may be considered "transparent" when at least 80% of the emitted radiation incident on the layer or region exits through the layer or region. In addition, as used herein, a layer or region is considered "reflective" or embodied as a "reflector" or "reflector" when at least 80% of the emitted radiation incident on the layer or region of the LED is reflected. In some embodiments, the emitted radiation includes visible light, such as blue and / or green LEDs with or without luminescent materials. In other embodiments, the emitted radiation may include non-visible light. For example, in the context of GaN-based blue and / or green LEDs, silver (Ag) may be considered a reflective material (e.g., at least 80% reflective). In the case of UV LEDs, appropriate materials may be selected to provide a desired, and in some embodiments, high reflectivity and / or a desired, and in some embodiments, low absorptivity. In certain embodiments, a "light-transmitting" material may be configured to transmit at least 50% of the emitted radiation of the desired wavelength.

[0058] The present disclosure can be used for LED chips having a variety of geometries, including flip chip geometries. Flip chip structures for LED chips typically include anode and cathode connections made from the same side or face of the LED chip. The anode and cathode sides are typically configured as mounting surfaces for the LED chip for mounting the flip chip to another surface, such as a printed circuit board. In this regard, the anode and cathode connections on the mounting surface are used to mechanically engage and electrically couple the LED chip to another surface. When the flip chip is mounted, the opposite side or face of the LED chip corresponds to a light emitting surface that is oriented toward the intended light emission direction. In certain embodiments, when the flip chip is mounted, a growth substrate for the LED chip can form a light emitting surface and / or adjacent to the light emitting surface. During chip manufacturing, the active LED structure can be epitaxially grown on the growth substrate.

[0059] The LED package may include one or more elements arranged together with one or more LED chips, such as luminescent materials, sealants, light regulating materials, lenses, and electrical contacts. In some aspects, the LED package may include a support, such as a base. Materials suitable for the base include, but are not limited to, ceramic materials, such as alumina or aluminum, AlN, or organic insulators, such as polyimide (PI) and polyphthalamide (PPA). In other embodiments, the base may include a printed circuit board (PCB), sapphire, Si, or any other suitable material. For PCB embodiments, different PCB types may be used, such as standard FR-4 PCB, metal core PCB, or any other type of PCB. A metal trace pattern may be provided on one or more sides of the base for receiving one or more LED chips and / or electrical connections to one or more LED chips. A sealant may be formed to cover the LED chip on the base to provide protection for the LED package elements below, and sometimes to provide light shaping for the emission from the LED package. The sealant may include a material having light transmittance and / or transparency at the wavelength provided by the LED chip and / or luminescent material below. Suitable sealant materials include silicone, plastic, epoxy, or glass. In certain aspects, the encapsulant can include a lens shape for controlling light emission.

[0060] According to various aspects of the present disclosure, a light emitting device may include multiple LED chips with certain LED packaging structures (such as a base and electrical connectors) that are connected together by wafer-level manufacturing. By connecting multiple LED chips to a base including wafer-level electrical connectors, a single LED chip group that has been bonded to the base using electrical connectors can be divided to form a multi-LED chip light emitting device. Wafer-level manufacturing may include bonding the LED wafer to the base wafer before the various light emitting devices are divided. As used herein, the LED wafer may include a growth substrate that has been deposited with an epitaxial LED structure over a large area. A single LED chip along the growth substrate may be formed by post-epitaxial manufacturing, which may include removing portions of the epitaxial LED structure along the cut to define the boundaries of the LED chip. The LED wafer may include other post-epitaxial manufacturing, such as forming a reflective structure, anode and cathode electrical contacts for each LED chip, and / or a passivation layer, etc. As used herein, the base wafer may include a ceramic material (such as alumina or aluminum, AlN), or an organic insulator (such as PI and PPA), or PCB, sapphire, Si, or any other suitable material. As described in more detail below, a metal trace pattern can be provided on one or more sides of the submount for receiving one or more LED chips of an LED wafer and / or making electrical connections to one or more LED chips of an LED wafer.

[0061] For multi-chip applications, wafer-level manufacturing provides many advantages, including avoiding complex pick-and-place steps for discrete LED chips, wherein a separate die attachment step is provided for each LED chip. In multi-chip applications, increasing the number of separate die attachment steps can lead to increased failures and / or electrical shorts associated with bonding strength differences and / or chip alignment deviations. Through wafer-level bonding, multiple LED chips can be simultaneously bonded to the electrical connectors of the base wafer, while the spacing between adjacent LED chips is fixed by the LED wafer. According to various aspects of the present disclosure, after wafer-level manufacturing, a spacing between the next adjacent LED chips in a multi-chip light-emitting device can be provided, which is less than or equal to 40 microns (μm), or in the range of 10μm to 40μm, or in the range of 20μm to 40μm, or in the range of 20μm to 30μm. At the wafer level, multiple LED chips can be defined by a common epitaxial structure by forming a cut between them. In this way, each LED chip can form a mesa along the LED wafer, and the above spacing value can be measured from the edge of the mesa to the edge of the mesa of the next adjacent LED chip. This close spacing may be important in multi-chip light emitting devices where multiple LED chips are arranged to collectively provide a single light emitting surface or the appearance of a single LED chip. In certain embodiments, the substrate on which the LED chips are formed is continuous, thereby also enhancing the appearance of a single LED chip. For example, in a flip chip embodiment where the emission exits through the substrate, having a continuous substrate with no gaps between the LED chips can provide the appearance of a single light emitting surface. It should be understood that the principles described herein are also applicable to applications with larger spacing between LED chips.

[0062] Another advantage of wafer-level manufacturing relates to avoiding the need to group discrete LED chips according to brightness, wavelength and / or turn-on voltage before assembly in a common device. With wafer-level manufacturing, the next adjacent LED chip is formed by the same area of ​​the common epitaxial LED structure, thereby eliminating the need to group individually by brightness, wavelength and / or turn-on voltage. Yet another advantage of wafer-level manufacturing relates to the ability to electrically connect multiple LED chips in different configurations by simply providing different metal trace patterns on the base wafer. For example, the base wafer can include patterns that electrically connect multiple LED chips in series, parallel, or series-parallel manners and can be individually addressed. It is worth noting that wafer-level manufacturing, combined with the above-mentioned tight spacing of the LED chips, provides such flexible electrical connections. In some embodiments, a monolithic high-voltage chip can be formed by multiple LED chips connected in a series or series-parallel arrangement, thereby increasing the operating voltage and reducing the step-down voltage required for the electronic driver to improve the overall system efficiency.

[0063] Figure 1AFIG. 1 is a top view of an LED wafer 10, with an exploded view showing LED chips 12 formed thereon. The LED wafer 10 includes a substrate structure 14 having a wafer shape. Figure 1A In the embodiment, the wafer shape is circular, and in other embodiments, the wafer shape may be square or rectangular. The substrate structure 14 may embody a growth wafer, such as sapphire, SiC, AlN or GaN, etc., and the epitaxial LED structure as described above may be deposited on the growth wafer. Various manufacturing steps may define the LED chip 12 according to the epitaxial LED structure, including forming one or more reflective layers, passivation layers, anode contacts 16 and cathode contacts 18 for each LED chip 12. A cut 20 is formed to define the boundary of each LED chip 12. The cut 20 may embody an area where the epitaxial LED structure is removed from the substrate structure 14. In this way, the cut 20 defines the spacing between the next adjacent LED chips 12. As described above, in some embodiments, this spacing may be less than or equal to 40 μm, or in the range of 10 μm to 40 μm, or in the range of 20 μm to 40 μm, or in the range of 20 μm to 30 μm.

[0064] Figure 1B 2 is a top view of a base wafer 22, with an exploded view showing a first or front metallization pattern formed thereon. The base wafer 22 includes a base structure 24 having a wafer shape. In some embodiments, the wafer shape of the base structure 24 is similar to Figure 1A The base structure 24 may include any of the materials described above and may form a precursor structure that, when subdivided, provides a separate base for multiple light-emitting devices. The first metallization pattern includes a repeating pattern of a plurality of pairs of first metal traces 26-1 and second metal traces 26-2. Each pair of first metal traces 26-1 and second metal traces 26-2 is formed with Figure 1A The anode contact 16 and the cathode contact 18 have corresponding shapes. In this way, when Figure 1A One side of the LED wafer 10 is mounted to Figure 1B Each anode contact 16 can be mechanically bonded to and electrically coupled to a corresponding first metal trace 26-1 when the side of the base wafer 22 visible in FIG. 2 is shown. In a similar manner, each cathode contact 18 can be mechanically bonded to and electrically coupled to a corresponding second metal trace 26-2. As will be described in more detail later, one or more vias 28 can be arranged to provide a conductive path through the base structure 24 to a second metallization pattern located on the opposite side or back side of the base wafer 22.

[0065] Figure 2Ais a cross-sectional view in a manufacturing step for forming a multi-light emitting device 30, wherein Figure 1A The LED wafer 10 is positioned to be mounted to Figure 1B The base wafer 22. For illustrative purposes, Figure 2A The view provided in FIG. 1 shows only four LED chips 12 with corresponding dicing streets 20, and the superimposed vertical dashed lines 32 indicate the locations of the individual light emitting devices 30 that will be separated later. In practice, the number of individual light emitting devices 30 formed can be much greater, and each individual light emitting device 30 can include more than two LED chips 12. A wafer aligner can be used to correctly position the LED wafer 10 relative to the base wafer 22 so that the anode contact 16 can be aligned with the first metal trace 26-1, and the cathode contact 18 can be aligned with the second metal trace 26-2.

[0066] like Figure 2A As shown, separate vias 28 may be arranged to electrically couple each of the first metal trace 26-1 and the second metal trace 26-2 of the first metallization pattern on the first side 22′ or front side of the submount wafer 22 with the second metallization pattern on the second side 22″ or back side of the submount wafer 22. The first metal trace 26-1 and the second metal trace 26-2 may also be referred to herein as front metal traces 26-1, 26-2. The second metallization pattern may be formed by back metal traces 34-1 to 34-3 configured to provide various electrical connections between the LED chips 12. For example, with Figure 2A The first metal trace 26-1 and the second metal trace 26-2 associated with the leftmost LED chip 12 in the embodiment are coupled to the back metal traces 34-1 and 34-2, respectively, while the back metal trace 34-2 is also electrically coupled to the first metal trace 26-1 associated with the next adjacent LED chip 12. Finally, the second metal trace 26-2 associated with the next adjacent LED chip 12 is electrically coupled to the back metal trace 34-3. In this way, the LED chips 12 of each light emitting device 30 can be electrically coupled in series based on the arrangement of the base wafer 22.

[0067] Figure 2B yes Figure 2A2 is a cross-sectional view of a subsequent manufacturing step in which the LED wafer 10 is bonded to the base wafer 22. As shown, the corresponding anode contacts 16 and cathode contacts 18 are bonded to the corresponding front metal traces 26-1, 26-2. This wafer bonding can be provided by various techniques that mechanically and electrically bond the metal of each anode contact 16 and each cathode contact 18 to the metal of the corresponding front metal traces 26-1, 26-2. For example, the bonding can include thermocompression bonding of certain identical metals, such as gold (Au), copper (Cu), or aluminum (Al), etc., which are present at the interface formed between the anode contact 16 or the cathode contact 18 and the corresponding front metal traces 26-1, 26-2. Other bonding can involve a die attach metal stack formed at the interface, such as a eutectic metal stack, including gold-tin (Au-Sn), gold-silicon (Au-Si), gold-germanium (Au-Ge), aluminum-germanium (Al-Ge), or gold-indium (Au-In), etc. Still other bonding may involve transient liquid phase bonding through copper-tin (Cu-Sn), gold-indium (Au-In), or silver-tin (Ag-Sn), etc. Additional bonding may involve bump bonding through a pattern of solder bumps or through solder paste bonding.

[0068] Figure 2C yes Figure 2B A cross-sectional view of a subsequent manufacturing step in which the light emitting device 30 has been Figure 2B The vertical dashed lines 32 in the figure are separated from each other. The separation can be achieved by wafer cutting or segmentation, such as mechanical saw cutting or laser cutting. After separation, each light emitting device 30 includes Figure 2B The substrate structure 14 is separated from the substrate 14' and Figure 2B The substrate 14' is separated from the base structure 24. Each light emitting device 30 can embody a multi-chip device in which an array of LED chips 12 are closely spaced and formed by a common area of ​​the epitaxial LED structure. The spacing can be determined by the previously described cut-way 20. The light emitting device 30 can be very suitable for arrangement within an LED package or within a larger LED lighting system. In some embodiments, the substrate 14' can include a material that is transmissive or transparent to the wavelengths generated by the LED chips 12, such as sapphire. In other embodiments, the substrate 14' may not be required. For example, Figure 2B The substrate structure 14 can be removed after being bonded to the base wafer 22, so that Figure 2C The light emitting device 30 may not include the substrate 14'.

[0069] After singulation, the back metal traces 34-1 and 34-3 of each light emitting device 30 form anode and cathode mounting pads for mounting to external electrical connections, while the other back metal trace 34-2 forms part of the conductive path therebetween. For example, the conductive path between back metal trace 34-1 and back metal trace 34-3 is routed through the base 24', through the left LED chip 12, back through the base 24' to the back metal trace 34-2, back through the base 24' to the next LED chip 12, and finally back through the base 24' to the back metal trace 34-3.

[0070] FIG. 3A to FIG. 3C A cross-sectional view showing a manufacturing step for forming a plurality of light emitting devices 36 similar to FIG. 2A to FIG. 2C The light emitting device 30 further comprises one or more bottom filling materials 38-1, 38-2. In this way, FIG. 2A to FIG. 2C The description of the fabrication steps is easily applicable to FIG. 3A to FIG. 3C The manufacturing steps are provided together with other details below.

[0071] Figure 3A is a cross-sectional view of a manufacturing step for forming a plurality of light emitting devices 36, the manufacturing step being similar to Figure 2A The manufacturing steps are shown in Figure 3AIn some embodiments, the first bottom fill material 38-1 can be formed on the LED wafer 10 to fill the cut streets 20 and other topographical changes associated with the LED chip 12, the anode contact 16 and / or the cathode contact 18. Before the removal step is taken to expose the surface of the anode contact 16 and the cathode contact 18, the first bottom fill material 38-1 can be initially formed to completely cover the LED chip 12, the anode contact 16 and the cathode contact 18. The removal step can include grinding and / or polishing the first bottom fill material 38-1 to effectively planarize the first bottom fill material with the anode contact 16 and the cathode contact 18. In some embodiments, the first bottom fill material 38-1 can be coplanar with the exposed surface of the anode contact 16 and the cathode contact 18. The first bottom fill material 38-1 may include a light regulating and / or light reflecting material configured to redirect light propagating downward from the LED chip 12 to increase brightness. In some embodiments, the first bottom fill material 38-1 can be formed by painting, partially or fully curing the dispense or spin coating, etc. The first underfill material 38-1 may include a ceramic material that enhances bonding, such as a ceramic slurry, a spin-on dielectric, and / or a sol-gel reaction (e.g., an inorganic colloidal suspension and gelation in a continuous liquid phase). The second underfill material 38-2 may be formed on the base wafer 22 in a similar manner and using similar materials as the first underfill material 38-1. In this manner, the second underfill material 38-2 may cover topographical variations associated with the front metal traces 26-1, 26-2 or other features that may be present on the first side 22'. In other embodiments, the second underfill material 38-2 may be omitted.

[0072] Figure 3B is used to form a plurality of light emitting devices 36 Figure 3A A cross-sectional view of a subsequent manufacturing step similar to Figure 2B. Thus, as described above, the LED wafer 10 is bonded to the base wafer 22. As shown, the presence of the first bottom fill material 38-1 and the second bottom fill material 38-2 can effectively fill the gap between the base wafer 22 and the LED wafer 10. In this way, an improved thermal contact area can be provided. For embodiments in which the first bottom fill material 38-1 and the second bottom fill material 38-2 include ceramic materials as described above, the ceramic materials can form a ceramic bond therebetween, thereby improving mechanical integrity and enhancing thermal conduction of the light emitting device 36. In some embodiments, the first bottom fill material 38-1 and the second bottom fill material 38-2 may not be formed before the wafers are bonded. Instead, the first bottom fill material 38-1 and the second bottom fill material 38-2 may be applied after bonding to fill the space between the LED wafer 10 and the base wafer 22. For example, the bottom fill materials 38-1, 38-2 can be applied with an appropriate viscosity so as to effectively wick and fill the space between the LED wafer 10 and the base wafer 22 before curing. In such an embodiment, the first underfill material 38 - 1 and the second underfill material 38 - 2 may embody a single continuous layer.

[0073] Figure 3C is used to form a plurality of light emitting devices 36 Figure 3B A cross-sectional view of a subsequent manufacturing step similar to Figure 2C In this regard, a single light emitting device 36 may be formed with a first underfill material 38-1 and a second underfill material 38-2 between the substrate 14' and the base 24'. Figure 2C In certain embodiments, substrate 14' may be optional.

[0074] The configuration of the front and back metal traces of the above-described base wafer can be well suited for providing different electrical arrangements of wafer-bonded LED chips. The principles described can be applied to electrical configurations of LED chips coupled in series, in parallel, in a combination of series and parallel, and to multi-chip light-emitting devices in a single addressable configuration. In some aspects, the base wafer can be formed with different back metal trace patterns at different locations, so that after wafer bonding with an LED wafer and subsequent singulation, some light-emitting devices can be formed with a first electrical configuration, and other light-emitting devices from the same LED wafer can be formed with a second electrical configuration that is different from the first electrical configuration. Thus, many different types of light-emitting devices can be manufactured simultaneously by simply providing various back metallization patterns along the base wafer.

[0075] Figure 4A and Figure 4B Shown above Figures 1B to 3CA larger portion of the submount wafer 22 is depicted that provides the series connections between the LED chips of the corresponding light emitting devices. Figure 4A 2 is a view of a first side of a base wafer 22', wherein superimposed vertical and horizontal dashed lines 32 form a grid having sixteen different device regions, each device region including four pairs of front metal traces 26-1, 26-2. As described above, the front metal traces 26-1, 26-2 are configured to be bonded to, for example, FIG. 2A to FIG. 2C 16 and cathode contacts 18 of the LED chip 12 shown in FIG. For illustrative purposes, Figure 4B It is from Figure 4A The same view of the base wafer 22 is shown with the front metal traces 26-1, 26-2 removed and the base structure 24 shown as transparent. The location of the through hole 28 remains as shown. In this way, the location of the back metal traces 34-1 to 34-5 is arranged with the same Figure 4A Therefore, without rotation, Figure 4A The diagram can be Figure 4B 's icon overlay.

[0076] FIG. 4C to FIG. 4E Shown from Figure 4A and Figure 4B A portion of the base wafer 22 is one of the device regions. Figure 4C yes Figure 4A , showing four pairs of front metal traces 26-1, 26-2 for a single device area. In this way, four LED chips can be flip-chip mounted to multiple pairs of front metal traces 26-1, 26-2. Figure 4D yes Figure 4B , showing the location of back metal traces 34-1 through 34-5 along with through-hole 28. Back metal traces 34-1, 34-5 form anode mounting pads and cathode mounting pads for mounting to external electrical connectors, while other back metal traces 34-2, 34-3 and 34-4 form portions of interconnection paths therebetween. To accommodate the various interconnection paths, certain back metal traces (e.g., 34-2, 34-3, 34-5) intended to electrically couple different LED chips together can have shapes that differ from one another, such as a wider shape (e.g., 34-2), a non-linear shape (e.g., 34-3), and / or a longer shape (e.g., 34-4). Although Figure 4C The portion of the base structure 24 is shown as a square, but can be adjusted to correspond to Figure 4A and Figure 4B The location of the separation line of the dashed line 32 in the figure can be used to provide other shapes, such as a rectangle.

[0077] Figure 4Eis a view of a substrate wafer 22 with front metal traces 26-1, 26-2. Figure 4C The image is overlaid according to the alignment of the through hole 28 Figure 4D Vias 28 define locations where some of front metal traces 26 - 1 , 26 - 2 are electrically coupled to corresponding ones of back metal traces 34 - 1 to 34 - 5 through base structure 24 . Figure 4F An equivalent circuit 40 is shown for an LED chip 12 that may then be mounted to front metal traces 26-1, 26-2 of first side 22'. As shown, the arrangement of vias 28 and back metal traces 34-1 to 34-5 provides a series arrangement of LED chips that may be used in high voltage applications.

[0078] FIG. 5A to FIG. 5D Shown provides 4A to 4D The additional configuration of the base wafer 22 provides parallel connection for the corresponding light emitting devices. Figure 5A is similar to Figure 4C 2 ′ of the base wafer 22 , except that the location of the one or more vias 28 relative to each front side metal trace 26 - 1 , 26 - 2 is different to accommodate parallel coupling as described below. Figure 5B yes Figure 5A 2 is a view of the back side 22" of the base wafer 22. As shown, only two back side metal traces 34-1, 34-2 are arranged relative to the through hole 28, the back side metal trace 34-1 forming the anode mounting pad and the back side metal trace 34-2 forming the cathode mounting pad. Figure 5C is a view of a substrate wafer 22 with front metal traces 26-1, 26-2. Figure 5A The image is overlaid according to the alignment of the through hole 28 Figure 5B . Vias 28 define locations where some of front metal traces 26-1, 26-2 are electrically coupled to corresponding ones of back metal traces 34-1, 34-2 through base structure 24. As shown, each front metal trace 26-1 is electrically coupled to back metal trace 34-1, and each front metal trace 26-2 is electrically coupled to back metal trace 34-2. Figure 5D 4 shows an equivalent circuit 42 of an LED chip 12 that can then be mounted to the front metal traces 26-1, 26-2 of the first side 22'. As shown, the arrangement of the through-holes 28 and the back metal traces 34-1, 34-2 provides a parallel arrangement for the LED chips 12. In some embodiments, a single submount wafer 22 may include one or more regions, such as FIG. 5A to FIG. 5D As shown, these regions are configured to provide parallel connections for light emitting devices and may also include one or more other regions, such as 4A to 4F As shown, these regions are configured to provide a series connection for the light emitting devices.

[0079] FIG. 6A to FIG. 6D Shows 4A to 4D Another additional configuration of the base wafer 22 provides series-parallel connections for corresponding light emitting devices. Fig. 6A is similar to Figure 4C 2 ′ of the base wafer 22 , except that the location of the one or more vias 28 relative to each front side metal trace 26 - 1 , 26 - 2 is different to accommodate series-parallel coupling as described below. Figure 6B yes Fig. 6A 2 is a view of the back side 22" of the base wafer 22. As shown, only three back side metal traces 34-1 to 34-3 are arranged relative to the through hole 28, and the back side metal traces 34-1, 34-3 form the anode mounting pad and the cathode mounting pad, and the back side metal trace 34-2 forms part of the electrical interconnection therebetween. Figure 6C is a view of a substrate wafer 22 with front metal traces 26-1, 26-2. Fig. 6A The image is aligned according to the through hole 28 overlaid on Figure 6B Vias 28 define locations where some of front metal traces 26 - 1 , 26 - 2 are electrically coupled to corresponding ones of back metal traces 34 - 1 to 34 - 3 through base structure 24 . Fig.6D An equivalent circuit 44 of an LED chip 12 is shown, which can then be mounted to the front metal traces 26-1, 26-2 of the first side 22'. As shown, the arrangement of the through-holes 28 and the back metal traces 34-1 to 34-3 provides and arranges the LED chips 12 in series. In some embodiments, a single base wafer 22 may include: one or more regions, such as FIG. 6A to FIG. 6D As shown in , these regions are configured to provide parallel connections for light emitting devices; and one or more other regions, such as 4A to 4F As shown in , these regions are configured to provide series connections for light emitting devices. In yet other embodiments, a single base wafer 22 may include 4A to 4F , FIG. 5A to FIG. 5D , FIG. 6A to FIG. 6D Different areas of each.

[0080] 7A to 7DAn alternative configuration of a base wafer 46 is shown, which includes a multilayer structure with through-holes and interconnects that route conductive paths between the front metal traces 26-1, 26-2 and the back metal traces 34-1, 34-2. The multilayer arrangement of the substrate structure 24 may include a plurality of sub-layers 48-1 to 48-3, providing increased flexibility in routing electrical connections. In some embodiments, the sub-layers 48-1 to 48-3 may include a laminate structure having through-holes 28 and interconnects 50 formed therein. The laminate structure may include a multilayer ceramic structure, such as a multilayer printed circuit board.

[0081] Fig. 7A is with Figure 4C The view provided is similar to the front view of a portion of the submount wafer 46. Thus, four pairs of front metal traces 26-1, 26-2 for a single device region are shown. However, as with the previous embodiments, any number of pairs of front metal traces 26-1, 26-2 may be provided depending on the number of LED chips per light emitting device. Figure 7B for Fig. 7A 4, which shows two back metal traces 34-1, 34-2 forming anode and cathode mounting pads for corresponding light emitting devices. Although there are only two back metal traces 34-1, 34-2, any number of series, parallel, and series-parallel arrangements can be provided by the multi-layer configuration of the base structure 24. Figure 7C It is along Fig. 7A A cross section taken along section line 7C-7C. Fig.7D It is along Fig. 7A 7D-7D of FIG. As shown, front traces 26-1, 26-2 may be formed on sub-layer 48-1, and a plurality of vias 28 may extend from each front trace 26-1, 26-2 through sub-layer 48-1. Interconnects 50 may be arranged in the next sub-layer 48-2, which redirects the conductive path horizontally within the base structure 24. Figure 7C In the cross section of FIG. 4 , another via 28 is arranged in the next sub-layer 48-3, which provides a conductive path to the back metal trace 34-1. The conductive path to the other back metal trace 34-2 can be arranged in Figure 7C and Fig.7D other locations outside the cross section.

[0082] As described above, the multi-layer structure can increase the design flexibility of the base wafer 46. For example, the backside metal traces 34-1, 34-2 can form a single anode and a single cathode, and their patterns are not necessarily the same as those of the base wafer 46. Figure 7BThe positions of each through hole 28 shown in are associated. Therefore, other areas of the back side are open to include other features, such as a neutral thermal pad for heat dissipation purposes. In other embodiments, the multi-layer structure allows additional anode contacts and cathode contacts to provide individual addressability for the LED chips. Various shapes of light emitting devices can be formed from a base wafer with a multi-layer structure, such as squares and rectangles.

[0083] It is contemplated that any of the above aspects and / or various individual aspects and features as described herein may be combined to obtain additional advantages. Unless otherwise indicated herein, any of the various embodiments disclosed herein may be combined with one or more other disclosed embodiments.

[0084] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the appended claims.

Claims

1. A method comprising: Providing a light emitting diode (LED) wafer, the light emitting diode LED wafer comprising a plurality of LED chips, each LED chip of the plurality of LED chips comprising an anode contact and a cathode contact; Providing a base wafer, the base wafer comprising a first metallization pattern located on a front side of the base wafer and a second metallization pattern located on a back side of the base wafer, the second metallization pattern being electrically coupled to the first metallization pattern; bonding the LED wafer to the front side of the submount wafer such that the anode contact and the cathode contact of each LED chip are electrically coupled to the first metallization pattern; as well as The LED wafer and the base wafer are divided to form a plurality of light emitting devices, each of which includes a substrate formed of the LED wafer, an LED chip array of the plurality of LED chips, and a base formed of the base wafer.

2. The method according to claim 1, wherein: The LED wafer includes a substrate structure that is subdivided to form each substrate of the plurality of light emitting devices, and the submount wafer includes a submount structure that is subdivided to form each submount of the plurality of light emitting devices.

3. The method according to claim 2, wherein: The substrate structure includes a sapphire wafer, and the plurality of LED chips are formed on the sapphire wafer.

4. The method according to claim 2, wherein: The base structure includes aluminum oxide or aluminum nitride.

5. The method according to claim 1, wherein: The first metallization pattern includes a pair of independent anode and cathode metal traces respectively bonded to the anode and cathode contacts of each LED chip of the plurality of LED chips.

6. The method according to claim 5, wherein: The second metallization pattern includes a first metal trace forming an anode mounting pad, a second metal trace forming a cathode mounting pad, and a third metal trace forming a portion of a conductive path between the first metal trace and the second metal trace.

7. The method according to claim 1, wherein: A pitch between next adjacent LED chips in the plurality of LED chips is less than or equal to 40 micrometers (μm).

8. The method according to claim 7, wherein: The pitch is in the range of 10 μm to 40 μm.

9. The method according to claim 1, wherein: The plurality of LED chips are subdivided from a common epitaxial LED structure.

10. The method according to claim 1, wherein: Bonding the LED wafer to the front side of the submount wafer includes thermocompression bonding, eutectic bonding, transient liquid phase bonding, bump bonding, or solder paste bonding the anode contact and the cathode contact to the first metallization pattern.

11. The method according to claim 1, wherein: Bonding the LED wafer to the front side of the submount wafer includes forming a ceramic bond between the LED wafer and the submount wafer. 12 . The method of claim 1 , further comprising forming an underfill material in a gap between the LED wafer and the submount wafer.

13. The method according to claim 1, wherein: The LED chip arrays are electrically coupled in series, in parallel, or in series-parallel.

14. The method according to claim 1, wherein: The second metallization pattern comprises: a first metal trace pattern configured to electrically couple the LED chip array of a first light emitting device of the plurality of light emitting devices in a first electrical configuration; and A second metal trace pattern is configured to electrically couple the LED chip array of a second light emitting device of the plurality of light emitting devices in a second electrical configuration.

15. The method according to claim 1, wherein: The base structure includes a multi-layer ceramic structure.

16. A method comprising: Providing a light emitting diode (LED) wafer on the substrate structure, wherein the light emitting diode LED wafer includes a plurality of LED chips; forming a first bottom filling material on the LED wafer; Providing a base wafer, the base wafer comprising a first metallization pattern located on a front side of the base wafer and a second metallization pattern located on a back side of the base wafer, the second metallization pattern being electrically coupled to the first metallization pattern; bonding the LED wafer to the front side of the submount wafer such that the plurality of LED chips are electrically coupled to the first metallization pattern; as well as The LED wafer and the submount wafer are divided to form a plurality of light emitting devices, each of which includes an LED chip array of the plurality of LED chips and a submount formed by the submount wafer.

17. The method according to claim 16, wherein: The LED wafer includes a plurality of scribe lines defining boundaries of each of the plurality of LED chips, and the first underfill material is arranged to fill portions of the plurality of scribe lines.

18. The method according to claim 16, wherein: The first underfill material includes a light reflective material configured to reflect or redirect light from the plurality of LED chips.

19. The method according to claim 16, wherein: The first underfill material is formed on the LED wafer after the LED wafer is mounted to the submount wafer.

20. The method according to claim 16, wherein: The first underfill material is formed on the LED wafer before the LED wafer is mounted to the submount wafer. 21 . The method of claim 20 , further comprising forming a second underfill material on the submount wafer before mounting the LED wafer to the submount wafer.

22. The method according to claim 21, wherein: The first underfill material and the second underfill material form a ceramic bond between the LED wafer and the submount wafer.

23. The method according to claim 16, wherein: The LED chip arrays are electrically coupled in series, in parallel, or in series-parallel mode.

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