Memory element with previously updated word line selection and protection of potentially vulnerable word lines and related methods

Abstract

A memory element and a protection method thereof are provided. The memory element includes a controller configured to update a first word line and a first protected word line during a first update period in response to an update signal; a random number generator configured to receive an address of the first word line and an address of the first protected word line to generate a first number; a counter electrically coupled to the random number generator. The counter is configured to receive the first number as an initial value of the counter, and configured to start in response to the update signal. The controller is configured to obtain an address of a second access word line being accessed when the counter counts down to zero, and update a second protected word line adjacent to the second access word line during a second update period.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 18 / 514,043 (i.e., priority date "November 20, 2023"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a memory element and a method for protecting the same. In particular, it relates to a memory element including a protection circuit for protecting a word line. Background Technology

[0003] Dynamic Random Access Memory (DRAM) stores each bit of data in a separate capacitor. A simple DRAM cell contains a single transistor and a single capacitor. If charge is stored in the capacitor, the cell is said to store a logic high (HIGH), depending on the convention used. Then, if no charge is present, the cell is said to store a logic low (LOW). Because the charge in the capacitor dissipates over time, DRAM systems require additional refresh circuitry to periodically update the charge stored in the capacitor. Since capacitors can only store a very limited amount of charge, two bit lines (BLs) are typically used for each bit to quickly distinguish between logic "1" and logic "0". The first bit in the bit line pair is called the bit line complement (BLT), and the other is called the bit line complement (BLC). The gate of a single transistor is controlled by a word line (WL).

[0004] Raw hammer is a security issue stemming from an unexpected and undesirable side effect of DRAM, where memory cells electrically cross each other due to leaked charge, potentially altering the contents of unaddressed neighboring memory columns (word lines) during a raw memory access. Raw hammer can be triggered by specific memory access patterns that repeatedly and rapidly activate the same memory column (word line). Consequently, memory cells connected to adjacent word lines leak charge and struggle to retain their original contents through subsequent periodic update cycles. A malicious operator can exploit the raw hammer effect to alter the contents of neighboring memory columns, leading to device failure. Therefore, there is a need to develop a method to protect memory (especially its word lines) and mitigate the described problem.

[0005] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0006] One embodiment of this disclosure provides a memory element. The memory element structure includes a plurality of word lines; and a controller configured to update a first word line and a first protected word line among the plurality of word lines during a first update cycle in response to an update signal, wherein the first protected word line is adjacent to the first access word line. The memory element further includes a random number generator configured to receive an address of the first word line and an address of the first access word line to generate a first number; and a counter electrically coupled to the random number generator. The counter is configured to receive the first number as an initial value for the counter and is configured to be enabled in response to the update signal. The controller is also configured to obtain an address of a second access word line being accessed when the counter decrements to zero, and to update a second protected word line during a second update cycle, wherein the second protected word line is adjacent to the second access word line.

[0007] Another embodiment of this disclosure provides a memory element. The memory element includes a plurality of word lines; a controller configured to update a first word line and adjacent word lines of a first access word line in the plurality of word lines during a first update cycle in response to an update signal; a random number generator configured to generate a first number based on the address of the first word line and the address of the first access word line; a counter electrically coupled to the random number generator, wherein the counter is configured to receive the first number as an initial value of the counter and to begin counting down in response to the update signal; and an address register electrically coupled to the counter, wherein the address register is configured to store an address of a second access word line that is valid when the counter counts down to zero. The controller is also configured to access the address register to obtain the address of the second access word line and to protect adjacent word lines of the second access word line during a second update cycle.

[0008] Another embodiment of this disclosure provides a method for protecting a memory element, wherein the semiconductor element includes a plurality of word lines. The protection method updates a first word line and a first protected word line among the plurality of word lines during a first update cycle in response to an update signal, wherein the first protected word line is adjacent to the first access word line; generates a first number by a random number generator based on an address of the first word line and an address of the first access word line; counts down from the first number by a counter in response to the update signal; when the counter reaches zero, obtains an address of a second access word line being accessed by a controller; and protects a second protected word line during a second update cycle, wherein the second protected word line is adjacent to the second access word line.

[0009] Embodiments of this disclosure provide a memory element having a protection circuit for selecting and protecting a vulnerable word line. Specifically, the memory protection circuit can protect word lines (memory cells) from column hammers. To trigger a column hammer, a malicious operator rapidly activates the same memory column, potentially causing charge leakage on adjacent unactivated memory columns. This protection circuit provides a random number generator and a counter to randomly select and protect potentially vulnerable memory columns. The counter can be configured to count down from a random number generated by the random number generator. When the counter reaches zero, an address of the activated memory column can be obtained. In other words, the memory column is selected from memory columns activated between multiple update cycles. In this case, the selection pool includes memory columns activated between multiple update cycles. The random number generator can generate a random number based on the address of the last updated word line and the address of the last accessed word line (the selected potentially vulnerable word line), thereby increasing the unpredictability of the random number. Additionally, to prevent the random number generated by the random number generator from exceeding the maximum number of activations between update cycles, the number adjuster modifies the random number to a range from zero to a predetermined number (i.e., the maximum number of activations between update cycles). Since memory columns adjacent to the activated memory columns are more likely to be affected by column hammering, they will be protected in subsequent update cycles.

[0010] Typically, the number of times a column hammer is triggered cannot be completed within two update cycles. For example, a memory element with 8192 rows may have approximately 170 activations between multiple update cycles, and the number of column hammer activations in the same column could be 10,000 or more. Therefore, protecting additional memory columns that may be subject to column hammers in each update cycle can eliminate the column hammer problem. Furthermore, the memory element can include a digital adjuster to determine whether the random number used to select a column in the memory exceeds the maximum number of activations between update cycles (i.e., 170 in this case), and then reduce the random number to between 0 and 170. This improves the security and performance of the memory element.

[0011] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure by modifying or designing other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0012] A more complete understanding of this disclosure can be obtained by referring to the detailed description and claims. This disclosure should also be understood to be associated with element numbers in the drawings, which represent similar elements throughout the description.

[0013] Figure 1 This is a schematic diagram illustrating memory elements of some embodiments of the present disclosure.

[0014] Figure 2 This is a schematic diagram illustrating memory elements of some embodiments of the present disclosure.

[0015] Figure 3 This is a schematic diagram illustrating the activation of character lines along the timeline between update cycles in some embodiments of this disclosure.

[0016] Figure 3A This is a schematic diagram illustrating the character line addresses accessed along the timeline at each startup between update cycles according to some embodiments of this disclosure.

[0017] Figure 3B This is a schematic diagram illustrating the character line addresses accessed along the timeline at each startup between update cycles according to some embodiments of this disclosure.

[0018] Figure 3C This is a schematic diagram illustrating the character line addresses accessed along the timeline at each startup between update cycles according to some embodiments of this disclosure.

[0019] Figure 4A This is a schematic diagram illustrating the character line addresses accessed along the timeline between update cycles in some embodiments of this disclosure, as well as the updated character line addresses, column hammer target character line addresses, and initial countdown numbers in each update cycle.

[0020] Figure 4B This is a schematic diagram illustrating the character line addresses accessed along the timeline between update cycles in some embodiments of this disclosure, as well as the updated character line addresses, column hammer target character line addresses, and initial countdown numbers in each update cycle.

[0021] Figure 4C This is a schematic diagram illustrating the character line addresses accessed along the timeline between update cycles in some embodiments of this disclosure, as well as the updated character line addresses, column hammer target character line addresses, and initial countdown numbers in each update cycle.

[0022] Figure 4D This is a schematic diagram illustrating the character line addresses accessed along the timeline between update cycles in some embodiments of this disclosure, as well as the updated character line addresses, column hammer target character line addresses, and initial countdown numbers in each update cycle.

[0023] Figure 5This is a flowchart illustrating a method for protecting memory elements according to some embodiments of this disclosure.

[0024] The reference numerals in the attached figures are explained as follows:

[0025] 1: Memory element

[0026] 2: Memory elements

[0027] 3: Schematic diagram

[0028] 3A: Schematic diagram

[0029] 3B: Schematic diagram

[0030] 3C: Illustration

[0031] 4A: Schematic diagram

[0032] 4B: Schematic diagram

[0033] 4C: Schematic diagram

[0034] 4D: Schematic diagram

[0035] 5: Protection Methods

[0036] 11: Memory Unit

[0037] 12: Sensing Amplifier

[0038] 21: Memory Unit

[0039] 22: Controller

[0040] 23: Random Number Generator

[0041] 23A: First number

[0042] 23B: The second number (the revised first number)

[0043] 24: Counter

[0044] 25: Address Register

[0045] 26: Digital Adjuster

[0046] 111: Memory Column

[0047] 112: Memory Column

[0048] 113: Memory Column

[0049] 114: Memory Column

[0050] 131: Column Address Decoder

[0051] 132: Row Address Decoder

[0052] 211: Character Line

[0053] 212: Character Line

[0054] 213: Character Line

[0055] 214: Character Line

[0056] act_1, act_2, act_3, ..., act_N-1, act_N: Startup

[0057] Add CBR Character line

[0058] Add LRH Character line

[0059] CBR: Update Cycle

[0060] CBR+1: Update Cycle

[0061] CBR+2: Update Cycle

[0062] CBR+3: Update Cycle

[0063] CBR+4: Update Cycle

[0064] CBR+5: Update Cycle

[0065] CDN: Initial countdown number

[0066] CDN dec Initial countdown number

[0067] CDN hex Initial countdown number

[0068] N max Maximum number of accesses

[0069] R / W: Read / Write signal

[0070] RS: Update signal

[0071] T act Time period

[0072] T CBR Time period

[0073] WL: Character line address

[0074] WL1: Word line address

[0075] WL2: Word line address

[0076] WL3: Wordline Address Detailed Implementation

[0077] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplicity and clarity and, unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0078] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the inventive concept of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0079] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms “comprises” and / or “comprising” are used in this specification, these terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0080] It should be understood that, in the description of this disclosure, the term "about" as used to describe the quantity of ingredients, components, or reactants of this disclosure refers to variations in quantity that may occur, for example, through typical measurements used to prepare concentrates or solutions and liquid handling procedures. Furthermore, variations may occur due to negligence in measurement procedures, differences in the manufacture, source, or purity of the ingredients used to manufacture the composition or carry out the method. In one aspect, the term "about" means within 10% of the reported value. In another aspect, the term "about" means within 5% of the reported value. Furthermore, in yet another aspect, the term "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

[0081] Figure 1 This is a schematic diagram illustrating a memory element 1 according to some embodiments of the present disclosure. The memory element 1 may include an array of multiple memory cells 11, multiple sense amplifiers 12, a column address decoder 131, and a row address decoder 132. In some embodiments, the memory element 1 may be a DRAM.

[0082] Please refer to Figure 1 The array of memory cells 11 may comprise multiple columns and rows. Each row of memory cells may share a single bit line or a pair of bit lines. Each column of memory cells may share a single word line. In some embodiments, a single memory cell may include a capacitor and a transistor, and is configured to store one bit of data therein. The charging state (charging or discharging) of a capacitor determines whether the memory cell stores a "1" or a "0" as a binary value.

[0083] In some embodiments, the memory address of an array of memory cells 11 applied to a matrix can be represented as column address and row address, which are processed by column address decoder 131 and row address decoder 132. When column address decoder 131 selects a particular column (e.g., memory column 114) for a read operation (this selection is also called column-driven), bits from all memory cells in that particular column can be transferred to sense amplifier 12. In some embodiments, a sense amplifier 12 is used for each row of memory cells to temporarily hold data. In some embodiments, row address decoder 132 can select the exact bit from one of the sense amplifiers 12. In some embodiments, sense amplifier 12 can be configured to receive or transmit data in response to read / write signals R / W. Write operations decode the address in a similar manner, but can rewrite the entire column to change the value of a single bit.

[0084] Because data bits are stored in capacitors with a natural discharge rate, the state stored in memory cell 11 may be lost over time. Therefore, all memory cells need to be periodically rewritten, a process called updating, to preserve the information stored in the memory cells. Each memory update cycle can update one or more columns of memory cells, and all memory cells can be repeatedly updated in consecutive cycles. Memory updates can be performed in several ways. In some embodiments, memory updates can be performed by different modes of signaling, such as column address strobing (RAS) updates, row address strobing before column address strobing (CAS-before-RAS) updates (CBR updates for short), and hidden updates.

[0085] To trigger the column hammer, the same memory column 111 can be activated at a high frequency and in a high quantity. When the activation frequency and activation quantity of memory column 111 are high enough, the charge on the unactivated neighboring memory columns 112 and 113 may leak, and therefore the data / content stored therein may be lost.

[0086] This protection circuit provides a random number generator and a counter (see detailed description for details). Figure 3 A counter is configured to randomly select and protect a possible memory column. The counter can be configured to count down from a random number generated by a random number generator. When the counter reaches zero, an address of the activated memory column (e.g., memory column 111) is obtained. In other words, the memory column is selected from memory columns activated between update cycles. Nearby memory columns 112 and 113 adjacent to the activated memory column 111 are more likely to suffer from column hammer effects and will therefore be protected in subsequent update cycles. In some embodiments, memory columns 112 and 113, as well as a planned update memory column 114, can be updated in subsequent update cycles.

[0087] Figure 2 This is a schematic diagram illustrating memory element 2 of some embodiments of this disclosure. Please refer to... Figure 2 The memory element 2 may include an array of multiple memory cells 21, a controller 22, a random number generator 23, a counter 24, an address register 25, and a digital adjuster 26. In some embodiments, the memory element 2 may be a dynamic random access memory (DRAM).

[0088] In some embodiments, the array of memory cells 21 may include multiple word lines. In some embodiments, the array of memory cells 21 may include a potential target word line 211 being accessed, i.e., a column hammer target, two adjacent word lines 212 and 213 adjacent to the potential target word line 211, and a normal word line 214. The normal word line 214 may be located anywhere in the array 21. For example, the normal word line 214 may be an edge word line or a word line sandwiched between two word lines. In one embodiment, the normal word line 214 may be separate from the potential target word line 211. In another embodiment, the normal word line 214 may be adjacent to the potential target word line 211 (not shown).

[0089] Controller 22 may be configured to update at least one of a plurality of word lines during a first update cycle by providing an update signal RS. In some embodiments, the update signal RS may be generated by controller 22 itself based on a clock signal. In other embodiments, controller 22 may be configured to update at least one of a plurality of word lines during a first update cycle in response to an update signal RS. In such embodiments, controller 22 may receive the update signal RS from other elements (not shown). In some embodiments, the update signal RS may be a RAS update instruction or a CBR update instruction. Controller 22 may be configured to update one or more word lines during an update cycle. In some embodiments, controller 22 may be configured to update one, two, three, four or more word lines simultaneously. In some embodiments, controller 22 may be configured to update the array of all memory cells 21 cycle by cycle. In some embodiments, controller 22 may be configured to update the array of all memory cells 21 in a predetermined pattern (i.e., an update pattern).

[0090] Random number generator 23 can be configured to generate a first number 23A. The first number 23A can be a positive integer. In some embodiments, the first number 23A can be binary. The first number 23A can be represented by a binary sequence having more than 2 bits. For example, the first number 23A can be represented by an 8-bit binary sequence. That is, the first number 23A can be a number in the range of 0 to 255. In other embodiments, the first number 23A can be more or less than 8 bits.

[0091] Please refer to Figure 2 The random number generator 23 may include a logic gate. The logic gate 23 may include an OR gate, an AND gate, an XOR gate, an XNOR gate, etc. In some embodiments, the random number generator 23 may be an XOR gate.

[0092] In some embodiments, logic gate 23 may have a first input terminal, a second input terminal, and an output terminal. In some embodiments, logic gate 23 may be configured to receive a character line Add updated in a previous update cycle at the first input terminal. CBR An address. Logic gate 23 can be configured to receive the accessed character line Add at the second input terminal. LRH The address is a possible target column hammer character line located in a previous update cycle. In some embodiments, logic gate 23 can be configured to respond to character line Add. CBR Address and access character lines Add LRH The address is used to generate the first number 23A.

[0093] In some embodiments, character lines AddCBR Address and access character lines Add LRH The address of each word line can be represented by a 4-bit hexadecimal sequence. The address of a word line represented by a 4-bit hexadecimal sequence can be converted to a 16-bit binary sequence.

[0094] In some embodiments, logic gate 23 can be configured to be based on character line Add. CBR Part of the address and access character line Add LRH The first number 23A is generated from a portion of the address. In some embodiments, when the character line Add... CBR When the address is represented as a 4-bit hexadecimal sequence, the word line Add... CBR This portion of the address can be 2 bits, which is half the total bit length. In other embodiments, regardless of the total bit length, the word line Add... CBR This part of the address can be the last two bits. In some embodiments, the hexadecimal character lines can be added. CBR The address is converted to binary. In some embodiments, the word line Add... CBR The 2-bit hexadecimal address can be converted to 8-bit binary.

[0095] In some embodiments, when accessing the character line Add LRH When the address is represented as a 4-bit hexadecimal sequence, the access word line Add... LRH This portion of the address can be 2 bits, which is half the total bit length. In other embodiments, the access character line Add... LRH This portion of the address can be the last two bits, regardless of the total bit length. In some embodiments, the access character line Add... LRH The hexadecimal address can be converted to binary. In some embodiments, the access bit line Add... LRH The 2-bit hexadecimal address can be converted to 8-bit binary.

[0096] Add character line for random number generator 23 CBR And access character line Add LRH The extracted portions can have the same bit length. In some embodiments, the random number generator 23 adds character lines Add CBR And access character line Add LRH The number of bits retrieved can be determined based on the size of the memory array.

[0097] In some embodiments, the output of the random number generator 23 can be coupled to the counter 24. The random number generator 23 can output the first number 23A from its output to the counter 24.

[0098] Random number generator 23 can be configured to respond to character line Add. CBR Address and access character lines Add LRH The address is used to generate a random number (i.e., the first number is 23A). Although the character line Add can be predetermined based on the update pattern. CBR However, the accessed character line can be randomly selected from the memory array. LRH Therefore, the first number 23A may be more difficult to predict. Thus, the security of memory element 2 can be improved.

[0099] A digital adjuster 26 may be connected to a random number generator 23 and configured to receive a first number 23A. The digital adjuster 26 may be a circuit that reduces the first number 23A to less than a threshold value. In some embodiments, the digital adjuster 26 may be configured to generate a modified first number 23B (or a second number 23B) based on the first number 23A. In some embodiments, when the first number 23A is greater than a first predetermined number, the digital adjuster 26 may modify the first number 23A to the modified first number 23B. In some embodiments, the first predetermined number is the maximum number of accesses between update cycles (see [details omitted]). Figure 3 After modification, the modified first number 23B is less than the first predetermined number. The modified first number 23B can be less than the first number 23A.

[0100] Figure 3 It is an indication Figure 3 Examples of some embodiments of this disclosure illustrate the initiation of character lines along the timeline between update cycles.

[0101] Please refer to Figure 3 Along the timeline (i.e., the x-axis), a time period T CBR Located between a first update cycle CBR and a second update cycle CBR+1. In some embodiments, the second update cycle CBR+1 immediately follows the first update cycle CBR. In some embodiments, each of the first update cycle CBR and the second update cycle CBR+1 may include a time period for the update job and an idle time period. The idle time period referred to here is the waiting time from the start of update cycle CBR to the start of update cycle CBR+1. Therefore, the time period T CBR It can be from the start of the first update cycle CBR to the start of the second update cycle CBR+1.

[0102] In some embodiments, N starts (act_1, act_2, act_3, ..., act_N-1, act_N) occur between the first update cycle CBR and the second update cycle CBR+1. Each start, act_1, act_2, act_3, act_N-1, and act_N, represents an access to a word line. Time period T act It occurs between two startups. For example, the time period T. act This can occur between launching act_1 and act_2. In some embodiments, the time period T act It can be the minimum necessary time to access a single word line (e.g., the first start act_1).

[0103] To clearly illustrate this disclosure, a memory array with 8,000 word lines is used as an example. The memory array may include 8,192 word lines. The address of a word line can be represented by a hexadecimal sequence, for example, using 4 bits. In some embodiments, the time to update all word lines (i.e., 8,192 word lines) can be 64 ms. In this case, the time period T required to update one word line is... CBR This can be calculated as 64ms / 8192, therefore the time period T CBR The interval is 7.8125 μs. In other words, for a total of 8k character lines, the time interval T from the start of the first update cycle to the start of the second update cycle is... CBR It could be 7.8125 μs. Assume the time period T... act If the interval is 45.75 ns, then the maximum number of accesses N between update cycles is... max According to the formula To calculate. Therefore, the maximum number of accesses N max It can be 7.8125μs / 45.75ns=170.765≈170, that is... Figure 3 The number of times N is 170. In this embodiment, 170 character lines can be accessed between update cycles. Accordingly, the first number 23A received by counter 24 can be modified to be lower than a predetermined number (e.g., 170 in this embodiment).

[0104] In some embodiments, the first number 23A may be less than a predetermined number, which is related to the time period T used for accessing the character line. act and the time period T between the first update cycle CBR and the second update cycle CBR+1 CBRRelatedly, in some embodiments, counter 24 may be configured to reset its initial value when the first number 23A is greater than a predetermined number. For example, the initial value of counter 24 may be reset to zero or a constant less than the predetermined number. Thus, counter 24 can count down from an initial value in the range of 0 to a predetermined number (i.e., the maximum number of accesses between update cycles), and when it decrements to zero, selectable character lines may be protected during subsequent update cycles.

[0105] Please refer to this again. Figure 2 The modified first number 23B can be represented in the same form as the first number 23A. In some embodiments, both the first number and the modified number can be binary. For example, if the first number 23A is represented by an 8-bit binary sequence, then the modified first number 23B is also represented by an 8-bit binary sequence. In some embodiments, the first number 23A can be represented by a binary sequence having Bit7, Bit6, Bit5, Bit4, Bit3, Bit2, Bit1, and Bit0. The modified first number 23B can be represented by a binary sequence having Bit7', Bit6', Bit5', Bit4', Bit3', Bit2', Bit1', and Bit0'.

[0106] The difference between the first number 23A and the modified first number 23B can be a single bit in the binary sequence. For example, the most significant bit (msb) of the first number 23A can be different from the most significant bit of the modified first number 23B. That is, bit 7' of the modified first number 23B is different from bit 7 of the first number 23A. In some embodiments, bits 6' to 0' of the modified first number 23B can be the same as bits 6 to 0 of the first number 23A. In another embodiment, the modified first number 23B can be reset to zero by the number adjuster 26. Therefore, bits 7' to 0' of the modified first number 23B are logic "0".

[0107] Conversely, when the first number 23A is less than the first predetermined number, the number adjuster 26 will not take any action on the first number 23A. In this case, the modified first number 23B will be the same as the original first number 23A.

[0108] Counter 24 may be electrically coupled to random number generator 23 and digital adjuster 26. In some embodiments, counter 24 may be electrically coupled to random number generator 23 via digital adjuster 26. Counter 24 may be configured to receive a modified first number 23B as an initial value for counter 24. In one embodiment, when the first number 23A is less than a first predetermined number, the modified first number 23B is the same as the first number 23A, and counter 24 decrements from the modified first number 23B (i.e., the first number 23A). In another embodiment, when the first number 23A is greater than a first predetermined number, the first number 23A is modified to a modified first number 23B that is less than the first predetermined number, and counter 24 decrements from the modified first number 23B that is different from the first number 23A.

[0109] In some embodiments, counter 24 is configured to start in response to an update signal RS received from controller 22. In other words, counter 24 may be configured to start counting down in response to update signal RS. Counter 24 may be configured to decrement from an initial value (i.e., a first number 23A or a modified first number 23B).

[0110] In some embodiments, counter 24 may be configured to decrement in response to an access signal indicating an access to one of the word lines.

[0111] Address register 25 can be electrically coupled to counter 24. Address register 25 can be configured to obtain and store the address of the first word line 211 (or possibly the target word line 211) that is valid when counter 24 decrements to zero.

[0112] Figure 3A It is an indication Figure 3A Examples of some embodiments of this disclosure include the character line addresses accessed along the timeline during each activation between update cycles CBR and CBR+1.

[0113] Please refer to Figure 3A Each time act_1, act_2, act_3, act_4, ..., and act_N are started, the word line address WL1 is accessed. In this case, regardless of the initial value of counter 24, address register 25 stores the most frequently accessed word line address WL1. In other words, word line address WL1 is most likely to be the target of malicious operators. Therefore, selecting a word line adjacent to the word line address WL1 to be protected can prevent hammer attacks.

[0114] Figure 3B It is an indication Figure 3B Examples of some embodiments of this disclosure include the character line addresses accessed along the timeline at each startup between update cycles CBR and CBR+1.

[0115] Please refer to Figure 3B The address register 25 accesses word line address WL1 at startup act_1, word line address WL2 at startup act_2, word line address WL1 at startup act_3, word line address WL2 at startup act_4, and word line address WL2 at startup act_N. That is, only word line addresses WL1 and WL2 are accessed. In this case, regardless of the initial value of counter 24, address register 25 stores the word line address WL1 or WL2 that is accessed most frequently. In some embodiments, word line addresses WL1 and WL2 are each 50% likely to be attacked. In other words, word line addresses WL1 and WL2 are most likely to be targeted by an attacker. Therefore, selecting the word line adjacent to word line address WL1 or WL2 for protection can prevent hammer attacks.

[0116] Figure 3C It is an indication Figure 3C Examples of some embodiments of this disclosure include the word line addresses accessed along the timeline at each startup between update cycles CBR and CBR+1.

[0117] Please refer to Figure 3C The word line address WL1 is accessed at startup act_1. Word line address WL2 is accessed at startup act_2. Word line address WL3 is accessed at startup act_3. Word line address WL1 is accessed at startup act_4. Word line address WL2 is accessed at startup act_N-1. Word line address WL3 is accessed at startup act_N. In some embodiments, word line addresses WL1, WL2, and WL3 are repeatedly accessed sequentially. That is, only word line addresses WL1, WL2, and WL3 are accessed between update cycles. In this case, address register 25 stores one of word line addresses WL1, WL2, and WL3. In some embodiments, the probability that word line addresses WL1, WL2, and WL3 are attacked can be approximately 33.33%. In other words, word line addresses WL1, WL2, and WL3 are most likely to be targeted by malicious operators. Therefore, selecting a character line adjacent to character line address WL1, WL2, or WL3 for protection can prevent column hammering.

[0118] Please refer to Figures 3A-3C The address of the character line to be protected can be randomly selected from those character lines that are valid between two update cycles. The character lines are selected from the character lines initiated between update cycles. In this case, the selection pool includes the character lines initiated between update cycles.

[0119] Please refer back to the previous page. Figure 2The controller 22 can be configured to access the address register 25 during a second update cycle to obtain the address of the first word line and protect the second word lines 212 / 213 (i.e., adjacent word lines 212 or 213). To protect the second word lines 212 / 213, the controller can be configured to update the second word lines 212 / 213 during the second update cycle in response to an update signal. In some embodiments, the second update cycle follows the first update cycle. For example, the second update cycle is a subsequent update cycle to the first update cycle. In some embodiments, the second word lines 212 / 213 are adjacent to the first word line 211.

[0120] Controller 22 can be configured to update one or more word lines during an update cycle. In some embodiments, controller 22 can be configured to update one, two, three, four, or more word lines simultaneously. Controller 22 can be configured to update adjacent word lines 212 and 213 during the same update cycle. In some embodiments, in addition to the second word lines 212 / 213, controller 22 can also be configured to update a third word line 214 during a second update cycle in response to an update signal RS, wherein the address of the third word line 214 is the same as the address of the first word line 211.

[0121] In some embodiments, controller 22 may be configured to update a character line adjacent to a possible target character line 211 and another character line separated from the possible target character line 211. For example, character lines 212 and 214 may be updated during a second update cycle. In some embodiments, in one update cycle, controller 22 may be configured to update a normal character line (e.g., character line 214) and a high-risk character line (e.g., character line 212 or 213) according to a predetermined update pattern determined by random number generator 23 and counter 24. That is, in one update cycle, at least one normal update character line and at least one character line with a high risk of column hammer effect may be updated simultaneously.

[0122] In this disclosure, when the counter 24 decrements to zero, the address of the first character line 211 to be started (or a possible target character line 211) can be obtained. In this case, the address of the character line to be protected can be randomly selected from those character lines that are valid during the two update cycles. In addition, the digital adjuster 26 modifies the first number 23A to a range of 0 to a first predetermined number to avoid the first number 23A exceeding the maximum number of starts between update cycles.

[0123] Figure 4A It is an indication Figure 4A This illustrates, in some embodiments of the present disclosure, the character line addresses accessed along the timeline between update cycles CBR and CBR+1, and the update character line address Add in each update cycle.CBR , Column hammer target character line address Add LRH And the initial reciprocal number CDN.

[0124] Please refer to Figure 4A The word line address WL with the value 1235 is stored at startup act_1. The word line address WL with the value 0021 is stored at startup act_2. The word line address WL with the value 1235 is stored at startup act_3. The word line address WL with the value 1235 is stored at startup act_59. The word line address WL with the value 0021 is stored at startup act_60. The word line address WL with the value 1235 is stored at startup act_N-1. The word line address WL with the value 0021 is stored at startup act_N. That is, only the two word line addresses with the values ​​1235 and 0021 are stored. In some embodiments, Figure 4A The word line address in the code is represented by a 4-bit hexadecimal sequence. In other words, the hexadecimal word line address WL of 1235 is equivalent to decimal 4661 and binary 0001001000110101. The hexadecimal word line address WL of 0021 is equivalent to decimal 33 and binary 0000000000100001.

[0125] In the update cycle CBR, the update character line address AddCBR could be, for example, 1ABC. When the update cycle CBR is the initial update cycle, there are no previous update cycles, so the possible target column hammer character line is located at address Add. LRH (In previous update cycles) it could be 0000. The hexadecimal word line address WL of 1ABC is equivalent to decimal 6844, which is equivalent to 0001101010111100. For example... Figure 2 The random number generator 23 discussed can be configured to respond to a hexadecimal update character line address Add. CBR Add the target character line address of the column hammer. LRH The last two bits are used to generate the first number 23A.

[0126] Responding to the update character line address Add CBR The last two bits are BC and the column hammer target word line address is Add. LRH The last two bits are 00, and the initial reciprocal number is CDN. hex That is, the first number 23A (the initial number of counter 24), which, according to the operation of logic gate 23 (e.g., XOR), can be a hexadecimal 3C. In some embodiments, the initial countdown number CDN hex =3C can be equal to the initial reciprocal number CDN dec=60. In this case, counter 24 can count down from 60, and address register 25 can be configured to obtain the word line address accessed at start act_60 between update cycles CBR and CBR+1, which is the word line address (WL) of 0021. Therefore, in the next update cycle CBR+1, the column hammer target word line address Add LRH It will be 0021. That is to say, during the update cycle CBR+1, the adjacent word line address 0021 (for example, the word line address of 0020 or 0022) can be protected.

[0127] In update cycle CBR+1, update character line address Add CBR It can be 1ABD, column hammer target character line address Add LRH It can be 0021. The word line address WL of hexadecimal 1ABD can be equivalent to decimal 6845, and is equivalent to 0001101010111101.

[0128] Responding to the update character line address Add CBR The last two bits are BD and the column hammer target character line address is Add. LRH The last two bits are 21. Based on the operation of logic gate 23 in the update cycle CBR+1 (e.g., XOR), the initial reciprocal number CDN hex It can be hexadecimal 9C. In some embodiments, the initial countdown number is CDN. hex =9C can be equal to the initial reciprocal number CDN dec =156. In this case, counter 24 can count down from 156, and address register 25 can be configured to obtain the word line address accessed at start act_156 between update cycles CBR+1 and CBR+2 (see...). Figure 4B ).

[0129] Figure 4B It is an indication Figure 4B This illustrates, in some embodiments of the present disclosure, the character line addresses accessed along the timeline between update cycles CBR+1 and CBR+2, and the update character line address Add in each update cycle. CBR , Column hammer target character line address Add LRH And the initial reciprocal number CDN.

[0130] Please refer to Figure 4BThe system accesses the following word line addresses: WL (1235) at startup act_1; WL (0021) at startup act_2; WL (1235) at startup act_3; WL (1235) at startup act_155; WL (0021) at startup act_156; WL (1235) at startup act_N-1; and WL (0021) at startup act_N. In other words, only the word line addresses 1235 and 0021 are accessed.

[0131] In update cycle CBR+1, update character line address Add CBR It can be 1ABD, column hammer target character line address Add LRH It can be 0021. For example... Figure 4A As shown, in response to the update character line address Add CBR The last two bits are BD and the column hammer target character line address is Add. LRH The last two bits are 21, and the initial reciprocal number in the update cycle CBR+1 CDN hex It can be hexadecimal 9C. In some embodiments, the initial countdown number is CDN. hex =9C can be equal to the initial reciprocal number CDN dec =156. In this case, counter 24 can count down from 156, and address register 25 can be configured to obtain the word line address stored at start act_156 between update cycles CBR+1 and CBR+2, which is the word line address (WL) of 0021. Accordingly, in the subsequent update cycle CBR+2, the target word line address Add is... LRH It will also be 0021. That is to say, in the update cycle CBR+2, the word line address that is adjacent to 0021 (for example, the word line address of 0020 or 0022) can be protected.

[0132] In update cycle CBR+2, update character line address Add CBR It can be 1ABE, column hammer target character line address Add LRH It can be 0021. The word line address WL of hexadecimal 1ABE can be equivalent to decimal 6846, and is equivalent to 0001101010111110.

[0133] Responding to the update character line address Add CBR The last two bits are BE and the column hammer target word line address is Add. LRH If the last two bits are 21, then the initial reciprocal number in the update cycle CBR+2 is CDN. hexIt can be hexadecimal 9F. In some embodiments, the initial countdown number is CDN. hex =9F can be equal to the initial reciprocal number CDN dec =159. In this case, counter 24 can count down from 159, and address register 25 can be configured to obtain the word line address accessed at start act_159 between update cycles CBR+2 and CBR+3 (see...). Figure 4C ).

[0134] Figure 4C It is an indication Figure 4C This illustrates, in some embodiments of the present disclosure, the character line addresses accessed along the timeline between update cycles CBR+2 and CBR+3, and the update character line address Add in each update cycle. CBR , Column hammer target character line address Add LRH And the initial reciprocal number CDN.

[0135] Please refer to Figure 4C The system accesses the following word line addresses: WL (1235) at startup act_1; WL (0021) at startup act_2; WL (1235) at startup act_3; WL (1235) at startup act_159; WL (0021) at startup act_160; WL (1235) at startup act_N-1; and WL (0021) at startup act_N. In other words, only the word line addresses of 1235 and 0021 are accessed.

[0136] In update cycle CBR+2, update character line address Add CBR It can be 1ABE, column hammer target character line address Add LRH It could be 0021. For example... Figure 4B As shown, in response to the update character line address Add CBR The last two bits are BE and the column hammer target word line address is Add. LRH The last two bits are 21, and the initial reciprocal number in the update cycle CBR+2 CDN hex It can be hexadecimal 9F. In some embodiments, the initial countdown number is CDN. hex =9F can be equal to the initial reciprocal number CDN dec=159. In this case, counter 24 can count down from 159, and address register 25 can be configured to obtain the word line address stored at start act_159 between update cycles CBR+2 and CBR+3, which is the word line address (WL) of 1235. Accordingly, in the subsequent update cycle CBR+3, the target word line address Add is... LRH It will also be 1235. That is to say, in the update cycle CBR+3, the word line address that is adjacent to 1235 can be protected (for example, the word line address of 1234 or 1236).

[0137] In update cycle CBR+3, update character line address Add CBR It can be 1ABF, column hammer target character line address Add LRH It can be 1235. The word line address WL of hexadecimal 1ABF can be equivalent to decimal 6847, and is equivalent to 0001101010111111.

[0138] Responding to the update character line address Add CBR The last two bits are BF and the column hammer target word line address is Add. LRH If the last two bits are 35, then the initial reciprocal number in the update cycle CBR+3 is CDN. hex It can be hexadecimal 8A. In some embodiments, the initial countdown number is CDN. hex =8A can be equal to the initial reciprocal number CDN dec =138. In this case, counter 24 can count backwards from 138, and address register 25 can be configured to obtain the word line address accessed at start act_138 between update cycles CBR+3 and CBR+4 (see...). Figure 4D ).

[0139] Figure 4D It is an indication Figure 4D This illustrates, in some embodiments of the present disclosure, the character line addresses accessed along the timeline between update cycles CBR+3 and CBR+4, and the update character line address Add in each update cycle. CBR , Column hammer target character line address Add LRH And the initial reciprocal number CDN.

[0140] Please refer to Figure 4DThe address WL for character line 1235 is stored at the start of act_1. The address WL for character line 0021 is stored at the start of act_2. The address WL for character line 1235 is stored at the start of act_3. The address WL for character line 1235 is stored at the start of act_137. The address WL for character line 0021 is stored at the start of act_138. The address WL for character line 1235 is stored at the start of act_N-1. The address WL for character line 0021 is stored at the start of act_N. In other words, only the address lines for character lines 1235 and 0021 are stored.

[0141] In update cycle CBR+3, the update character line address AddCBR can be 1ABF, and the column hammer target character line address Add... LRH It could be 1235. For example... Figure 4C As shown, in response to the update character line address Add CBR The last two bits are BF and the column hammer target character line address is Add. LRH The last two bits are 35, and the initial reciprocal number in the update cycle CBR+3 CDN hex It can be hexadecimal 8A. In some embodiments, the initial countdown number is CDN. hex =8A can be equal to the initial reciprocal number CDN dec =138. In this case, counter 24 can count down from 138, and address register 25 can be configured to obtain the word line address stored at start act_138 between update cycles CBR+3 and CBR+4, which is the word line address (WL) of 0021. Accordingly, in the subsequent update cycle CBR+4, the target word line address Add is... LRH It will also be 0021. That is to say, during the update cycle CBR+4, the word line address that is adjacent to 0021 (such as the word line address of 0020 or 0022) can be protected.

[0142] In update cycle CBR+4, update character line address Add CBR It can be 1AC0, column hammer target character line address Add LRH It can be 0021. The word line address WL of hexadecimal 1AC0 can be equivalent to decimal 6848, and is equivalent to 0001101011000000.

[0143] For update cycle CBR+4, in response to update character line address Add CBR The last two bits are C0, and the column hammer target character line address is Add. LRHIf the last two digits are 21, then the first number 23A can be hexadecimal E1, equivalent to decimal 225, or binary 11100001. In this case, the first number 23A is greater than the first predetermined number (170), so the first number 23A will be modified by the number adjuster 26 to the modified first number 23B. For example, the number adjuster 26 can be configured to reset the most significant bit (msb) of the first number 23A in binary mode. Therefore, the modified first number 23B can be 01100001, equivalent to decimal 197, or hexadecimal 61.

[0144] Therefore, in the update cycle CBR+4, the initial reciprocal number CDN hex It can be hexadecimal 61 (CDN) dec =97). In this case, counter 24 can count down from 97, and address register 25 can be configured to obtain the word line address (not shown) accessed at start act_97 between update cycles CBR+4 and CBR+5.

[0145] Please refer to Figures 4A to 4D The address of the character line to be protected can be randomly selected from those character lines that are valid during the two update cycles. Character lines are selected from those initiated between update cycles. In this case, the selection pool includes character lines initiated between update cycles (i.e., character line addresses that are 0021 and 1235).

[0146] Figure 5 This is a flowchart illustrating a method 5 for protecting a memory element according to some embodiments of the present disclosure. In some embodiments, the protection method 5 is used to protect word lines contained in a memory element. In some embodiments, a memory element may include multiple word lines.

[0147] In step 51, a first word line and a first protected word line among a plurality of word lines can be updated in response to an update signal during a first update cycle, wherein the first protected word line is adjacent to the first access word line. In some embodiments, the controller of the memory element (e.g., Figure 2 The controller 22) can update one or more character lines in each update cycle in response to an update signal. In some embodiments, in the first update cycle (e.g., Figure 4C In the update cycle CBR+2, the controller can be configured to update a normal word line (e.g., the word line address of 1ABE) and a high-risk word line (e.g., the word line address of 0020 or 0022, adjacent to Add) according to a predetermined update pattern. LRH =0021). In some embodiments, step 51 may be performed by Figure 2 The controller 22 executes the commands.

[0148] In step 52, a first number can be generated by a random number generator based on an address of the first word line and an address of the first access word line. In some embodiments, the random number generator (e.g., Figure 2 The random number generator 23) can be configured to generate a random number based on a portion of the address of the first word line and a portion of the address of the first access word line. In some embodiments, step 52 can be performed by... Figure 2 The random number generator 23 in the middle is executed.

[0149] In step 53, a counter may count down from the first number in response to the update signal. In some embodiments, the counter may be configured to start counting in response to the update signal. In some embodiments, each countdown is triggered by an access signal indicating an access to a character line. In some embodiments, step 53 may be... Figure 2 The counter 24 shown is executed.

[0150] In step 54, when the counter counts to zero, a controller can obtain an address of a second access word line that is being accessed. In some embodiments, when the counter counts down to zero, the address of the second access word line can be obtained (e.g., as shown in the image). Figure 4C As shown, in the startup act_159, the word line address is 1235 and it is stored in an address register (e.g., as shown). Figure 2 In the address register 25 shown. The controller (e.g., Figure 2 The controller 22) can be configured to access the address register and obtain the address of the second access word line. In some embodiments, step 54 can be performed by the controller 22 in a configuration with / without having Figure 2 The execution is performed in the case of address register 25 shown.

[0151] In step 55, a second protected character line may be protected during a second update cycle, wherein the second protected character line is adjacent to the second access character line. In some embodiments, the second protected character line may be updated during the second update cycle (e.g., the character line address of 1234 or 1236 may be updated during update cycle CBR+3, such as...). Figure 4C (as shown). In some embodiments, step 55 may be performed by... Figure 2 The controller 22 executes the commands.

[0152] To achieve a chain hammer effect, a malicious operator often accesses one or more target character lines at a high frequency. This frequent access to the target character line leads to a chain hammer effect on adjacent character lines. In other words, under the chain hammer effect, even if nearby character lines are not accessed, their contents may be altered due to leaked charge.

[0153] This disclosure provides a memory element capable of identifying potentially vulnerable target word lines and protecting word lines adjacent to these target word lines. A random number generator generates a random number as the initial value of a counter; when the counter decrements to zero, the address of the accessed target word line is obtained. Furthermore, to prevent the random number generated by the random number generator from exceeding the maximum number of starts between update cycles, a digital adjuster modifies the random number to a range from zero to a predetermined number (i.e., the maximum number of starts between update cycles). Therefore, word lines adjacent to frequently accessed target word lines can be updated to maintain their content.

[0154] One embodiment of this disclosure provides a memory element. The memory element structure includes a plurality of word lines; and a controller configured to update a first word line and a first protected word line among the plurality of word lines during a first update cycle in response to an update signal, wherein the first protected word line is adjacent to the first access word line. The memory element further includes a random number generator configured to receive an address of the first word line and an address of the first access word line to generate a first number; and a counter electrically coupled to the random number generator. The counter is configured to receive the first number as an initial value for the counter and is configured to be enabled in response to the update signal. The controller is also configured to obtain an address of a second access word line being accessed when the counter decrements to zero, and to update a second protected word line during a second update cycle, wherein the second protected word line is adjacent to the second access word line.

[0155] Another embodiment of this disclosure provides a memory element. The memory element includes a plurality of word lines; a controller configured to update a first word line and adjacent word lines of a first access word line in the plurality of word lines during a first update cycle in response to an update signal; a random number generator configured to generate a first number based on the address of the first word line and the address of the first access word line; a counter electrically coupled to the random number generator, wherein the counter is configured to receive the first number as an initial value of the counter and to begin counting down in response to the update signal; and an address register electrically coupled to the counter, wherein the address register is configured to store an address of a second access word line that is valid when the counter counts down to zero. The controller is also configured to access the address register to obtain the address of the second access word line and to protect adjacent word lines of the second access word line during a second update cycle.

[0156] Another embodiment of this disclosure provides a method for protecting a memory element, wherein the semiconductor element includes a plurality of word lines. The protection method updates a first word line and a first protected word line among the plurality of word lines during a first update cycle in response to an update signal, wherein the first protected word line is adjacent to the first access word line; generates a first number by a random number generator based on an address of the first word line and an address of the first access word line; counts down from the first number by a counter in response to the update signal; when the counter reaches zero, obtains an address of a second access word line being accessed by a controller; and protects a second protected word line during a second update cycle, wherein the second protected word line is adjacent to the second access word line.

[0157] Embodiments of this disclosure provide a memory element having a protection circuit for selecting and protecting a vulnerable word line. Specifically, the memory protection circuit can protect word lines (memory cells) from column hammers. To trigger a column hammer, a malicious operator rapidly activates the same memory column, potentially causing charge leakage on adjacent unactivated memory columns. This protection circuit provides a random number generator and a counter to randomly select and protect potentially vulnerable memory columns. The counter can be configured to count down from a random number generated by the random number generator. When the counter reaches zero, an address of the activated memory column can be obtained. In other words, the memory column is selected from memory columns activated between multiple update cycles. In this case, the selection pool includes memory columns activated between multiple update cycles. The random number generator can generate a random number based on the address of the last updated word line and the address of the last accessed word line (the selected potentially vulnerable word line), thereby increasing the unpredictability of the random number. Additionally, to prevent the random number generated by the random number generator from exceeding the maximum number of activations between update cycles, the number adjuster modifies the random number to a range from zero to a predetermined number (i.e., the maximum number of activations between update cycles). Since memory columns adjacent to the activated memory columns are more likely to be affected by column hammering, they will be protected in subsequent update cycles.

[0158] Typically, the number of times a column hammer is triggered cannot be completed within two update cycles. For example, a memory element with 8192 rows may have approximately 170 activations between multiple update cycles, and the number of column hammer activations in the same column could be 10,000 or more. Therefore, protecting additional memory columns that may be subject to column hammers in each update cycle can eliminate the column hammer problem. Furthermore, the memory element can include a digital adjuster to determine whether the random number used to select a column in the memory exceeds the maximum number of activations between update cycles (i.e., 170 in this case), and then reduce the random number to between 0 and 170. This improves the security and performance of the memory element.

[0159] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0160] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A memory element, comprising: Multiple character lines; A controller is configured to update a first character line and a first protected character line among the plurality of character lines in response to an update signal during a first update cycle, wherein the first protected character line is adjacent to a first access character line. A random number generator is configured to receive an address of the first word line and an address of the first access word line to generate a first number; as well as A counter, electrically coupled to the random number generator, wherein the counter is configured to receive the first number as an initial value of the counter, and is configured to be turned on in response to the update signal; The controller is also configured to obtain an address of a second access word line being accessed when the counter counts down to zero, and to update a second protected word line during a second update cycle, wherein the second protected word line is adjacent to the second access word line.

2. The memory element of claim 1, wherein the first number is a positive integer.

3. The memory element of claim 1, wherein the first number is represented by a binary sequence of more than 2 bits.

4. The memory element of claim 3, wherein the first number is represented by an 8-bit binary sequence.

5. The memory element of claim 1, wherein the first number is less than a first predetermined number, wherein the first predetermined number is associated with a first time period and a second time period, the first time period being used to access a word line, and the second time period being between the first update cycle and the second update cycle.

6. The memory element of claim 5 further includes a digital adjuster configured to reset a most significant bit of the first number when the first number is greater than the first predetermined number.

7. The memory element of claim 1, wherein the random number generator includes an XOR gate.

8. The memory element of claim 1, wherein the address of the first word line and the address of the first access word line are both represented by a 4-bit hexadecimal sequence.

9. The memory element of claim 8, wherein the random number generator is configured to generate the first number based on a first portion of the address of the first word line and a first portion of the address of the first access word line.

10. The memory element of claim 1, further comprising an address register electrically connected to the counter, wherein the address register is configured to acquire and store the address of the first access word line accessed when the counter decrements to zero.

11. The memory element of claim 1, wherein the controller is also configured to update a second word line during the second update cycle.

12. A memory element, comprising: Multiple character lines; A controller is configured to update a first character line and an adjacent character line of a first access character line among the plurality of character lines during a first update cycle in response to an update signal; A random number generator is configured to generate a first number based on an address of the first word line and the address of the first access word line; A counter, electrically coupled to the random number generator, wherein the counter is configured to receive the first number as an initial value of the counter and to start counting down in response to the update signal; as well as An address register electrically connected to the counter, wherein the address register is configured to store an address of a second access word line that is valid when the counter counts down to zero; The controller is also configured to access the address register to obtain the address of the second access word line and to protect the adjacent bit lines of the second access word line during a second update cycle.

13. The memory element of claim 12, wherein the first number is a positive integer.

14. The memory element of claim 12, wherein the first number is represented by a binary sequence of more than 2 bits.

15. The memory element of claim 14, wherein the first number is represented by an 8-bit binary sequence.

16. The memory element of claim 12, wherein the first number is less than a first predetermined number, wherein the first predetermined number is associated with a first time period and a second time period, the first time period being used to access a word line, and the second time period being between the first update cycle and the second update cycle.

17. The memory element of claim 16, further comprising a digital adjuster configured to reset a most significant bit of the first number when the first number is greater than the first predetermined number.

18. The memory element of claim 12, wherein the random number generator includes an XOR gate.

19. The memory element of claim 12, wherein the address of the first word line and the address of the first access word line are both represented by a 4-bit hexadecimal sequence.

20. The memory element of claim 19, wherein the random number generator is configured to generate the first number based on a first portion of the address of the first word line and a first portion of the address of the first access word line.

Images