Adaptation of DRAM command / address interface

Abstract

The invention relates to adaptation of a DRAM command / address interface. A decision counter circuit is used in an adaptive circuit to apply digital averaging to an input signal to obtain an adaptive setting of a circuit parameter of a memory chip of a memory device during operation. Individual adaptive settings of the parameters (e.g., impedance, capacitance, equalization parameters) during operation may be obtained for each of the memory chips in the memory device. The adaptation enables equalization adjustment across temperature and voltage drift.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of priority to U.S. Provisional Application No. 63 / 601,014, filed Nov. 20, 2023, the entire content of which is incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to the field of semiconductor memory devices. More specifically, embodiments of this disclosure relate to the adaptation of the command / address interface of a memory device. Background Art

[0004] The operating speed of memory devices, including the data rate of memory devices, has been increasing over time. As a side effect of the increasing speed of memory devices, data errors due to distortion may increase. For example, inter-symbol interference between the transmitted data may occur because the previously received data affects the currently received data (e.g., the previously received data affects and interferes with the subsequently received data). One way to correct this interference is by using a decision feedback equalizer (DFE) circuit or a continuous time linear equalizer (CTLE) circuit, which can be programmed to cancel (i.e., undo, mitigate, or counteract) the effect of the channel on the transmitted data. However, a memory device may include multiple memory chips, and the signals received at each memory chip may be different due to the way the reflections of the signals queue at the corresponding inputs of each memory chip and / or the dynamic changes of the signals during operation (e.g., across process, voltage, and temperature (PVT) drifts). Summary of the Invention

[0005] In one aspect, this disclosure relates to an apparatus that includes: a receiver configured to receive a signal and produce an output of the signal; and an adaptation circuit configured to receive the signal and obtain an adaptive value of a parameter based on the signal and the output of the signal.

[0006] In another aspect, this disclosure relates to a method that includes: receiving a signal by a receiver; producing an output of the signal by the receiver; and producing an adaptive value of a parameter by an adaptation circuit based on the signal and the output of the signal, wherein the adaptation circuit is configured to: produce an error code based on a first comparison between the signal and the parameter; produce a decision bit based on a second comparison between the error code and the output of the signal from the receiver; use the decision bit to produce a count; and produce an output indicating an address or decrement of the parameter based on the count.

[0007] On the other hand, the present disclosure relates to an adaptive circuit, comprising: an error circuit configured to generate an error code based on a first comparison between a signal and a parameter, wherein a receiver is configured to receive the signal and generate an output of the signal; a decision circuit configured to generate a decision bit based on a second comparison between the error code and the output of the signal from the receiver; and a decision counter configured to use the decision bit to generate a count and generate an output indicating an increase or decrease of the parameter based on the count. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Aspects of the present disclosure may be better understood after reading the following detailed description and with reference to the drawings, in which:

[0009] Figure 1 is a simplified block diagram illustrating certain features of a memory device according to an embodiment of the present disclosure;

[0010] Figure 2 is a simplified block diagram of a portion of a command / address (CA) input circuit of a memory device according to an embodiment of the present disclosure; Figure 1 of

[0011] Figure 3 illustrates an embodiment of a portion of a CA input circuit according to an embodiment of the present disclosure; Figure 2 of

[0012] Figure 4 illustrates an embodiment of a bit counter block according to an embodiment of the present disclosure; Figure 3 of

[0013] Figure 5 illustrates another embodiment of a portion of a CA input circuit according to an embodiment of the present disclosure; Figure 2 of

[0014] Figure 6 is a flowchart illustrating a method for implementing an adaptive circuit to determine an adaptive value of an input voltage level according to an embodiment of the present disclosure; and

[0015] Figure 7 is a flowchart illustrating a method for implementing an adaptive circuit to determine an adaptive value of an equalization parameter according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] One or more specific embodiments will be described below. To provide a concise description of these embodiments, all features of the actual implementation are not described in this specification. It should be understood that in the development of any such actual implementation (such as in any engineering or design project), many implementation-specific decisions must be made to achieve the specific goals of the developer, such as meeting system-related and business-related constraints, which may vary with the implementation. In addition, it should be understood that this development effort may be complex and time-consuming, but will still be a routine design, fabrication, and manufacturing task for those of ordinary skill in the art who benefit from this disclosure.

[0017] Memory devices exchange data and store data in banks. Each bank may include a plurality of memory cells in which data is stored. A group of banks may be provided on a memory chip, and the memory device may include a plurality of memory chips. Due to the way in which reflections of signals queue at the corresponding inputs of each memory chip and / or the signals may be different at each memory chip during operation (e.g., dynamic changes across process, voltage, and temperature (PVT)), in some embodiments, the memory chips in the memory device may require different parameter settings.

[0018] To at least partially improve the correction of signal distortion, it may be necessary to perform individual adaptive settings of parameters (e.g., impedance, capacitance, equalization parameters) during operation for each of the memory chips in the memory device. As discussed below, this adaptation may take into account memory environment-specific complexities such as single-ended signaling, burst data transfer (including associated fast power-on and / or power-off), relatively poor transistor performance, bidirectional pins, PVT drift, and / or other conditions. The adaptation may be performed during operation of the memory device and may not add training time during startup.

[0019] The present disclosure herein provides systems and methods for performing adaptation during operation to obtain adaptive settings of circuit parameters of memory chips of a memory device. A decision counter circuit may be used in the adaptation circuit to apply digital averaging to an input signal to obtain an adaptive setting. Specifically, the high-level input voltage (V IH )(e.g., compared to VrCA) and the low-level input voltage (V IL )(e.g., compared to VrCA) of the input at the signal pins (e.g., CA<13:0>) of the memory chip may be determined by using a digital averaging method. V IH and V ILThe adaptive values can be used in conjunction with digital averaging methods to determine the adaptive equalization (EQ) parameters (e.g., resistors, capacitors, tap bias coefficients) for decision feedback equalization (DFE) circuits (e.g., single-tap DFE, multi-tap DFE) or continuous-time linear equalization (CTLE) circuits that mitigate signal distortion in memory chips. For example, an adaptive value for a tap bias coefficient can be determined for a DFE circuit, and adaptive values for resistors and capacitors can be determined for a CTLE circuit.

[0020] Referring now to the figures, Figure 1 is a simplified block diagram illustrating specific features of the memory device 10. Specifically, Figure 1 the block diagram is a functional block diagram illustrating specific functionality of the memory device 10. According to one embodiment, the memory device 10 can be a double data rate type five synchronous dynamic random access memory (DDR5 SDRAM) device. Compared to previous generations of DDR SDRAM, the various features of DDR5 SDRAM allow for reduced power consumption, more bandwidth, and more storage capacity.

[0021] The memory device 10 can include a plurality of banks 12. For example, the banks 12 can be DDR5 SDRAM banks. The banks 12 can be provided on one or more chips (e.g., SDRAM chips) arranged on a dual in-line memory module (DIMM). As will be appreciated, each DIMM can include several SDRAM memory chips (e.g., x8 or x16 memory chips). Each SDRAM memory chip can include one or more banks 12. For DDR5, the banks 12 can be further arranged to form bank groups. For example, for an 8-gigabit (Gb) DDR5 SDRAM, the memory chip can include 16 banks 12 arranged in 8 bank groups, with each bank group including 2 banks. For example, for a 16GB DDR5 SDRAM, the memory chip can include 32 banks 12 arranged in 8 bank groups, where each bank group includes 4 banks. Depending on the application and design of the overall system, various other configurations, organizations, and sizes of the banks 12 on the memory device 10 can be utilized.

[0022] The memory device 10 can include a command interface 14 and an input / output (I / O) interface 16 configured to exchange (e.g., receive and transmit) signals with an external device. The command interface 14 is configured to provide several signals (e.g., signal 15) from an external device (not shown) (e.g., a processor or a controller). The processor or controller can provide various signals 15 to the memory device 10 to facilitate the transfer and reception of data to be written to or read from the memory device 10.

[0023] As will be appreciated, command interface 14 may include several circuits (such as clock input circuit 18 and command / address input circuit 20) to ensure proper handling of signal 15, for example. Command interface 14 may receive one or more clock signals from an external device. Generally, double data rate (DDR) memories utilize a differential pair of system clock signals, referred to herein as the true clock signal (Clk_t) and the complementary clock signal (Clk_c). The positive clock edge of DDR refers to the point where the rising true clock signal Clk_t crosses the falling complementary clock signal Clk_c, while the negative clock edge indicates the transition of the falling true clock signal Clk_t and the rising of the complementary clock signal Clk_c. Commands (such as read commands, write commands, etc.) are typically keyed in on the positive edge of the clock signal and data is transmitted or received on both the positive and negative clock edges.

[0024] Clock input circuit 18 receives the true clock signal (Clk_t) and the complementary clock signal (Clk_c) and generates an internal clock signal CLK. The internal clock signal CLK is supplied to an internal clock generator 30, such as a delay locked loop (DLL) circuit. Internal clock generator 30 generates a phase-controlled internal clock signal LCLK based on the received internal clock signal CLK. The phase-controlled internal clock signal LCLK is supplied to, for example, I / O interface 16 and is used as a timing signal for determining the output timing of read data.

[0025] The internal clock signal CLK may also be provided to various other components within memory device 10 and may be used to generate various additional internal clock signals. For example, the internal clock signal CLK may be provided to command decoder 32. Command decoder 32 may receive command signals from command bus 34 and may decode the command signals to provide various internal commands. For example, command decoder 32 may supply command signals to internal clock generator 30 via bus 36 to coordinate the generation of the phase-controlled internal clock signal LCLK. Command decoder 32 may also supply command signals to I / O interface 16 via bus 37 to facilitate the reception and transmission of I / O signals. The phase-controlled internal clock signal LCLK may be used, for example, to time the data through I / O interface 16.

[0026] In addition, the command decoder 32 can decode commands received from the command bus 34 (such as read commands, write commands, mode register set commands, activation commands, etc.) and provide access to a specific bank 12 corresponding to the command via the bus path 40. As will be appreciated, the memory device 10 can include various other decoders (such as row decoders and column decoders) to facilitate access to the bank 12. In one embodiment, each bank 12 includes a bank control block 22 that provides the necessary decoding (such as row decoders and column decoders) as well as other features (such as timing control and data control) to facilitate execution of commands to and from the bank 12. A group of banks 12 can be included in the memory chip 23, and the memory device 10 can include one or more memory chips.

[0027] The memory device 10 performs operations such as read commands and write commands based on command / address signals received from an external device (such as a processor). In one embodiment, the command / address bus can be a 14-bit bus that accommodates command / address signals (CA<13:0>). The command / address signals are time-multiplexed into the command interface 14 using clock signals (Clk_t and Clk_c). The command / address input circuit 20 in the command interface 14 can be configured to, for example, receive and transmit commands to provide access to the bank 12 through the command decoder 32. Additionally, the command interface 14 can receive a chip select signal (CS_n). The chip select signal CS_n enables the memory device 10 to process commands on the incoming command / address signals CA<13:0> for the memory chip selected by the chip select signal CS_n. Thus, access to a specific bank 12 within the memory device 10 is facilitated by the information encoded on the chip select signal CS_n and the command / address signals CA<13:0>.

[0028] Additionally, the command interface 14 can be configured to receive several other command signals. For example, an on-die termination command / address (CA_ODT) signal can be provided to facilitate proper impedance matching within the memory device 10. A reset command (RESET_n) can be used to, for example, reset the command interface 14, status registers, state machines, and the like during power-up. The command interface 14 can also receive a command / address inversion (CAI) signal, which can be provided to invert the state of the command / address signals CA<13:0> on the command / address bus depending on the command / address routing used for the specific memory device 10. A mirror (MIR) signal can also be provided to facilitate the mirroring function. Based on the configuration of multiple memory devices in a particular application, the MIR signal can be used to multiplex signals such that they can be swapped for certain routings of signals to the memory device 10. Various signals can also be provided to facilitate testing of the memory device 10, such as a test enable (TEN) signal. For example, the TEN signal can be used to place the memory device 10 in a test mode for connectivity testing.

[0029] The command interface 14 can also be used to provide an alert signal (ALERT_n) to the system processor or controller for certain detectable errors. For example, if a cyclic redundancy check (CRC) error is detected, the alert signal (ALERT_n) can be transmitted from the memory device 10. Other alert signals can also be generated. In addition, the buses and pins used to transmit the alert signal (ALERT_n) from the memory device 10 can be used as input pins during certain operations, such as the connectivity test mode performed using the TEN signal, as described above.

[0030] By transmitting and receiving data signals 44 through the I / O interface 16, data can be sent to and from the memory device 10 using the commands and timing signals discussed above. More specifically, data can be sent to or retrieved from the bank 12 through the data bus 46, which includes a plurality of bidirectional data buses. Data I / O signals, commonly referred to as DQ signals, are typically transmitted and received in one or more bidirectional data buses. For some memory devices, such as DDR5 SDRAM memory devices, the I / O signals can be divided into high and low bytes. For example, for a x16 memory device, the I / O signals can be divided into high and low I / O signals (e.g., DQ<15:8> and DQ<7:0>) corresponding to the high and low bytes of the data signal, for example.

[0031] To allow for higher data rates within the memory device 10, some memory devices (such as DDR memory devices) can utilize a data strobe signal, commonly referred to as the DQS signal. The DQS signal is driven by an external processor or controller that transmits data (e.g., for a write command) or by the memory device 10 (e.g., for a read command). For a read command, the DQS signal is actually an additional data output (DQ) signal with a predetermined pattern. For a write command, the DQS signal serves as a clock signal to capture the corresponding input data. Like the clock signals (Clk_t and Clk_c), the data strobe (DQS) signal can be provided as a differential pair of data strobe signals (DQS_t and DQS_c) to provide differential pair signaling during reads and writes. For some memory devices, such as DDR5 SDRAM memory devices, the differential pair of DQS signals can be divided into high and low data strobe signals (e.g., UDQS_t and UDQS_c; LDQS_t and LDQS_c) corresponding to the high and low bytes of the data transmitted to or from the memory device 10, for example.

[0032] An impedance (ZQ) calibration signal can also be provided to the memory device 10 through the I / O interface 16. The ZQ calibration signal can be provided to a reference pin and can be used to tune the output driver and on-die termination (ODT) values by adjusting the pull-up and pull-down resistors of the memory device 10 over changes in process, voltage, and temperature (PVT) values. Since PVT characteristics may affect the ZQ resistor value, the ZQ calibration signal can be provided to the ZQ reference pin for adjusting the resistor to calibrate the input impedance to a known value. As will be appreciated, a precision resistor is typically coupled between the ZQ pin on the memory device 10 and GND / VSS external to the memory device 10. This resistor serves as a reference for adjusting the drive strength of the internal ODT and the IO pins.

[0033] Additionally, a loopback signal (LOOPBACK) can be provided to the memory device 10 through the I / O interface 16. The loopback signal can be used during a test or debug phase to set the memory device 10 to a mode in which signals loop back through the memory device 10 through the same pins. For example, the loopback signal can be used to set the memory device 10 to test the data output of the memory device 10. The loopback can include data and strobes or may include only the data pins. This is typically desirable for monitoring the data captured by the memory device 10 at the I / O interface 16.

[0034] As will be appreciated, various other components, such as a power supply circuit (for receiving external VDD and VSS signals), a mode register (for defining various modes of programmable operation and configuration), a read / write amplifier (for amplifying signals during read / write operations), a temperature sensor (for sensing the temperature of the memory device 10), etc. can also be incorporated into the memory device 10. Therefore, it should be understood that Figure 1 the block diagram of

[0035] In some embodiments, the memory device 10 may be disposed within (physically integrated into or otherwise connected to) a host device, or otherwise coupled to a host device. The host device may include any one of a desktop computer, a laptop computer, a pager, a cellular phone, a personal organizer, a portable audio player, a control circuit, a camera, etc. The host device may also be a network node, such as a router, a server, or a client (e.g., one of the computer types previously described). The host device may be other kinds of electronic devices, such as a copier, a scanner, a printer, a gaming machine, a television, a set-top video distribution or recording system, a cable television box, a personal digital media player, a factory automation system, an automotive computer system, or a medical device. (The terms used to describe these various examples of systems, like many other terms used herein, may share some referents and should not, therefore, be construed narrowly because of the other items listed.)

[0036] Accordingly, the host device may be a processor-based device that may include a processor, such as a microprocessor, that controls system functions and the processing of requests within the host. Additionally, any host processor may include multiple processors that share system control. The host processor may be directly or indirectly coupled to additional system elements of the host such that the host processor controls the operation of the host by executing instructions that may be stored within or external to the host.

[0037] As discussed above, data can be written to and read from the memory device 10 by a host, for example, such that the memory device 10 operates as a volatile memory, such as a double data rate DRAM (e.g., DDR5 SDRAM). In some embodiments, the host may also include a separate non-volatile memory, such as a read-only memory (ROM), PC-RAM, silicon-oxide-nitride-oxide-silicon (SONOS) memory, metal-oxide-nitride-oxide-silicon (MONOS) memory, a polysilicon floating gate-based memory, and / or other types of flash memories of various architectures (e.g., NAND memory, NOR memory, etc.), as well as other types of memory devices (e.g., storage devices), such as a solid state drive (SSD), a multimedia card (MMC), a secure digital (SD) card, a compact flash (CF) card, or any other suitable device. Additionally, it should be understood that the host may include one or more external interfaces, such as a universal serial bus (USB), a peripheral component interconnect (PCI), PCI Express (PCI-E), a small computer system interface (SCSI), IEEE 1394 (FireWire), or any other suitable interface, as well as one or more input devices to allow a user to input data into the host, such as buttons, switch elements, a keyboard, a light pen, a stylus, a mouse, and / or a voice recognition system. The host may also optionally include an output device, such as a display coupled to the processor, and a network interface device for interfacing with a network (e.g., the Internet), such as a network interface card (NIC). As will be appreciated, depending on the application of the host, the host may include many other components.

[0038] The host is operable to transfer data to the memory device 10 for storage and to read data from the memory device 10 to perform various operations at the host. Thus, to facilitate these data transfers, in some embodiments, the I / O interface 16 may include a data transceiver 48 that operates to receive DQ signals from and transmit DQ signals to the I / O interface 16.

[0039] As previously mentioned, in some embodiments, the memory device 10 may include more than one memory chip, and the command interface 14 may include several signal pins (e.g., CS_n, CA<13:0>, Clk_t / Clk_c, RESET_n) to receive signals 15 for the memory chips of the memory device 10. The chip select signal (CS_n) may be used to enable the memory device 10 to process commands on the incoming command / address signals CA<13:0> for the memory chip selected by the chip select signal CS_n. However, the signals received at each memory chip may be affected by reflections of the transmission lines, and the signals may be affected differently due to the way the signals queue at the corresponding inputs of each memory chip and / or the dynamic changes of the signals during operation. Therefore, it may be necessary to perform individual adaptive settings of parameters (e.g., impedance, capacitance, equalization parameters) for each of the memory chips in the memory device 10 during operation.

[0040] In some embodiments, an adaptive circuit may be used to obtain adaptive settings of parameters of the memory chips of the memory device 10 during operation of the memory device 10. A decision counter circuit may be used in the adaptive circuit to apply digital averaging to the signals to obtain the adaptive settings, as described in more detail herein. For example, the high-level input voltage (V IH )(e.g., compared to VrCA) and the low-level input voltage (V IL )(e.g., compared to VrCA) of the inputs at the signal pins (e.g., CA<13:0>) may be determined by using a digital averaging method. The adaptive values of V IH and V IL may be used together with the digital averaging method to determine the adaptive equalization (EQ) parameters (e.g., resistance, capacitance, tap bias coefficient) of a decision feedback equalization (DFE) circuit or a continuous time linear equalization (CTLE) circuit for mitigating signal distortion of the memory chip.

[0041] In some embodiments, each of the signal pins (e.g., CS_n, CA<13:0>, Clk_t / Clk_c) of the command interface 14 may be individually adapted because they may be connected to different numbers of memory chips and / or operate at different frequencies. In these embodiments, each of the signal pins of the command interface 14 may have a unique adaptive circuit. In some embodiments, for the purpose of energy saving or area efficiency (AE), a common adaptive circuitry system may be shared within a group of signal pins (e.g., CS_n, CA<13:0>, Clk_t / Clk_c) or within all the signal pins of the command interface 14.

[0042] Figure 2Describe an embodiment of a portion of a command / address input circuit 20 of a memory device 10 that includes an adaptive circuit. As illustrated, a command / address (CA) input circuit 20 can receive a CA signal 100 via a channel 102 (e.g., a connection, transmission line, and / or conductive material). An output 104 of the channel 102 can be transmitted to an input 106 of a CA receiver 108. A reference voltage VrCA can be applied to an input 110 of the CA receiver 108. A chip select (CS) gating enable signal 112 can be used to enable the CA receiver 108. A CS gating enable signal 114 can be used to enable an adaptive circuit 116. The adaptive circuit 116 can include several circuits to obtain an adaptive setting of the CA input circuit 20 during operation of the memory device 10. In some embodiments, the CS gating enable signal 112 and the CS gating enable signal 114 can be the same signal. In some embodiments, a CS gating enable signal (e.g., CS gating enable signals 112 and 114) can be used to routinely or on demand (e.g., when it is determined that the distortion of a signal is greater than a threshold) enable a corresponding receiver (e.g., CA receiver 108) and an adaptive circuit (e.g., adaptive circuit 116). In some embodiments, when there is data on the command / address bus, a CS gating enable signal (e.g., CS gating enable signals 112 and 114) can be used to enable a corresponding receiver (e.g., CA receiver 108) and an adaptive circuit (e.g., adaptive circuit 116) at any time. In some embodiments, a CS gating enable signal (e.g., CS gating enable signals 112 and 114) can utilize a CS_n signal and enable a corresponding receiver (e.g., CA receiver 108) and an adaptive circuit (e.g., adaptive circuit 116) of a selected memory chip. For simplicity, in all embodiments described below, the CS gating enable signal 112 and the CS gating enable signal 114 can be used for receivers and adaptive circuits (e.g., error latches, bit counters) and may not be shown in the figures (e.g., Figure 3 and Figure 5 ). The output 104 of the channel 102 can also be transmitted to the adaptive circuit 116 via a path 118. Although a CA receiver is used in the embodiment illustrated in Figure 2 , in some embodiments, receivers for other signals (e.g., CS, CLK_t / CLK_c, CAI, MIR, TEN, CA_ODT, RESET, ALERT) can be used with an adaptive circuit system to obtain corresponding adaptive settings.

[0043] Figure 3 is a block diagram illustrating an embodiment of a portion of a CA input circuit 20 that has an adaptive circuit 119 that can be used to obtain an adaptive setting. In Figure 3Among them, an optional pre - amplifier (pre - amp) 105 can be placed in front of the CA receiver 108 to obtain an amplified output 104. Using the optional pre - amplifier 105 can improve the amplitude of the CA signal from the output 104 and avoid an increase in the pad capacitance. In some embodiments, the pre - amplifier 105 may not be used for energy saving and / or AE. The output 104 together with the reference voltage VrCA can be input into the optional pre - amplifier 105, and the amplified output 104 from the optional pre - amplifier 105 can be transmitted to the input 106 of the CA receiver 108. The CA receiver 108 may include a comparator to receive the CA signal of the output 104 (or the amplified output 104 from the optional pre - amplifier 105) through the input 106. The comparator 120 can receive the reference voltage VrCA through the input 110. The comparator 120 may have an output 122 to transmit a decision code (d k ) based on the values of the input 106 and the reference voltage VrCA. For example, when the input 106 has a value greater than the reference voltage VrCA, the decision code d k may have a value of "1"; and when the input 106 has a value less than the reference voltage VrCA, the decision code d k may have a value of "0".

[0044] The CA signal of the output 104 (or the amplified output 104 from the optional pre - amplifier 105) can also be transmitted to the adaptive circuit 119 through the path 118. The adaptive circuit 119 may include an error circuit 130 (e.g., an error latch), which may include a comparator 132. The path 118 can be coupled to the input 134 of the comparator 132, and a programmable reference voltage level ("dLev") can be applied to the input 136 of the comparator 132. The comparator 132 can transmit an error code (e k ) via the path 138, and the error code is generated based on the value of the input 134 and the value of dLev at the input 136. For example, when the input 134 has a value greater than the value of dLev at the input 136, the error code e k may have a value of "1"; and when the input 134 has a value less than the value of dLev at the input 136, the error code e k may have a value of "0".

[0045] The adaptive circuit 119 may include a bit counter block 140 to receive the decision code d k from the CA receiver 108 via the output 122, and the bit counter block 140 may also receive the error code e k from the error circuit 130 via the path 138. The bit counter block 140 is used to perform digital averaging based on the decision code d k and the error code e k , as described in detail in Figure 4 .

[0046] Figure 4 is a block diagram illustrating an embodiment of a bit counter block 140 that can be used in an adaptive circuit 119. Error code e k and decision code d k can be input into a decision circuit 142 (e.g., an AND gate) of the bit counter block 140 to generate a decision bit (e.g., "1" or "0") of an output 144. The output 144 of the decision circuit 142 can be input into an error bit counter 146, and the error bit counter 146 can be used to count the number of decision bits. For example, the decision circuit 142 can include an AND gate, and when the decision code d k has a value of "1", the output 144 can have a value of "1" only when the error code e k has a value of "1". When the decision code d k has a value of "0", before being transmitted to the bit counter block 140, both the decision code d k and the error code e k can be inverted (e.g., by using an inverter) so that the output 144 can have a value of "1" only when the error code e k has a value of "0". When N (e.g., N = 1, 2,...) bits are counted in the error bit counter 146, the output 148 of the error bit counter 146 can have a high (e.g., "1") value.

[0047] The decision code d k can also be input into a CA bit counter 150, and the CA bit counter 150 can be used to count the total number of 2N decision codes d k transmitted to the bit counter block 140. As mentioned above, in some embodiments, when the decision code d k has a value of "0", the decision code d k can be inverted (e.g., by using an inverter) before being transmitted into the bit counter block 140. When 2N bits are counted in the CA bit counter 150, the output 152 of the CA bit counter 150 can have a high (e.g., "1") value. When 2N bits of the decision code d k are counted in the CA bit counter 150, the output 152 can be used to stop the counting in the error bit counter 146. If the error bit counter 146 is stopped before N bits are counted in the error bit counter 146, then the output 148 can have a low (e.g., "0") value. For example, when at least N bits of the 2N bits of the decision code d k transmitted to the bit counter block 140 are equal to the corresponding error code e k transmitted to the bit counter block 140When this occurs, output 148 can have a value of "1", which can be used to increment the decision. When output 148 has a value of "0", no increment decision is made. When the decision code d is received at the CA bit counter 150 k for 2N bits, the error bit counter 146 can stop counting. Since the value of output 148 can be determined based on a decision on whether the error code e k and the decision code d k are equal for at least half of the received CA bits (e.g., N out of ≥ 2N bits), the error bit count 146 is sometimes referred to as a decision counter.

[0048] Return Figure 3 , output 148 can be input into the digital logic block 160, which can be used to obtain an updated dLev digital code by incrementing or decrementing the current dLev digital code by a step size based on output 148 of the decision counter 146. The step size can be determined based on the CA input, the historical value of dLev, etc. The digital logic block 160 can include any kind of logic circuit. For example, the digital logic block 160 can include an adder / subtractor circuitry to calculate the increment / decrement decision. The output of the digital logic block 160 can be input into the dLev and equalization (EQ) parameter generator block 170, which can be used to generate updated dLev and EQ parameters based on the updated dLev digital code obtained by the digital logic block 160. The output 180 of the dLev and EQ parameter generator block 170 can include the updated dLev and EQ parameters, which can be applied to the error circuit 130 (e.g., comparator 132) and the CA receiver 108 (e.g., the CA receiver 108 can include a DFE circuit or a CTLE circuit for mitigating distortion of the CA signal).

[0049] For example, the high level (V IH ) input voltage and the low level (V IL ) input voltage of the input can be determined adaptively by using the systems and methods described herein. For example, the programmable reference voltage level dLev can be used to determine the adaptive settings of the input voltage levels V IH and V IL . In Figure 3 , the adaptive circuit 119 can be used to determine the voltage levels of V IH and V IL one by one, i.e., determining one voltage level at a time. For example, the adaptive setting of V IH (or V IL ) can be first determined by adjusting the dLev value by using the bit counter 140, the digital logic block 160, and the dLev and EQ generator 170, and then the adaptive setting of V IL (or V IH ) can be determined similarly.

[0050] In some embodiments, two error latches can be used in the error circuit of an adaptive circuit, as illustrated in Figure 5 . When two error latches are used in the error circuit of an adaptive circuit, two parameters (e.g., input voltage levels V IH and V IL ) can be determined for adaptive settings simultaneously. Figure 5 is a block diagram illustrating another embodiment of a CA input circuit 20 of an adaptive circuit 200 that can be used to simultaneously obtain adaptive settings for two parameters. The adaptive circuit 200 can have an error circuit 190 that includes two error latches. For example, the error circuit 190 can include an error latch that includes a comparator 132 using a programmable reference voltage level dLevLo, and an error latch that includes a comparator 192 using a programmable reference voltage level dLevHi.

[0051] In Figure 5 , path 118 can be coupled to input 134 of comparator 132, and the programmable reference voltage level dLevLo can be applied to input 136 of comparator 132. Comparator 132 can transmit an error code (e kLo ) via path 138, which is generated based on the value of input 134 and the value of dLevLo at input 136. For example, when input 134 has a value greater than the value of dLevLo at input 136, the error code e kLo can have a value of "1"; and when input 134 has a value less than the value of dLevLo at input 136, the error code e kLo can have a value of "0".

[0052] Additionally, path 118 can be coupled to input 194 of comparator 192, and the programmable reference voltage level dLevHi can be applied to input 196 of comparator 192. Comparator 192 can transmit an error code (e kHi ) via path 198, which is generated based on the value of input 194 and the value of dLevHi at input 196. For example, when input 194 has a value greater than the value of dLevHi at input 196, the error code e kHi can have a value of "1"; and when input 194 has a value less than the value of dLevHi at input 196, the error code e kHi can have a value of "0".

[0053] The bit counter block 140 can receive the error code e kHi from comparator 192 via path 198, and receive the error code e kLo。The bit counter block 140 can be used to perform digital averaging on the decision code d kHi and the error code e kLo based on the error code e k In some embodiments, a common error bit counter (e.g., error bit counter 146) can be used in the bit counter block 140 to perform error bit counting on different values of the decision code d k and a selection device (e.g., a multiplexer) can be used to select the error code e k to be output to the bit counter block 140 depending on the value of the decision code d kLo or the error code e kHi . For example, when the decision code d k has a value of 0, which means that the CA input at the input 106 of the CA receiver 108 is lower than the reference voltage VrCA, the error code e kLo can be output (e.g., via path 138) to the bit counter block 140 to determine an increment in the adaptive setting of dLevLo, and the bit count in the CA bit counter 150 can be incremented only when the decision code d k has a value of 0 (e.g., when the decision code d k has a value of "0", the decision code d k and the error code e kLo can be flipped (e.g., by using an inverter) before being transmitted to the bit counter block 140). When the decision code d k and the error code e kLo ) When the decision code d k has a value of 1, which means that the CA input at the input 106 of the CA receiver 108 is higher than the reference voltage VrCA, the error code e kHi can be output (e.g., via path 198) to the bit counter block 140 to determine an increment in the adaptive setting of dLevHi, and the bit count in the CA bit counter 150 can be incremented only when the decision code d k has a value of 1. In some embodiments, additional bit counter blocks can be used to simultaneously determine the increments in the adaptive settings of dLevLo and dLevHi. For example, one bit counter block can be used for the decision code d k with a value of 1, and another bit counter block can be used for the decision code d k with a value of 0.

[0054] An increment decision can be transferred from the bit counter block 140 to the digital logic block 160 via the output 148. The digital logic block 160 can include logic circuitry to obtain corresponding adaptive settings (e.g., for dLevLo and dLevHi) based on the increment decision of the bit counter block 140. The output of the digital logic block 160 can be input into the dLev and equalization (EQ) parameter generator block 170, which can be used to generate updated dLevHi, dLevLo, and EQ parameters based on the increment decision of the bit counter block 140. The output 180 of the dLev and EQ parameter generator block 170 can include the updated dLevHi, dLevLo, and EQ parameters, which can be applied to the error circuitry 190 (e.g., comparator 132 and comparator 192) and the CA receiver 108 (e.g., the CA receiver 108 can include a DFE circuitry or a CTLE circuitry for mitigating distortion of the CA signal).

[0055] Figure 6 A flowchart of a method 300 for implementing an adaptive circuit (e.g., adaptive circuit 119, adaptive circuit 200) for dLev training to determine adaptive settings for programmable reference voltage levels (e.g., dLevHi and / or dLevLo). At block 302, the CA input circuit 20 can receive a signal indicating that dLev training can begin. For example, the memory device 10 can perform adaptation routinely or on demand (e.g., when it is determined that the distortion of the signal is greater than a threshold) or whenever there is data on the command / address bus by sending out an adaptation signal. At block 304, the adaptive circuit 116 can receive a command (e.g., an adaptation signal sent from the memory device 10) to begin dLev training, and corresponding CS gating enable signals (e.g., CS gating enable signal 112, CS gating enable signal 114) can be used to enable corresponding circuitry (e.g., the CA receiver 108, the adaptive circuit 116) of the selected memory chip (e.g., memory chip 23). In some embodiments, the adaptive circuit 116 can include only one error latch (e.g., adaptive circuit 119), and the method 300 can be used to determine the voltage levels of V IH and V IL one by one, i.e., determine one voltage level at a time. In some embodiments, the adaptive circuit 116 can include two error latches (e.g., adaptive circuit 200), and the voltage levels V IH and V IL。At block 306, the bit counter (e.g., CA bit counter 150) and the decision counter (e.g., error bit counter 146) of the adaptive circuit (e.g., adaptive circuit 119, adaptive circuit 200) can be set to 0, and a bit count limit (e.g., 2N) can be determined. In some embodiments, a selection device (e.g., a multiplexer) can be used to select an adaptive circuit (e.g., adaptive circuit 119, adaptive circuit 200) from the shared circuitry for dLev training. A training completion flag can be used to indicate whether dLev training is complete, and it can be reset to 0 at block 306. A command that can be initiated by an internal state machine in the selected memory chip (e.g., memory chip 23) can be used to start dLev training. In some embodiments, the command can be triggered each time the selected memory chip is enabled (e.g., via the CS_n signal), while in other embodiments, the command can be triggered based on an oscillator / timer, or a detected temperature drift by a temperature sensor, or a detected voltage drift, etc.

[0056] At block 308, the bit count of the bit counter (e.g., CA bit counter 150) is determined. If the bit count is less than the bit count limit (e.g., 2N), then at block 310, the error circuit (e.g., error circuit 130, error circuit 190) can compare the CA input with the current values of dLevHi and / or dLevLo (e.g., the values of dLevHi and / or dLevLo stored in a register), as described above in the paragraphs regarding Figure 3 and Figure 5 . At block 310, the CA receiver 108 can compare the CA input with the reference voltage VrCA. Depending on the output of the CA receiver 108 (the value of the decision code d k ), a selection device (e.g., a multiplexer) can be used to select the error code e kLo or the error code e kHi to be output to the bit counter block 140 for determining the adaptive settings of dLevLo or dLevHi, as described above in the paragraphs regarding Figure 5 . In some embodiments, the adaptive settings of dLevLo and dLevHi can be determined simultaneously, as described above in the paragraphs regarding Figure 5 . At block 312, the output of the decision circuit 142 and the output of the CA receiver 108 (the value of the decision code d k ) can be used to make an increment or decrement decision (e.g., based on a truth table). At block 314, the decision counter 146 can be incremented based on the output 144 of the decision circuit 142, and the CA bit counter 150 can be incremented. Then, block 308 can be repeated, and if it is determined that the bit count is less than the bit count limit (e.g., 2N), then blocks 310 to 314 can be repeated.

[0057] If it is determined at block 308 that the bit count is equal to the bit count limit (e.g., 2N), then the counting of the bit counter block 140 can be paused at block 316. The current dLevHi and / or dLevLo digital codes can be incremented or decremented by a step size based on the output 148 of the decision counter 146. The step size can be determined based on the CA input, historical values of dLevHi and dLevLo, etc. The dLevHi and dLevLo digital codes can be stored in registers, and the corresponding registers can be updated with the updated dLevHi and / or dLevLo digital codes. At block 318, the CA bit counter (e.g., CA bit counter 150) and the decision counter (e.g., decision counter 146) can be reset. At block 320, the dLev and EQ generator block 170 can generate updated values of dLevHi and dLevLo based on the updated dLevHi and dLevLo digital codes. At block 322, the training completion flag can be updated (e.g., based on a loop counter). At block 324, the value of the training completion flag can be determined. If the value of the training completion flag meets a condition (e.g., is equal to a predefined value), then the dLev training can be completed at block 326, otherwise, block 310 can be repeated.

[0058] Figure 7A flowchart of a method 400 for implementing an adaptive circuit (e.g., adaptive circuit 116, adaptive circuit 200) for equalizer training to determine an adaptive setting of EQ parameters is described. At block 402, a CA input circuit 20 may receive a signal indicating that equalizer training may begin. For example, the signal may be sent after dLev training is completed (e.g., indicated by a training completion flag). At block 404, the adaptive circuit 116 may receive a command to start equalizer training, and corresponding CS gating enable signals (e.g., CS gating enable signal 112, CS gating enable signal 114) may be used to enable corresponding circuits (e.g., CA receiver 108, adaptive circuit 116) of a selected memory chip (e.g., memory chip 23). At block 406, the bit counter (e.g., CA bit counter 150) and decision counter (e.g., error bit counter 146) of the adaptive circuit (e.g., adaptive circuit 119, adaptive circuit 200) may be set to 0, and a bit count limit (e.g., 2N) may be determined. In some embodiments, a selection device (e.g., multiplexer) may be used to select an adaptive circuit (e.g., adaptive circuit 119, adaptive circuit 200) from a shared circuitry for equalizer training. A training completion flag may be used to indicate whether equalizer training is completed, and it may be reset to 0 at block 406. A command initiated by an internal state machine in the selected memory chip (e.g., memory chip 23) may be used to start equalizer training. In some embodiments, the command may be triggered each time (e.g., via a CS_n signal) the selected memory chip is enabled, while in other embodiments, the command may be triggered based on an oscillator / timer, or a temperature drift detected by a temperature sensor, or a voltage drift detected, etc.

[0059] At block 408, the bit count of the bit counter (e.g., CA bit counter 150) is determined. If the bit count is less than the bit count limit (e.g., 2N), then at block 410, an error circuit (e.g., error circuit 190) may compare the CA input with the current values of dLevHi and dLevLo (e.g., the values of dLevHi and dLevLo stored in a register), as described above in the paragraph regarding Figure 5 The current values of dLevHi and dLevL0 may be adaptive values determined by using the dLev training method described in Figure 6 At block 410, the CA receiver 108 may compare the CA input with a reference voltage VrCA. Depending on the output (decision code d k value) of the CA receiver 108, a selection device (e.g., multiplexer) may be used to select an error code e kLo or error code e kHi。At block 412, an increment or decrement decision (e.g., based on a truth table) can be made using the output of decision circuit 142, the output of CA receiver 108 (the value of decision code d k ), and the feedback bit of the EQ parameter. For example, the equalization (EQ) parameters (e.g., resistance, capacitance, tap bias coefficient) of a DFE circuit (e.g., single-tap DFE, multi-tap DFE) or a CTLE circuit can be used in CA receiver 108, and feedback can be used to obtain an adaptive value of the EQ parameter. At block 414, decision counter 146 can be incremented based on the output 144 of decision circuit 142, and CA bit counter 150 can be incremented. Then, block 408 can be repeated, and if it is determined that the bit count is less than the bit count limit (e.g., 2N), then blocks 410 to 414 can be repeated.

[0060] If it is determined at block 408 that the bit count is equal to the bit count limit (e.g., 2N), then the counting of bit counter block 140 can be paused at block 416. The current EQ parameter digital code can be incremented or decremented by a step size based on the output 148 of decision counter 146. The step size can be determined based on the CA input, the historical values of EQ, etc. The EQ digital code can be stored in a register, and the corresponding register can be updated with the updated EQ digital code. At block 418, the CA bit counter (e.g., CA bit counter 150) and the decision counter (e.g., decision counter 146) can be reset. At block 420, dLev and EQ generator block 170 can generate an updated value of EQ (e.g., a bias voltage) for the equalization circuit (e.g., DFE, CTLE) based on the updated EQ digital code. At block 422, the training complete flag can be updated (e.g., based on a loop counter). At block 424, the value of the training complete flag can be determined. If the value of the training complete flag meets a condition (e.g., equals a predefined value), then equalizer training can be completed at block 426; otherwise, block 410 can be repeated.

[0061] Thus, the technical effects of the present disclosure include methods and systems for performing adaptation during operation to obtain adaptive settings of circuit parameters of memory chips of a memory device. Individual adaptive settings of the parameters (e.g., impedance, capacitance, equalization parameters) can be obtained for each of the memory chips in the memory device during operation. The adaptation can be performed during operation of the memory device and no training time needs to be added during startup. The adaptation can enable equalization adjustment across temperature and voltage drifts. Specifically, the adaptation of the CA input circuit can improve the CA write margin and enable a faster speed grade.

[0062] It should be understood that logically equivalent circuitry may be used to implement the systems and methods described above. For example, a logical XOR gate may be replaced by a logically equivalent combination of NOT gates, AND gates, inverse NOT gates, OR gates, NAND gates, NOR gates, or the like.

[0063] Although the present disclosure may readily admit of various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. It should be understood, however, that the present disclosure is not intended to be limited to the particular forms disclosed. Rather, the present disclosure is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.

[0064] The technologies presented and claimed herein are referenced and applied to specifically improve the art and are thus not abstract, intangible, or purely theoretical but rather practical and concrete examples. Further, if any claim appended to the end of this specification contains one or more elements designated as "means for [performing a function]" or "step for [performing a function]," then those elements are intended to be construed under 35 U.S.C. 112(f). However, for any claim containing elements designated in any other manner, such elements are not intended to be construed under 35 U.S.C. 112(f).

Claims

1. A device comprising: a receiver configured to receive a signal and generate an output of the signal; and An adaptive circuit is configured to receive the signal and obtain an adaptive value of a parameter based on the signal and the output of the signal.

2. The apparatus of claim 1, wherein the receiver comprises a command / address receiver. 3 . The device of claim 1 , wherein a selection signal is used to enable the adaptive circuit to obtain the adaptive value of the parameter of a memory chip among a plurality of memory chips of the device.

4. The apparatus of claim 1 , wherein the adaptive circuit comprises: an error circuit configured to generate an error code based on a first comparison between the signal and the parameter; a decision circuit configured to generate a decision bit based on a second comparison between the error code and the output of the signal from the receiver; and A decision counter is configured to generate a count using the decision bit and to generate an output indicating an increment or decrement of the parameter based on the count. The apparatus of claim 4 , wherein the decision circuit comprises an AND gate.

6. The device of claim 4, wherein the adaptive circuit comprises an additional error circuit configured to generate an additional error code for an additional parameter based on a third comparison between the signal and the additional parameter.

7. The device of claim 6, wherein the adaptive circuit comprises a selection device to select the error code or the additional error code configured to be output to the decision circuit based on the output of the signal.

8. The device of claim 4, wherein the adaptive circuit comprises a generator block configured to generate an updated value for the parameter based on the output from the decision counter.

9. A method comprising: receiving a signal by a receiver; generating an output of said signal by said receiver; as well as generating, by an adaptive circuit, an adaptive value of a parameter based on the signal and the output of the signal, wherein the adaptive circuit is configured to: generating an error code based on a first comparison between the signal and the parameter; generating a decision bit based on a second comparison between the error code and the output of the signal from the receiver; Using the decision bits to generate a count; and An output is generated indicative of an address or decrement of the parameter based on the count.

10. The method of claim 9, wherein the receiver comprises a command / address receiver.

11. The method according to claim 9, comprising: A selection signal is received to enable the adaptive circuit to obtain the adaptive value of the parameter of a memory chip among a plurality of memory chips.

12. The method of claim 9, wherein the decision bit is generated by using an AND gate.

13. The method of claim 9, wherein the adaptive circuit is further configured to: An additional error code is generated for an additional parameter based on a third comparison between the signal and the additional parameter.

14. The method of claim 13, wherein the adaptive circuit is further configured to: The error code or the additional error code is selected based on the output of the signal to generate the decision bit.

15. The method of claim 9, wherein the adaptive circuit is further configured to: An updated value for the parameter is generated based on the output indicating an increment or decrement of the parameter.

16. An adaptive circuit, comprising: an error circuit configured to generate an error code based on a first comparison between a signal and a parameter, wherein a receiver is configured to receive the signal and generate an output of the signal; a decision circuit configured to generate a decision bit based on a second comparison between the error code and the output of the signal from the receiver; and A decision counter is configured to generate a count using the decision bit and to generate an output indicating an increment or decrement of the parameter based on the count.

17. The adaptive circuit of claim 16, wherein the receiver comprises a command / address receiver.

18. The adaptive circuit of claim 16, wherein the adaptive circuit comprises an additional error circuit configured to generate an additional error code for an additional parameter based on a third comparison between the signal and the additional parameter.

19. The adaptive circuit of claim 18, wherein the adaptive circuit comprises a selection device configured to select the error code or the additional error code based on the output of the signal to output it to the decision circuit to generate the decision bit.

20. The adaptive circuit of claim 16, wherein the adaptive circuit comprises a generator block configured to generate an updated value for the parameter based on the output from the decision counter.

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