Preparation method of silicon carbide power device
By forming trenches in the edge area of the silicon carbide substrate sheet and performing an etching process, the stress increase and warping problems caused by the ion implantation process are solved, and the yield and test accuracy of the silicon carbide power devices are improved.
Patent Information
- Application Number
- CN202311538670.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-17
- Publication Date
- 2025-05-20
AI Technical Summary
在制造碳化硅功率器件时，离子注入工艺导致碳化硅衬底片应力增大，容易出现翘曲、破片和测试误差的问题。
At least one trench is formed in the front edge region of the silicon carbide substrate sheet and an etching process is performed in subsequent processes to reduce stress and warpage.
It effectively reduces the warpage and stress of the silicon carbide substrate sheet, improves the device yield, reduces the on-resistance, and improves the accuracy of data testing.
Smart Images
Figure CN120020999A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and particularly relates to a method for manufacturing a silicon carbide power device. Background Art
[0002] As a representative material among the third-generation semiconductors, silicon carbide (SiC) has physical properties such as a wide bandgap, a high breakdown electric field, a high thermal conductivity, and a high electron saturation velocity, which endow it with advantages such as high temperature resistance, high voltage resistance, high frequency, high power, and radiation resistance. It can reduce the energy consumption of downstream products and reduce the terminal volume, and is thus mainly applied to high-power electronic devices in aspects of power conversion and control circuits of power equipment, such as power diodes, power triodes, thyristors, MOSFETs, IGBTs, etc.
[0003] Currently, in the process of manufacturing a silicon carbide power device with SiC as the substrate, it usually includes an ion implantation process. Due to the instability of the process technology, it is bound to cause an increase in the stress of the SiC substrate (wafer) after ion implantation on the SiC substrate, and then problems such as wafer or substrate breakage, the thinning process not being able to reach the silicon process, and errors in the final test due to stress problems will occur in the subsequent manufacturing processes. Summary of the Invention
[0004] The purpose of the present invention is to provide a method for manufacturing a silicon carbide power device, so as to reduce the warpage of the silicon carbide substrate wafer and release stress, reduce the probability of chip breakage and cracking in the subsequent processes of the silicon carbide substrate wafer, improve the production rate of the silicon carbide power device, reduce the on-resistance, and improve the accuracy of subsequent data testing of the device.
[0005] To solve the above technical problems, the present invention provides a method for manufacturing a silicon carbide power device, including:
[0006] Performing at least one ion implantation process on the front surface of the silicon carbide substrate wafer, and forming at least one groove in the front edge region of the silicon carbide substrate wafer;
[0007] Performing subsequent processes on the front surface of the silicon carbide substrate wafer with the groove formed thereon to form an electrical structure including a source region, a drain region, and a gate structure, and performing at least one etching process after each subsequent process.
[0008] In some optional examples, the silicon carbide substrate wafer may be a silicon carbide wafer, and the silicon carbide wafer may include a plurality of chips and scribe lines separating the plurality of chips.
[0009] In some optional examples, the step of forming at least one groove in the front edge region of the silicon carbide substrate wafer may include:
[0010] Etch the silicon carbide wafer to form a trench in the cutting channel between two adjacent chips.
[0011] In some alternative examples, the silicon carbide substrate wafer includes a middle structural region and edge regions on both sides of the structural region;
[0012] The step of forming at least one trench in the front edge region of the silicon carbide substrate wafer includes:
[0013] Etch the silicon carbide substrate wafer corresponding to the edge region to form a trench on the silicon carbide substrate wafer.
[0014] In some alternative examples, the depth range of the trench in the direction perpendicular to the front surface of the silicon carbide substrate wafer is: 3 μm to 5 μm.
[0015] In some alternative examples, the width range of the trench in the direction parallel to the front surface of the silicon carbide substrate wafer is: 5 μm to 10 μm.
[0016] In some alternative examples, the step of performing subsequent processes on the front surface of the silicon carbide substrate wafer formed with the trench includes:
[0017] Deposit a gate oxide material layer and a gate material layer on the front surface of the silicon carbide substrate wafer in sequence, wherein the gate oxide material layer and the gate material layer also synchronously extend and fill in the trench;
[0018] Etch the gate oxide material layer and the gate material layer to form a gate structure on the front surface of the silicon carbide substrate wafer; and
[0019] Etch and remove the gate oxide material layer and the gate material layer filled in the trench.
[0020] In some alternative examples, after etching and removing the gate oxide material layer and the gate material layer filled in the trench, the preparation method further includes:
[0021] Form a blocking layer on the top surface of the gate structure, wherein the blocking layer also synchronously extends and fills in the trench;
[0022] Perform an ion implantation process on the silicon carbide substrate wafer exposed on both sides of the gate structure to form the source region or the drain region; and
[0023] Etch and remove the blocking layer filled in the trench.
[0024] In some alternative examples, after forming the gate structure and before etching away the gate oxide material layer and the gate material layer filled in the trench, or, after forming the source region or the drain region and before etching away the barrier layer filled in the trench, the preparation method further includes:
[0025] Performing a chemical mechanical polishing process on the surface of the gate oxide material layer, the gate material layer or the barrier layer.
[0026] In some alternative examples, after performing subsequent processes on the front side of the silicon carbide substrate wafer with the trench formed therein, the preparation method further includes:
[0027] Performing a thinning process on the back side of the silicon carbide substrate wafer.
[0028] Compared with the prior art, the technical solution provided by the present invention has at least one of the following beneficial effects:
[0029] In a preparation method of a silicon carbide power device provided by the present invention, after performing an ion implantation process on the front side of the silicon carbide substrate wafer, a new etching process is added to form at least one customized trench on the silicon carbide substrate wafer (or on the scribe line of the silicon carbide wafer), so as to effectively reduce the warping of the silicon carbide substrate wafer and release stress through the trenches on one side or both sides of the silicon carbide substrate wafer (or silicon carbide wafer), and reduce the probability of chip breakage and cracking in subsequent processes.
[0030] Furthermore, since the silicon carbide substrate wafer (or silicon carbide wafer) for forming the silicon carbide power device provided by the present invention forms trenches for reducing stress after ion implantation, the yield of the subsequent formed silicon carbide power device is improved, its on-resistance is reduced, the accuracy of subsequent data testing of the device is improved, and it is also very helpful for subsequent cutting. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figure 1 It is a schematic flow chart of a preparation method of a silicon carbide power device provided in some embodiments of the present invention.
[0032] Figure 2 It is a top view of the structure of multiple chips and scribe lines included when the silicon carbide substrate wafer is a silicon carbide wafer in some embodiments of the present invention.
[0033] Figure 3 In some embodiments of the present invention, using Figure 1 The preparation method of the silicon carbide power device shown forms a cross-sectional view of the structure of a trench on the scribe line of the silicon carbide wafer shown in Figure 2 Shown.
[0034] Figure 4 The structural cross-sectional view of the trench formed when the silicon carbide substrate wafer provided in some embodiments of the present invention is a single silicon carbide substrate.
[0035] Among them, the reference signs are as follows:
[0036] 10 - silicon carbide wafer;
[0037] 11 - scribe lane on the silicon carbide wafer;
[0038] 101 - trench;
[0039] 20 - silicon carbide substrate;
[0040] 21 - structural region on the silicon carbide substrate;
[0041] 22 - edge region on the silicon carbide substrate. Detailed implementation manners
[0042] In order to make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further elaborated in detail below in conjunction with the drawings and embodiments. Although the exemplary implementation methods of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the implementation manners described herein. On the contrary, these implementation manners are provided to enable a more thorough understanding of the present invention and to be able to fully convey the scope of the present invention to those skilled in the art.
[0043] The present invention will be described more specifically by way of example in the following paragraphs with reference to the drawings. The advantages and features of the present invention will be clearer according to the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the purpose of the embodiments of the present invention. It can be understood that the meanings of "on...", "above...", and "over..." in the present invention should be interpreted in the broadest manner, so that "on..." not only means "on" something "without any intermediate features or layers (i.e., directly on something)", but also includes the meaning of "on" something "with intermediate features or layers".
[0044] In addition, for the convenience of description, spatial relative terms such as "on...", "above...", "over...", "upper", "upper part", etc. can be used in this article to describe the relationship between one element or feature and another element or feature as shown in the drawings. Except for the orientation depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device can be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein can be correspondingly interpreted.
[0045] In the embodiments of the present invention, terms such as "first" and "second" are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be noted that the technical solutions described in the embodiments of the present invention can be combined arbitrarily without conflict.
[0046] The preparation method of the silicon carbide power device provided in the embodiments of the present invention will be explained below by combining the flowchart of the preparation method with the structural diagram of the trenches formed on different substrate structures.
[0047] Embodiment 1
[0048] Refer to Figure 1 and in combination with Figures 2 to 3 Figure 1 is a schematic flowchart of a preparation method of a silicon carbide power device provided in some embodiments of the present invention, Figure 2 is a schematic structural diagram of multiple chips and scribe lanes included in a silicon carbide wafer when the silicon carbide substrate wafer is the silicon carbide wafer in some embodiments of the present invention, Figure 3 In some embodiments of the present invention, using Figure 1 the preparation method of the silicon carbide power device shown forms a structural cross-section diagram of trenches on the scribe lanes of the silicon carbide wafer shown in Figure 2
[0049] As shown in Figure 1 the preparation method of the silicon carbide power device at least includes the following steps:
[0050] Step S101, performing at least one ion implantation process on the front surface of the silicon carbide substrate wafer, and forming at least one trench in the front edge region of the silicon carbide substrate wafer;
[0051] Step S102, performing subsequent processes on the front surface of the silicon carbide substrate wafer formed with the trench to form an electrical structure including a source region, a drain region, and a gate structure, and performing at least one etching process after each subsequent process.
[0052] Refer to Figure 2 In the above step S101, the silicon carbide substrate wafer is the silicon carbide wafer 10, and the silicon carbide wafer 10 may specifically include multiple chips, such as Die1, Die2, Die3,..., Dien, and scribe lanes 11 that separate the multiple chips. Among them, the silicon carbide material corresponding to each chip specifically provides a platform for the subsequent formation of the silicon carbide power device.
[0053] In an alternative example, an ion implantation process can be used to dope at least one of the chips on the silicon carbide wafer 10 with N-type or P-type ions to form a silicon carbide P-type wafer or a silicon carbide N-type wafer. Among them, the N-type ions can specifically be at least one of phosphorus ions, arsenic ions, and antimony ions, and the P-type ions can specifically be at least one of boron ions, indium ions, and gallium ions.
[0054] However, due to the immaturity of the existing ion implantation process and the instability of the manufacturing process, the ion implantation process performed on at least one of the chips usually causes lattice damage to the silicon carbide material, an increase in the warpage of the silicon carbide material, and an increase in stress, thereby resulting in a series of other technical problems.
[0055] To address this problem, the researchers of the present invention proposed a solution, which can form grooves with a specific shape on a partial region of the silicon carbide material, thereby using the grooves to reduce the warpage of the silicon carbide material, release stress, reduce the probability of chip breakage and cracking of the silicon carbide substrate wafer in subsequent processes, improve the yield of silicon carbide power devices, reduce the on-resistance, and improve the accuracy of subsequent data testing of the devices.
[0056] It should be noted that in the embodiments of the present invention, the specific position where the grooves are formed, the number of grooves, and the shape of each groove are not limited, as long as it does not prevent the formation of silicon carbide power devices.
[0057] As an example, when the silicon carbide substrate wafer is a silicon carbide wafer 10 including multiple chips as shown in Figure 2 then the groove 101 can be formed on the scribe line between two adjacent chips as shown in Figure 2 or Figure 3 and at least one groove 101 is formed on each scribe line.
[0058] Specifically, the depth range of the groove 101 in the direction perpendicular to the surface of the silicon carbide wafer 10 is: 3 μm to 5 μm, that is, it can be 3 μm, 4 μm, 5 μm, and any integer or decimal within the above numerical range, but not limited thereto; and its width range in the direction parallel to the surface of the silicon carbide wafer 10 is: 5 μm to 10 μm, that is, it can be 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, and any integer or decimal within the above numerical range, but not limited thereto.
[0059] Exemplarily, the groove 101 can be a rectangular groove structure of 3 μm × 5 μm, or a square groove structure of 5 μm × 5 μm, or a "V"-shaped groove structure of 3 μm × 5 μm or 5 μm × 5 μm, but not limited thereto.
[0060] In the above step S102, for at least one chip on the silicon carbide wafer 10, a deposition process can be further performed on the chip, such as chemical vapor deposition process or physical vapor deposition process, so as to sequentially form a gate oxide material layer (not shown in the figure) and a gate material layer (not shown in the figure) on the surface of the chip after the ion implantation process. Then, an etching process, such as dry etching process or wet etching process, is performed on the gate oxide material layer and the gate material layer to form a gate structure (not shown in the figure) on one side of the chip.
[0061] In some embodiments, since the gate oxide material layer and the gate material layer will be filled in the trench 101 synchronously during the deposition process of the gate oxide material layer and the gate material layer, therefore, in order to ensure that the trench 101 also serves the purpose of reducing the warpage degree of the silicon carbide material and releasing stress in the subsequent process, and further, after forming the gate structure, the preparation method provided in the embodiment of the present invention further includes a process of removing the gate oxide material layer and the gate material layer filled in the trench 101 by using an etching process, such as dry etching or wet etching process.
[0062] In some other embodiments, after forming the gate structure by using the preparation method provided by the present invention and before etching and removing the gate oxide material layer and the gate material layer filled in the trench 101, chemical mechanical polishing can be first performed on the gate oxide material layer and the gate material layer filled in the trench 101 to ensure that the gate oxide material layer and the gate material layer in the trench 101 can be completely removed by using the subsequent etching process.
[0063] Further, after etching and removing the gate oxide material layer and the gate material layer filled in the trench 101, the preparation method provided in the embodiment of the present invention further includes:
[0064] Forming a barrier layer (not shown in the figure) on the top surface of the gate structure, wherein the barrier layer also extends and fills in the trench 101 synchronously;
[0065] Performing an ion implantation process on the silicon carbide material exposed on both sides of the gate structure to form the source region (not shown in the figure) or the drain region (not shown in the figure); and etching and removing the barrier layer (not shown in the figure) filled in the trench 101.
[0066] In some embodiments, after forming the source region or the drain region by using the preparation method provided by the present invention and before etching and removing the barrier layer filled in the trench, chemical mechanical polishing can be first performed on the barrier layer filled in the trench 101 to ensure that the barrier layer in the trench 101 can be completely removed by using the subsequent etching process.
[0067] Further, after performing the above-described gate structure formation process and source-drain region formation process on any one chip on the silicon carbide wafer 10, processes such as thinning process, backside ohmic process, and ohmic test can also be performed on the backside of the silicon carbide wafer 10 corresponding to the chip. This is the prior art and will not be specifically described in detail in the present invention.
[0068] However, in the preparation method provided by the present invention, a plurality of grooves with a specific shape are formed on the scribe lines of the silicon carbide wafer, thereby reducing the warpage of the silicon carbide wafer, releasing the stress of the silicon carbide wafer, and then improving the tolerance of the backside of the silicon carbide wafer to the thinning process, which is expected to reach 50 μm. That is, the fragmentation rate is reduced, and then the machine requirements for subsequent processes on the silicon carbide wafer are reduced, the yield of silicon carbide power devices is increased, the on-resistance is reduced, and finally the accuracy of subsequent data testing of the device is improved.
[0069] Based on the same inventive concept, the present invention also provides an example in which grooves can be formed on a single silicon carbide substrate of a silicon carbide substrate wafer to achieve the beneficial effects of the above-mentioned Embodiment 1. For details, see Embodiment 2 below.
[0070] Embodiment 2
[0071] Refer to Figure 1 and in combination with Figure 4 Figure 1 is a schematic flow chart of a method for manufacturing a silicon carbide power device provided in some embodiments of the present invention. Figure 4 is a cross-sectional view of the structure of the grooves formed when the silicon carbide substrate wafer is a single silicon carbide substrate in some embodiments of the present invention.
[0072] As Figure 1 shown, the method for manufacturing a silicon carbide power device includes at least the following steps:
[0073] Step S101, performing at least one ion implantation process on the front side of the silicon carbide substrate wafer, and forming at least one groove in the front edge region of the silicon carbide substrate wafer.
[0074] Step S102, performing subsequent processes on the front side of the silicon carbide substrate wafer formed with the groove to form an electrical structure including a source region, a drain region, and a gate structure, and performing at least one etching process after each subsequent process.
[0075] Refer to Figure 4 In the above step S101, the silicon carbide substrate wafer is a single silicon carbide substrate 20, and the silicon carbide substrate 20 may specifically include a structure region 21 for subsequently forming a silicon carbide power device and edge regions 22 on both sides of the structure region 21.
[0076] In an alternative example, an ion implantation process can be used to dope the silicon carbide substrate 20 with N-type or P-type ions to form a p-type silicon carbide substrate or an n-type silicon carbide substrate. Among them, the N-type ions can specifically be at least one of phosphorus ions, arsenic ions, and antimony ions, and the P-type ions can specifically be at least one of boron ions, indium ions, and gallium ions.
[0077] However, due to the immaturity of the existing ion implantation process and the instability of the manufacturing process, the ion implantation process performed on the silicon carbide substrate 20 usually causes lattice damage to the silicon carbide material, an increase in the warpage degree of the silicon carbide material, and an increase in stress, thereby causing a series of other technical problems.
[0078] To solve this problem, the researchers of the present invention proposed a solution, which can form grooves with a specific shape on a part of the silicon carbide material, thereby using the grooves to reduce the warpage degree of the silicon carbide material, release stress, reduce the probability of chip breakage and cracking of the silicon carbide wafer in subsequent processes, improve the production rate of silicon carbide power devices, reduce the on-resistance, and improve the accuracy of subsequent data testing of the devices.
[0079] It should be noted that in the embodiments of the present invention, the specific position of forming the grooves, the number of grooves, and the shape of each groove are not limited.
[0080] As an example, when the silicon carbide wafer is the silicon carbide substrate 20 as shown in Figure 4 the groove 101 can be formed on the edge region 22 as shown in Figure 4 so that the groove 101 is located on both sides of the silicon carbide substrate 20.
[0081] Specifically, the depth range of the groove 101 in the direction perpendicular to the surface of the silicon carbide substrate 20 is: 3 μm to 5 μm, that is, it can be 3 μm, 4 μm, 5 μm, and any integer or decimal within the above numerical range, but not limited thereto; and its width range in the direction parallel to the surface of the silicon carbide substrate 20 is: 5 μm to 10 μm, that is, it can be 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, and any integer or decimal within the above numerical range, but not limited thereto.
[0082] Exemplarily, the groove 101 can be a rectangular groove structure of 3 μm × 5 μm, or a square groove structure of 5 μm × 5 μm, or a "V"-shaped groove structure of 3 μm × 5 μm or 5 μm × 5 μm, but not limited thereto.
[0083] In the above step S102, a deposition process, such as chemical vapor deposition or physical vapor deposition, can be further performed on the silicon carbide substrate 20 to sequentially form a gate oxide material layer (not shown in the figure) and a gate material layer (not shown in the figure) on the surface of the structure region 21 of the silicon carbide substrate 20 after the ion implantation process. Then, an etching process, such as dry etching or wet etching, is performed on the gate oxide material layer and the gate material layer to form a gate structure (not shown in the figure) on one side of the chip.
[0084] In some embodiments, since the gate oxide material layer and the gate material layer are filled in the trench 101 synchronously during the deposition process, in order to ensure that the trench 101 also serves to reduce the warpage of the silicon carbide material and release stress during subsequent processes, after forming the gate structure, the manufacturing method provided in the embodiments of the present invention further includes a process of removing the gate oxide material layer and the gate material layer filled in the trench 101 by using an etching process, such as dry etching or wet etching.
[0085] In some other embodiments, after forming the gate structure by using the manufacturing method provided by the present invention and before etching and removing the gate oxide material layer and the gate material layer filled in the trench 101, chemical mechanical polishing can be performed on the gate oxide material layer and the gate material layer filled in the trench 101 first to ensure that the gate oxide material layer and the gate material layer in the trench 101 can be completely removed by using subsequent etching processes.
[0086] Further, after etching and removing the gate oxide material layer and the gate material layer filled in the trench 101, the manufacturing method provided in the embodiments of the present invention further includes:
[0087] forming a blocking layer (not shown in the figure) on the top surface of the gate structure, and the blocking layer also extends and fills in the trench 101 synchronously;
[0088] performing an ion implantation process on the silicon carbide substrate 20 exposed on both sides of the gate structure to form the source region (not shown in the figure) or the drain region (not shown in the figure); and etching and removing the blocking layer (not shown in the figure) filled in the trench 101.
[0089] In some embodiments, after forming the source region or the drain region by using the manufacturing method provided by the present invention and before etching and removing the blocking layer filled in the trench, chemical mechanical polishing can be performed on the blocking layer filled in the trench 101 first to ensure that the blocking layer in the trench 101 can be completely removed by using subsequent etching processes.
[0090] Further, after performing the gate structure formation process and the source / drain region formation process on the silicon carbide substrate 20 as described above, processes such as back thinning process, back ohmic process, and ohmic test can be performed on the back of the silicon carbide substrate 20. This is prior art and will not be specifically described in detail in the present invention.
[0091] In summary, in a method for manufacturing a silicon carbide power device provided by the present invention, after performing an ion implantation process on the front side of a silicon carbide wafer, an additional etching process is added to form at least one customized trench on the silicon carbide wafer (or on the scribe line of the silicon carbide wafer), so as to effectively reduce the warping of the silicon carbide wafer and release stress through the trenches on one or both sides of the silicon carbide wafer, and reduce the probability of chip breakage and cracking in subsequent processes.
[0092] Furthermore, since the silicon carbide wafer (or silicon carbide wafer) for forming a silicon carbide power device provided by the present invention forms trenches for reducing stress after ion implantation, the yield of the subsequent formed silicon carbide power device is improved, its on-resistance is reduced, the accuracy of subsequent data testing of the device is improved, and it also helps a lot in subsequent cutting.
[0093] The above description is only a description of the preferred embodiments of the present invention, and does not limit the protection scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure belong to the protection scope of the present invention.
[0094] It should be noted that although the present invention has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, many possible changes and modifications can be made to the technical solution of the present invention by using the above-disclosed technical content, or modified into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still belong to the protection scope of the technical solution of the present invention.
[0095] In this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising said element.
[0096] The above is only a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention are included within the scope of protection of the present invention.
Claims
1. A method for preparing a silicon carbide power device, characterized in that: include: Performing at least one ion implantation process on the front surface of the silicon carbide substrate, and forming at least one groove in the front edge region of the silicon carbide substrate; A subsequent process is performed on the front side of the silicon carbide substrate sheet with the groove formed thereon to form an electrical structure including a source region, a drain region and a gate structure, and at least one etching process is performed after each subsequent process.
2. The method for preparing a silicon carbide power device according to claim 1, characterized in that: The silicon carbide substrate piece is a silicon carbide wafer, and the silicon carbide wafer includes a plurality of chips and dicing lanes for dividing the plurality of chips.
3. The method for preparing a silicon carbide power device according to claim 2, characterized in that: The step of forming at least one groove in the front edge region of the silicon carbide substrate comprises: The silicon carbide wafer is etched to form a groove in the dicing path between two adjacent chips.
4. The method for preparing a silicon carbide power device according to claim 3, characterized in that: The silicon carbide substrate sheet includes a structure area located in the middle and edge areas located on both sides of the structure area; The step of forming at least one groove in the front edge region of the silicon carbide substrate comprises: The silicon carbide substrate sheet corresponding to the edge region is etched to form a groove on the silicon carbide substrate sheet.
5. The method for preparing a silicon carbide power device according to claim 4, characterized in that: The depth of the groove along the direction perpendicular to the front surface of the silicon carbide substrate is 3 μm to 5 μm.
6. The method for preparing a silicon carbide power device according to claim 5, characterized in that: The width of the groove along the direction parallel to the front surface of the silicon carbide substrate is 5 μm to 10 μm.
7. The method for preparing a silicon carbide power device according to claim 6, characterized in that: The step of performing a subsequent process on the front side of the silicon carbide substrate sheet having the groove formed thereon comprises: Depositing a gate oxide material layer and a gate material layer in sequence on the front surface of the silicon carbide substrate, wherein the gate oxide material layer and the gate material layer also extend synchronously to fill in the groove; Etching the gate oxide material layer and the gate material layer to form a gate structure on the front surface of the silicon carbide substrate; and The gate oxide material layer and the gate material layer filled in the trench are removed by etching.
8. The method for preparing a silicon carbide power device according to claim 7, characterized in that: After etching away the gate oxide material layer and the gate material layer filled in the trench, the preparation method further comprises: forming a barrier layer on the top surface of the gate structure, wherein the barrier layer also extends and fills the trench simultaneously; Performing an ion implantation process on the silicon carbide substrate sheet exposed on both sides of the gate structure to form the source region or the drain region; and The barrier layer filled in the trench is removed by etching.
9. The method for preparing a silicon carbide power device according to claim 8, characterized in that: After forming the gate structure and before etching away the gate oxide material layer and the gate material layer filled in the trench, or after forming the source region or the drain region and before etching away the barrier layer filled in the trench, the preparation method further includes: A chemical mechanical polishing process is performed on the surface of the gate oxide material layer, the gate material layer or the barrier layer.
10. The method for preparing a silicon carbide power device according to claim 9, characterized in that: After performing a subsequent process on the front side of the silicon carbide substrate sheet having the groove formed thereon, the preparation method further comprises: A thinning process is performed on the back side of the silicon carbide substrate.