Semiconductor element comprising interlayer dielectric substance layer and preparation method thereof
By forming the first and second interlayer dielectric layers on the semiconductor element and performing chemical mechanical planarization, the problems of ILD0 layer depression and Al residue in the HARP process are solved, and the preparation of ILD0 layer without leakage is achieved, which shortens the process cycle and avoids plasma bombardment damage.
Patent Information
- Application Number
- CN202311542808.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-17
- Publication Date
- 2025-05-20
AI Technical Summary
When preparing the ILD0 layer in the existing HARP process, the ILD0 layer will become depression after chemical mechanical planarization, causing the Al metal layer to remain in the ILD0 layer, causing leakage problems.
The first interlayer dielectric layer is formed by HARP process, and then the second interlayer dielectric layer is formed thereon through the BPSG process, and chemical mechanical planarization is performed to avoid depression and Al residue of the ILD0 layer.
It effectively avoids the depression and Al residue of ILD0 layer during planarization, prevents leakage problems, and at the same time shortens the process cycle and avoids damage to the components by plasma bombardment.
Smart Images
Figure CN120021008A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor device including an interlayer dielectric layer and a method for manufacturing the same. Background Art
[0002] In modern times, microelectronics technology has become the foundation of the entire information industry and an important symbol reflecting a country's comprehensive strength and economic development level. With the development of integrated circuit technology, chips with high speed, high device density, low power consumption, and low cost have increasingly become the main products of ultra-large scale integrated circuit manufacturing.
[0003] The semiconductor ILD0 layer is an important component in semiconductor devices. ILD0 is the abbreviation of Inter Layer Dielectric (the interlayer dielectric of the zero-th layer), which is mainly used to isolate and protect the circuit structure of semiconductor devices.
[0004] In the process of preparing the ILD0 layer by the existing HARP process, due to the properties of the ILD0 layer formed by HARP, after subsequent chemical mechanical planarization treatment, depressions will appear in the ILD0 layer, which will cause some metallic Al to remain in the ILD0 layer during the preparation of the Al metal layer, resulting in leakage of the ILD0 layer. Summary of the Invention
[0005] The object of the present disclosure is to provide a semiconductor device including an interlayer dielectric layer and a method for manufacturing the same.
[0006] To achieve the above object, in a first aspect of the present disclosure, a method for forming an interlayer dielectric layer on a semiconductor device is provided, the method including the following steps:
[0007] S1. On the semiconductor device provided with a plurality of gates, form a first interlayer dielectric layer by the HARP process;
[0008] The first interlayer dielectric layer fills the spaces between the plurality of gates;
[0009] The maximum height of the first interlayer dielectric layer is less than the minimum height of the gates;
[0010] S2. Form a second interlayer dielectric layer by the BPSG process;
[0011] The second interlayer dielectric layer covers the surface of the first interlayer dielectric layer;
[0012] S3. Perform a first chemical mechanical planarization treatment on the second interlayer dielectric layer.
[0013] Optionally, step S1 includes: subjecting tetraethyl orthosilicate and ozone to a thermal reaction to form the first interlayer dielectric layer, with conditions including: a temperature of 400 - 600 °C, a reaction pressure of 400 - 700 Torr, a flow rate of tetraethyl orthosilicate of 1000 - 40000 sccm, and a flow rate of ozone of 1000 - 40000 sccm.
[0014] Optionally, step S2 includes: forming the second interlayer dielectric layer by sub-atmospheric chemical vapor deposition, with conditions including: a temperature of 400 - 600 °C and a reaction pressure of 100 - 700 Torr.
[0015] Optionally, in step S2, the raw materials for forming the second interlayer dielectric layer include triethyl borate, triethyl phosphate, and tetraethyl orthosilicate;
[0016] The flow rate of tetraethyl orthosilicate is 1000 - 40000 sccm, the flow rate of triethyl borate is 200 - 40000 sccm, and the flow rate of triethyl phosphate is 200 - 40000 sccm.
[0017] Optionally, in the second interlayer dielectric layer, the concentration of boron atoms is 2.5 - 7.5 at%, and the concentration of phosphorus atoms is 0.5 - 4.5 at%.
[0018] Optionally, step S3 includes: subjecting the second interlayer dielectric layer to the first chemical mechanical planarization treatment by chemical mechanical polishing, with a pressure of 1 - 3 PSI.
[0019] Optionally, the method further includes: forming an Al layer on the second interlayer dielectric layer, and then subjecting the Al layer to a second chemical mechanical planarization treatment.
[0020] Optionally, the method further includes: subjecting the Al layer to the second chemical mechanical planarization treatment by chemical mechanical polishing, with a pressure of 1 - 3 PSI.
[0021] Optionally, the method further includes: forming an Al layer on the second interlayer dielectric layer by physical vapor deposition, with a pressure of 0.5 - 100 mtorr.
[0022] The second aspect of the present disclosure provides a semiconductor device including an interlayer dielectric layer prepared by using the method described in the first aspect of the present disclosure.
[0023] The third aspect of the present disclosure provides a semiconductor device including an interlayer dielectric layer, on which a plurality of gates are provided. The interlayer dielectric layer is formed on the semiconductor device and fills between the gates. The interlayer dielectric layer sequentially includes a first interlayer dielectric layer and a second interlayer dielectric layer stacked from bottom to top;
[0024] The first interlayer dielectric layer comprises silicon dioxide, and the second interlayer dielectric layer comprises silicon dioxide doped with boron and phosphorus elements.
[0025] Through the above technical solution, the present disclosure adopts the HARP process to form the first interlayer dielectric layer on a semiconductor element provided with a plurality of gates; then adopts the BPSG process to form the second interlayer dielectric layer on the first interlayer dielectric layer. The interlayer dielectric layer (ILD0 layer) formed by the method of the present disclosure will not exhibit a dishing effect during subsequent planarization, that is, the surface of the ILD0 layer will not have depressions, and there will be no phenomenon of Al remaining in the ILD0 layer during the process of preparing the Al layer, avoiding the problem of leakage of the ILD0 layer; moreover, no holes are generated during the process of forming the second interlayer dielectric layer by the BPSG process, avoiding the step of plasma bombardment. On the one hand, the process of forming the first interlayer dielectric layer and the second interlayer dielectric layer can be completed on the same machine tool, shortening the process cycle; on the other hand, it avoids damage to the components caused by plasma bombardment.
[0026] Other features and advantages of the present disclosure will be described in detail in the subsequent specific implementation part. Brief Description of the Drawings
[0027] The drawings are used to provide a further understanding of the present disclosure, and constitute a part of the specification, and are used to explain the present disclosure together with the following specific implementation manners, but do not constitute a limitation to the present disclosure. In the drawings:
[0028] Figure 1 is a flowchart of a specific implementation manner of the method for forming an interlayer dielectric layer on a semiconductor element according to the present disclosure.
[0029] Figure 2 is a schematic diagram of the structure after forming the second interlayer dielectric layer according to the present disclosure.
[0030] Figure 3 is a schematic diagram of the structure obtained after performing the first chemical mechanical planarization treatment on the second interlayer dielectric layer according to the present disclosure.
[0031] Description of the Reference Numerals in the Drawings
[0032] 1 Semiconductor element
[0033] 2 First interlayer dielectric layer
[0034] 3 Second interlayer dielectric layer
[0035] 4 Contact hole etch stop layer
[0036] 5 Gate Specific Implementation Manner
[0037] The following is a detailed description of the specific embodiments of the present disclosure with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining and understanding the present disclosure, and are not used to limit the present disclosure.
[0038] As Figure 1 shown, a method for manufacturing a semiconductor device including an interlayer dielectric layer is provided in the first aspect of the present disclosure. The method includes the following steps:
[0039] S1. On the semiconductor device provided with a plurality of gates, a first interlayer dielectric layer is formed by the HARP process;
[0040] The first interlayer dielectric layer fills the gaps between the plurality of gates;
[0041] The maximum height of the first interlayer dielectric layer is less than the minimum height of the gates;
[0042] S2. A second interlayer dielectric layer is formed by the BPSG process;
[0043] The second interlayer dielectric layer covers the surface of the first interlayer dielectric layer;
[0044] S3. A first chemical mechanical planarization treatment is performed on the second interlayer dielectric layer.
[0045] During the process of forming the ILD0 layer (interlayer dielectric layer) and planarizing on the surface of the semiconductor device provided with gates by the HARP process, a dishing effect occurred, that is, due to the action of chemical reaction and mechanical force, depressions appeared on the surface of the ILD0 layer. These depressions would cause some Al to remain in the ILD0 layer during the preparation of the Al layer, resulting in leakage of the interlayer dielectric layer. The inventors of the present disclosure formed the first interlayer dielectric layer by the HARP process, and then formed the second interlayer dielectric layer on the first interlayer dielectric layer by the BPSG process. This method will not show the dishing effect during the subsequent planarization process, that is, no depressions will appear on the surface of the ILD0 layer, and there will be no phenomenon of Al remaining in the ILD0 layer during the preparation of the Al layer, avoiding the problem of ILD0 layer leakage.
[0046] In the present disclosure, the thicknesses of the first interlayer dielectric layer and the second interlayer dielectric layer can be uniform or non-uniform.
[0047] In the present disclosure, the semiconductor device provided with a plurality of gates can be a semiconductor device obtained after the CESL SIN process, which includes a P-well region and an N-well region.
[0048] In the present disclosure, the gate is a non-metal gate, for example, it can be a polysilicon dummy gate. A contact hole etch stop layer is provided on the surface of the gate, and the material can be silicon nitride. The above-mentioned gate is removed during subsequent preparation and filled to form an Al gate; after step S1, a first interlayer dielectric layer is also formed on the upper surface of the contact hole etch stop layer.
[0049] In the present disclosure, the heights of the respective gates can be the same or different. The "minimum height of the gate" refers to the minimum distance between the top of the gate and the upper surface of the semiconductor element.
[0050] In order to obtain a better hole filling effect, according to an embodiment of the present disclosure, step S1 includes: thermally reacting tetraethyl orthosilicate and ozone to form a first interlayer dielectric layer; the conditions include: the temperature is 400 - 600 °C, the reaction pressure is 400 - 700 Torr, the flow rate of tetraethyl orthosilicate is 1000 - 40000 sccm, the flow rate of ozone is 1000 - 40000 sccm, and step S1 is carried out in a sub-atmospheric chemical vapor deposition (SACVD) chamber; the height of the first interlayer dielectric layer is set according to product requirements, and the height of the first interlayer dielectric layer can be controlled by the reaction time.
[0051] According to an embodiment of the present disclosure, step S2 includes: forming a second interlayer dielectric layer by magnetron sputtering chemical vapor deposition; the conditions include: the temperature is 400 - 600 °C, the reaction pressure is 100 - 700 Torr; the minimum height of the second interlayer dielectric layer is The height of the second interlayer dielectric layer can be controlled by the deposition time.
[0052] According to an embodiment of the present disclosure, in step S2, the raw materials for forming the second interlayer dielectric layer can include triethyl borate (TEB), triethyl phosphate (TEPO), and tetraethyl orthosilicate (TEOS). The above-mentioned raw materials have good fluidity, and during the heat treatment process, the high temperature enhances their fluidity, and no holes are generated during the formation of the second interlayer dielectric layer, avoiding the step of plasma bombardment. On the one hand, the processes of forming the first interlayer dielectric layer and the second interlayer dielectric layer can be completed on the same machine, shortening the process cycle; on the other hand, damage caused by plasma bombardment is avoided; among them, the flow rate of tetraethyl orthosilicate is 1000 - 40000 sccm, the flow rate of triethyl borate is 200 - 40000 sccm, and the flow rate of triethyl phosphate is 200 - 40000 sccm.
[0053] According to an embodiment of the present disclosure, step S3 includes: performing the first chemical mechanical planarization treatment on the second interlayer dielectric layer by chemical mechanical polishing, with a pressure of 1 - 3 PSI, and the temperature can be room temperature.
[0054] According to an embodiment of the present disclosure, in the second interlayer dielectric layer, the concentration of boron atoms is 2.5 to 7.5 at%, and the concentration of phosphorus atoms is 0.5 to 4.5 at%. The concentrations of boron atoms and phosphorus atoms are the ratios of the number of atoms of boron atoms or phosphorus atoms to the total number of atoms in the second interlayer dielectric layer; the concentrations of boron atoms and phosphorus atoms are controlled by the flow rates of tetraethyl orthosilicate, triethyl borate, and triethyl phosphate.
[0055] According to an embodiment of the present disclosure, the method further includes: forming an Al layer on the second interlayer dielectric layer, and then performing a second chemical mechanical planarization process on the Al layer until the contact hole etch stop layer is removed; the process of forming the Al layer can also form an Al gate at the original position of the polysilicon.
[0056] According to an embodiment of the present disclosure, the method further includes: removing the polysilicon before forming the Al layer, and the removal method is conventional in the art and will not be elaborated here.
[0057] According to an embodiment of the present disclosure, the method further includes: performing the second chemical mechanical planarization process on the Al layer by chemical mechanical polishing, with a pressure of 1 to 3 PSI and a temperature that can be room temperature.
[0058] According to an embodiment of the present disclosure, the method further includes: forming an Al layer on the second interlayer dielectric layer by physical vapor deposition, with a pressure of 0.5 to 100 mtorr, a target material that can be aluminum metal, and a temperature that can be room temperature.
[0059] According to a specific embodiment of the present disclosure, the method for manufacturing a semiconductor device including an interlayer dielectric layer may specifically include the following steps:
[0060] S1. On a semiconductor device 1 provided with a plurality of gates 5, tetraethyl orthosilicate and ozone are thermally reacted by the HARP process, and the conditions include: a temperature of 400 to 600 °C, a reaction pressure of 400 to 700 Torr, a flow rate of tetraethyl orthosilicate of 1000 to 40000 sccm, and a flow rate of ozone of 1000 to 40000 sccm, to form a first interlayer dielectric layer 2;
[0061] The first interlayer dielectric layer 2 fills the gaps between the plurality of gates 5;
[0062] The maximum height of the first interlayer dielectric layer 2 is less than the minimum height of the gates 5;
[0063] S2. By using the BPSG process, triethyl borate, triethyl phosphate, and tetraethyl orthosilicate are used to form the second interlayer dielectric layer 3 by SACVD. The conditions include: the temperature is 400 - 600 °C, the reaction pressure is 100 - 700 Torr, the flow rate of tetraethyl orthosilicate is 1000 - 40000 sccm, the flow rate of triethyl borate is 200 - 40000 sccm, and the flow rate of triethyl phosphate is 200 - 40000 sccm;
[0064] By controlling the flow rates of tetraethyl orthosilicate, triethyl borate, and triethyl phosphate, the concentration of boron atoms in the second interlayer dielectric layer is 2.5 - 7.5 at%, and the concentration of phosphorus atoms is 0.5 - 4.5 at%;
[0065] The obtained structure is as Figure 2 shown;
[0066] S3. At room temperature, the second interlayer dielectric layer 3 is subjected to the first chemical mechanical planarization treatment by chemical mechanical polishing, with a pressure of 1 - 3 PSI, until the contact hole etch stop layer 4 is removed. The obtained structure is as Figure 3 shown;
[0067] S4. Remove the polysilicon;
[0068] S5. At room temperature, using aluminum metal as the target, an Al layer is formed on the second interlayer dielectric layer 3 by physical vapor deposition, with a pressure of 0.5 - 100 mtorr; then the Al layer is subjected to the second chemical mechanical planarization treatment by chemical mechanical polishing, with a pressure of 1 - 3 PSI.
[0069] By adopting the specific embodiments of the present disclosure, the generation of holes in the interlayer dielectric layer (ILD0 layer) can be avoided, and the leakage of the ILD0 layer is avoided; and the step of plasma bombardment is avoided. On the one hand, the processes of forming the first interlayer dielectric layer and the second interlayer dielectric layer are completed on the same machine tool, shortening the process cycle; on the other hand, the damage to the components caused by plasma bombardment is avoided.
[0070] The second aspect of the present disclosure provides a semiconductor device including an interlayer dielectric layer prepared by using the method described in the first aspect of the present disclosure.
[0071] The third aspect of the present disclosure provides a semiconductor device including an interlayer dielectric layer. A plurality of gates are provided on the semiconductor device. The interlayer dielectric layer is formed on the semiconductor device and fills between the gates. The interlayer dielectric layer sequentially includes a first interlayer dielectric layer and a second interlayer dielectric layer stacked from bottom to top;
[0072] The first interlayer dielectric layer includes silicon dioxide, and the second interlayer dielectric layer includes silicon dioxide doped with boron and phosphorus elements.
[0073] The preferred embodiments of the present disclosure have been described in detail above in conjunction with the accompanying drawings. However, the present disclosure is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present disclosure, various simple modifications can be made to the technical solutions of the present disclosure, and these simple modifications all fall within the protection scope of the present disclosure.
[0074] In addition, it should be noted that, among the various specific technical features described in the above specific embodiments, they can be combined in any appropriate manner without conflict. To avoid unnecessary repetition, the present disclosure does not separately describe various possible combination methods.
[0075] Furthermore, any combination can be made among various different embodiments of the present disclosure, as long as it does not violate the idea of the present disclosure, and it should also be regarded as the content disclosed by the present disclosure.
Claims
1. A method for forming an interlayer dielectric layer on a semiconductor device, characterized in that: The method comprises the following steps: S1, forming a first interlayer dielectric layer on the semiconductor element provided with a plurality of gates by a HARP process; The first interlayer dielectric layer fills the spaces between the plurality of gates; The maximum height of the first interlayer dielectric layer is smaller than the minimum height of the gate; S2, forming a second interlayer dielectric layer by a BPSG process; The second interlayer dielectric layer covers the surface of the first interlayer dielectric layer; S3. Perform a first chemical mechanical planarization process on the second interlayer dielectric layer.
2. The method according to claim 1, wherein: Step S1 includes: thermally reacting tetraethyl orthosilicate and ozone to form the first interlayer dielectric layer; the conditions include: temperature of 400-600° C., reaction pressure of 400-700 Torr, flow rate of the tetraethyl orthosilicate of 1000-40000 sccm, and flow rate of the ozone of 1000-40000 sccm.
3. The method according to claim 1, wherein: Step S2 includes: forming the second interlayer dielectric layer by sub-atmospheric pressure chemical vapor deposition; the conditions include: temperature of 400-600° C. and reaction pressure of 100-700 Torr.
4. The method according to claim 3, wherein: In step S2, raw materials for forming the second interlayer dielectric layer include triethyl borate, triethyl phosphate and ethyl orthosilicate; The flow rate of the tetraethyl orthosilicate is 1000-40000 sccm, the flow rate of the triethyl borate is 200-40000 sccm, and the flow rate of the triethyl phosphate is 200-40000 sccm.
5. The method according to claim 1, wherein: In the second interlayer dielectric layer, the concentration of boron atoms is 2.5-7.5 at %, and the concentration of phosphorus atoms is 0.5-4.5 at %.
6. The method according to claim 1, wherein: Step S3 includes: performing the first chemical mechanical planarization treatment on the second interlayer dielectric layer by chemical mechanical polishing at a pressure of 1 to 3 PSI.
7. The method according to claim 1, wherein: The method further includes: forming an Al layer on the second interlayer dielectric layer, and then performing a second chemical mechanical planarization process on the Al layer.
8. The method according to claim 7, wherein: The method further includes: performing the second chemical mechanical planarization treatment on the Al layer by chemical mechanical polishing at a pressure of 1 to 3 PSI.
9. The method according to claim 7, wherein: The method further comprises: forming an Al layer on the second interlayer dielectric layer by physical vapor deposition at a pressure of 0.5 to 100 mtorr.
10. A semiconductor element comprising an interlayer dielectric layer prepared by the method according to any one of claims 1 to 9.
11. A semiconductor device comprising an interlayer dielectric layer, characterized in that: A plurality of gates are arranged on the semiconductor element, the interlayer dielectric layer is formed on the semiconductor element and filled between the gates, and the interlayer dielectric layer includes a first interlayer dielectric layer and a second interlayer dielectric layer stacked from bottom to top; The first interlayer dielectric layer includes silicon dioxide, and the second interlayer dielectric layer includes silicon dioxide doped with boron and phosphorus.