Semiconductor package including heat dissipation member and method of manufacturing same

Abstract

The invention relates to a semiconductor package including a heat dissipation member and a method of manufacturing the same. A semiconductor package includes a heat dissipation member having a plurality of through holes through a first surface of the heat dissipation member. The semiconductor package further includes a semiconductor chip disposed on the first surface of the heat dissipation member and a vertical connector connected to the semiconductor chip. The semiconductor package also includes a molding member sealing the semiconductor chip, sealing the vertical connector, and filling the plurality of through holes. The semiconductor package additionally includes a redistribution layer disposed on the molding member.

Description

Technical Field

[0001] Various embodiments of the disclosed technology generally relate to a semiconductor package including a heat dissipation member and a method of manufacturing the same. Background Art

[0002] Even though electronic products are getting smaller in size, they are increasingly required to process large amounts of data. Therefore, there is an increasing need to increase the integration degree of semiconductor devices used in electronic products.

[0003] As the integration degree of semiconductor devices increases, the heat generated during the operation of semiconductor devices may adversely affect the operation of components of semiconductor chips. Summary of the Invention

[0004] In an embodiment, a semiconductor package may include: a heat dissipation member having a plurality of through-holes passing through a first surface of the heat dissipation member; a semiconductor chip disposed on the first surface of the heat dissipation member; a vertical connector connected to the semiconductor chip; a molding member sealing the semiconductor chip, sealing the vertical connector, and filling the plurality of through-holes; and a redistribution layer disposed on the molding member.

[0005] In an embodiment, a method of manufacturing a semiconductor package may include the steps of: forming a heat dissipation member having a plurality of through-holes on a carrier substrate; disposing a semiconductor chip on the heat dissipation member; forming a vertical connector connected to the semiconductor chip; forming a molding member sealing the semiconductor chip and the vertical connector and filling the plurality of through-holes; and forming a redistribution layer on the molding member. Brief Description of the Drawings

[0006] Figure 1 is a cross-sectional view of a semiconductor package based on an embodiment of the disclosed technology.

[0007] Figure 2 is a plan view showing a heat dissipation member and fiducial marks of a semiconductor package based on an embodiment of the disclosed technology.

[0008] Figure 3 is a cross-sectional view of a semiconductor package based on an embodiment of the disclosed technology.

[0009] Figures 4 to 11 is a view showing a method of manufacturing a semiconductor package based on an embodiment of the disclosed technology. Detailed Description

[0010] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, although shown in different drawings, the same elements will be referred to by the same reference numerals. In addition, in the following description of the present disclosure, when the subject matter of the present disclosure may be unclear, the detailed description of known functions and configurations included herein will be omitted. It should be noted that unless specifically stated otherwise, the terms "comprising", "having", "including", etc. used in the specification and claims should not be construed as being limited to the means listed thereafter. In the case of using an indefinite article or a definite article (e.g., "a", "an", and "the") when referring to a singular noun, unless specifically stated otherwise, this may include the plural of the noun.

[0011] In addition, when describing the components of the present disclosure, terms such as first, second, A, B, (a), and (b) may be used. These are only for distinguishing one component from another, and do not limit the substance, order, sequence, or quantity of the components.

[0012] In the description of the positional relationship of components, in the case of describing at least two components as "connected", "coupled", or "linked", it will be understood that at least two components may be directly "connected", "coupled", or "linked", but may be indirectly "connected", "coupled", or "linked" in the case where another component is interposed between the two components. Here, the other component may be included in at least one of the at least two components that are "connected", "coupled", or "linked" to each other.

[0013] In the description of the time flow relationship of components, operation methods, or manufacturing methods, in the case of describing the front-back relationship in terms of time or the front-back relationship in terms of process flow, for example, by "after", "subsequently", "next", or "before", unless "immediately" or "directly" is used, non-consecutive cases may be included.

[0014] In the case of referring to the numerical value of a component or its corresponding information (e.g., level, etc.), even without a separate explicit description, the numerical value or its corresponding information may be interpreted as including an error range that may be caused by various factors (e.g., process variables, internal or external shocks, noise, etc.).

[0015] Hereinafter, various embodiments of the disclosed technology will be described in detail with reference to the accompanying drawings. The various embodiments are intended to provide a semiconductor package including a heat dissipation member and a method of manufacturing the same. According to some embodiments of the disclosed technology, a semiconductor package including a heat dissipation member having a plurality of through holes filled with a molding member and a method of manufacturing the same may be provided.

[0016] Figure 1 is a cross-sectional view of a semiconductor package based on an embodiment of the disclosed technology, Figure 2It is a plan view showing a heat dissipation member and a fiducial mark of a semiconductor package according to an embodiment of the disclosed technology.

[0017] Referring to Figure 1 and Figure 2 , the semiconductor package 1 may include a mounting region MR and a peripheral region ER around the mounting region MR. The peripheral region ER may surround the outer edge of the mounting region MR.

[0018] The heat dissipation member 10 may be disposed in the mounting region MR and may include a plurality of through holes OP passing through one surface 10a. For example, the through holes OP may extend from one surface 10a of the heat dissipation member 10 to the other surface 10b and may pass through the other surface 10b. The other surface 10b of the heat dissipation member 10 may be a surface opposite to the one surface 10a. The other surface 10b of the heat dissipation member 10 may be a surface farther from the surface of the first semiconductor chip 21 than the one surface 10a. The one surface 10a and the other surface 10b of the heat dissipation member 10 are also respectively referred to as the first surface 10a and the second surface 10b of the heat dissipation member 10. The heat dissipation member 10 may have a mesh structure having a plurality of through holes OP.

[0019] As Figure 2 shown, the through holes OP may have a diamond shape. Although not shown, the through holes OP may have a polygonal shape such as a triangle, a rectangle, a square, or a pentagon, or may have a circular or elliptical shape. Although Figure 2 the case where the through holes OP are regularly arranged is shown, the through holes OP may be irregularly arranged.

[0020] The heat dissipation member 10 may include a material having a higher Young's modulus than the molding member 40 to be described later. The heat dissipation member 10 may be made of metal.

[0021] The heat dissipation member 10 may have a structure in which a barrier metal layer 11, a seed metal layer 12, and a plated metal layer 13 are stacked. The seed metal layer 12 may be disposed on the barrier metal layer 11, and the plated metal layer 13 may be disposed on the seed metal layer 12. The barrier metal layer 11, the seed metal layer 12, and the plated metal layer 13 may have the same layout structure.

[0022] For example, the seed metal layer 12 and the plated metal layer 13 may include the same material. The seed metal layer 12 and the plated metal layer 13 may include copper (Cu). The barrier metal layer 11 may include at least one of metals having a lower ionization tendency than the plated metal layer 13. For example, the barrier metal layer 11 may include at least one of titanium (Ti), titanium tungsten (TiW), and nickel (Ni). A metal having a lower ionization tendency refers to a metal having a more stable electron configuration and thus a higher ionization energy.

[0023] The upper surface of the metal plating layer 13 may be configured as one surface 10a of the heat dissipation member 10, and the lower surface of the barrier metal layer 11 may be configured as the other surface 10b of the heat dissipation member 10. The upper surface of the metal plating layer 13 is covered by the molding member 40 and is not exposed to the outside of the semiconductor package 1, but the lower surface of the barrier metal layer 11 is exposed to the outside of the semiconductor package 1. Since the barrier metal layer 11 having a surface exposed to the outside of the semiconductor package 1 is made of a metal with a low ionization tendency, oxidation of the heat dissipation member 10 can be suppressed.

[0024] The first semiconductor chip 21 to the fourth semiconductor chip 24 may be stacked on one surface 10a of the heat dissipation member 10.

[0025] Each of the first semiconductor chip 21 to the fourth semiconductor chip 24 may include a non-volatile memory such as a flash memory, a PRAM (phase change random access memory), and an MRAM (magnetoresistive random access memory), or a volatile memory such as a DRAM (dynamic random access memory) and an SRAM (static random access memory), or a non-memory such as a logic circuit, but is not limited thereto.

[0026] Each of the first semiconductor chip 21 to the fourth semiconductor chip 24 may have a front side provided with a chip pad (one of 21A to 24A) and a rear side opposite to the front side. The chip pad (one of 21A to 24A) may be electrically connected to the integrated circuit in the semiconductor chip (one of 21 to 24).

[0027] The first semiconductor chip 21 to the fourth semiconductor chip 24 may be stacked on the heat dissipation member 10 in a face-up type such that their rear sides face the heat dissipation member 10.

[0028] The first adhesive layer 61 to the fourth adhesive layer 64 may be respectively attached to the rear sides of the first semiconductor chip 21 to the fourth semiconductor chip 24. Each of the first semiconductor chip 21 to the fourth semiconductor chip 24 may be attached to the semiconductor chip (one of 21 to 23) or the heat dissipation member 10 located directly below it using an adhesive layer (one of 61 to 64). The first semiconductor chip 21 to the fourth semiconductor chip 24 may be stacked offset from each other to expose the corresponding chip pads 21A to 24A.

[0029] Although Figure 1 The embodiment showing four semiconductor chips 21 to 24 stacked on the heat dissipation member 10 is only an example, and the disclosed technology is not limited thereto. The disclosed technology includes all embodiments in which at least one semiconductor chip is provided on the heat dissipation member 10.

[0030] The first vertical connector 31 to the fourth vertical connector 34 may be respectively connected to the first semiconductor chip 21 to the fourth semiconductor chip 24.

[0031] Each of the first to fourth vertical connectors 31 to 34 may extend in the vertical direction, and one end thereof is connected to a corresponding one of the chip pads 21A to 24A of the first to fourth semiconductor chips 21 to 24. The first to fourth vertical connectors 31 to 34 may be configured with interconnecting members that extend substantially vertically from the surfaces of the first to fourth semiconductor chips 21 to 24 or stand substantially vertically.

[0032] The first to fourth vertical connectors 31 to 34 may respectively provide paths for transmitting electrical signals to the first to fourth semiconductor chips 21 to 24. For example, the first to fourth vertical connectors 31 to 34 may be formed of one or more conductive metals such as gold (Au) or copper (Cu).

[0033] The first to fourth vertical connectors 31 to 34 may be vertical bonding leads. Alternatively, among the first to fourth vertical connectors 31 to 34, the fourth vertical connector 34 connected to the uppermost fourth semiconductor chip 24 may be a conductive bump, and the first to third vertical connectors 31 to 33 connected to the first to third semiconductor chips 21 to 23 other than the fourth semiconductor chip 24 may be vertical bonding leads.

[0034] The molding member 40 is formed to cover one surface 10a of the heat dissipation member 10, fill the through holes OP of the heat dissipation member 10, and cover the first to fourth semiconductor chips 21 to 24 and the first to fourth vertical connectors 31 to 34. The molding member 40 may be used to seal the first to fourth semiconductor chips 21 to 24 and the first to fourth vertical connectors 31 to 34 to protect the first to fourth semiconductor chips 21 to 24 and the first to fourth vertical connectors 31 to 34 from the external environment. The molding member 40 may include an encapsulating material such as an epoxy molding compound (EMC) material. The encapsulating material may include, for example, an epoxy resin component and fillers dispersed therein.

[0035] Since the molding member 40 fills the through holes OP of the heat dissipation member 10, the heat dissipation member 10 may be combined with the molding member 40.

[0036] The molded member 40 and the heat dissipation member 10 in combination can be used as protective layers 10 and 40 for protecting the first semiconductor chip 21 to the fourth semiconductor chip 24 and the first vertical connector 31 to the fourth vertical connector 34. Since the heat dissipation member 10 is combined with the molded member 40, the volume fraction occupied by the molded member 40 in the semiconductor package 1 can be reduced. As described above, since the heat dissipation member 10 can be made of a material having a larger Young's modulus than the molded member 40, the heat dissipation member 10 can be used to increase the body strength of the protective layers 10 and 40.

[0037] The molded member 40 may include protrusions 41 that fill the through holes OP. The inner surface 10d of the heat dissipation member 10 provided by the through holes OP can contact the protrusions 41 of the molded member 40.

[0038] The inner surface 10d of the heat dissipation member 10 may be a surface located in the through holes OP. In the disclosed technology, the through holes OP can pass through one surface 10a and another surface 10b of the heat dissipation member 10, and the inner surface 10d of the heat dissipation member 10 may be a surface connecting one surface 10a and another surface 10b. The end of the protrusion 41 of the molded member 40 can be disposed on the same plane as the another surface 10b of the heat dissipation member 10. The molded member 40 may not extend to the another surface 10b of the heat dissipation member 10.

[0039] By forming a plurality of through holes OP in the heat dissipation member 10 and filling the through holes OP of the heat dissipation member 10 with the molded member 40, the contact area between the molded member 40 and the heat dissipation member 10 can be increased. Therefore, the stress caused by the property differences such as ductility and coefficient of thermal expansion between the material configuring the heat dissipation member 10 and the material configuring the molded member 40 can be alleviated or mitigated. Therefore, delamination and / or cracking at the interface between the heat dissipation member 10 and the molded member 40 due to the stress can be alleviated, suppressed, or prevented.

[0040] The molded member 40 can be configured to surround the outer surface 10c of the heat dissipation member 10. The outer surface 10c of the heat dissipation member 10 may be a surface connecting the outer edge of one surface 10a and the outer edge of another surface 10b. The heat dissipation member 10 may not be disposed on the side surface of the molded member 40. The side surface of the molded member 40 may be a surface that is cut in the sawing process for individuating the semiconductor package 1. Since the heat dissipation member 10 is not disposed on the surface cut in the sawing process, the stress applied to the material during the sawing process can be reduced, and the appearance of burrs can be alleviated, suppressed, or prevented.

[0041] The redistribution layer 50 is disposed on the molded member 40. The redistribution layer 50 may include redistribution lines 51 and a dielectric layer 52. The redistribution lines 51 may be connected to the vertical connectors 31 to 34 and may be connected to the first semiconductor chip 21 to the fourth semiconductor chip 24 through the vertical connectors 31 to 34. The redistribution lines 51 may be insulated from each other by the dielectric layer 52.

[0042] The external connection terminals 70 may be connected to some of the redistribution lines 51. Although not shown, some of the redistribution lines 51 may include ball bond pads. The dielectric layer 52 may have openings exposing the ball bond pads. The external connection terminals 70 may be attached to the ball bond pads. The external connection terminals 70 may include solder balls.

[0043] As Figure 2 shown, the fiducial mark PM may be disposed in the peripheral region ER. The fiducial mark PM may be used as a reference point (e.g., zero point) for determining the positions of the first semiconductor chip 21 to the fourth semiconductor chip 24 in the process of disposing the first semiconductor chip 21 to the fourth semiconductor chip 24.

[0044] Although not shown in the figure, the fiducial mark PM may be disposed at the same height level as the plated metal layer 13 of the heat dissipation member 10. The fiducial mark PM may be formed together with the plated metal layer 13 of the heat dissipation member 10 and may be made of the same material as the plated metal layer 13, but is not limited thereto. The fiducial mark PM may be formed in a process separate from the plated metal layer 13 or may be made of a material different from the plated metal layer 13. Although Figure 2 the case where the fiducial mark PM is shown disposed in the peripheral region ER is illustrated, the position of the fiducial mark PM is not limited thereto.

[0045] Figure 3 is a cross-sectional view of a semiconductor package based on an embodiment of the disclosed technology.

[0046] Referring Figure 3 , the through hole OP of the heat dissipation member 10 may be formed to a depth that passes through one surface 10a of the heat dissipation member 10 but does not reach the other surface 10b of the heat dissipation member 10.

[0047] The barrier metal layer 11 and the seed metal layer 12 of the heat dissipation member 10 may be disposed in the mounting region MR and the peripheral region ER, and the plated metal layer 13 may be disposed in the mounting region MR. The through hole OP may pass through the plated metal layer 13, but may not pass through the barrier metal layer 11 and the seed metal layer 12. The through hole OP may pass through the plated metal layer 13 to expose the seed metal layer 12. The thickness of the plated metal layer 13 may be greater than the sum of the thicknesses of the seed metal layer 12 and the barrier metal layer 11.

[0048] The molded member 40 can be configured to surround the outer surface 13c of the metal-plated layer 13. The outer surface 13c can be a surface connecting the outer edges of the first surface 13a and the second surface 13b of the metal-plated layer 13. The first surface 13a of the metal-plated layer 13 can be the surface on which the first semiconductor chip 21 is mounted, and the second surface 13b of the metal-plated layer 13 can be the surface opposite to the first surface 13a. The second surface 13b of the metal-plated layer 13 can be the surface that is set to be farther from the first semiconductor chip 21 than the first surface 13a and contacts the seed metal layer 12.

[0049] The side surface of the molded member 40 can be the surface that is cut in the sawing process for individuating the semiconductor package 1A. On the side surface of the molded member 40, only the barrier metal layer 11 and the seed metal layer 12 of the heat dissipation member 10 may be provided, and the metal-plated layer 13 may not be provided. Since the metal-plated layer 13 having a relatively large thickness is not provided on the surface cut in the sawing process, the stress applied to the material during the sawing process can be reduced, and the occurrence of burrs can be alleviated, suppressed, or prevented.

[0050] Figures 4 to 11 is a diagram showing a manufacturing method of a semiconductor package according to an embodiment of the disclosed technology.

[0051] Refer to Figure 4 , and a carrier substrate 100 is provided.

[0052] Process steps for manufacturing a semiconductor package according to an embodiment of the disclosed technology can be performed on the carrier substrate 100. The carrier substrate 100 can be used as a workbench, a processing wafer, or a support substrate.

[0053] The carrier substrate 100 can be made of glass, silicon (Si), or metal. The carrier substrate 100 can have a circular shape such as a wafer.

[0054] A release layer 110 can be provided on the carrier substrate 100. The release layer 110 can be made of a material having an adhesive force, and its adhesive force can be reduced by at least one of chemical treatment and optical treatment. The carrier substrate 100 can be made of a transparent material.

[0055] Refer to Figure 5 , and perform the step of forming the heat dissipation member 10P.

[0056] The heat dissipation member 10P can be Figure 6 a pre-structure of the heat dissipation member 10 of . The process for forming the heat dissipation member 10P can include forming a barrier metal layer 11 on the release layer 110, forming a seed metal layer 12 on the barrier metal layer 11, forming a mask layer PR having a mesh-shaped open area on the seed metal layer 12, and forming a metal-plated layer 13 on the seed metal layer 12 by a plating process.

[0057] A barrier metal layer 11 and a seed metal layer 12 can be formed on an installation region MR and a peripheral region ER. The barrier metal layer 11 can include a metal having a different ionization tendency from the metals included in the seed metal layer 12 and the plated metal layer 13. The barrier metal layer 11 can include a metal having a smaller ionization tendency than the metals included in the seed metal layer 12 and the plated metal layer 13. For example, the seed metal layer 12 and the plated metal layer 13 can include copper (Cu), and the barrier metal layer 11 can include at least one of titanium (Ti), titanium tungsten (TiW), and nickel (Ni). The barrier metal layer 11 and the seed metal layer 12 can be formed using electroless plating, evaporation, or sputtering, but are not limited thereto.

[0058] The mask layer PR can include a plurality of patterns separated by a mesh-like open area. The mask layer PR is patterned to provide an open area that serves as a template for the plated metal layer 13. The mask layer PR can cover the peripheral region ER so that the plated metal layer 13 is not formed in the peripheral region ER.

[0059] Through a plating process, a plated metal layer 13 is formed on the seed metal layer 12 exposed through the open area of the mask layer PR. The plating process can use an electroless plating process or an electroplating process, but is not limited thereto. The plated metal layer 13 can have the same layout structure as the open area of the mask layer PR. Since a plurality of through holes OP corresponding to the plurality of patterns configuring the mask layer PR are formed in the plated metal layer 13, the plated metal layer 13 can have a mesh-like layout structure.

[0060] In the drawings of this specification, the thickness of the plated metal layer 13 is shown to be similar to the sum of the thicknesses of the barrier metal layer 11 and the seed metal layer 12. However, the thicknesses of the barrier metal layer 11 and the seed metal layer 12 are shown exaggeratedly, and the thickness of the plated metal layer 13 is greater than the sum of the thicknesses of the barrier metal layer 11 and the seed metal layer 12.

[0061] In the process of forming the plated metal layer 13, a reference mark PM can be additionally formed together with the plated metal layer 13. The reference mark PM can be formed by patterning the mask layer PR to further include an opening area that serves as a template for the reference mark PM and using the plating process for forming the plated metal layer 13. In addition, for example, the reference mark PM can be formed separately from the plated metal layer 13. The reference mark can be formed on the seed metal layer 12 before or after forming the plated metal layer 13.

[0062] The mask layer PR can be formed using a photoresist and can be removed after forming the plated metal layer 13.

[0063] Refer to Figure 6 and perform the step of selectively removing the portions of the barrier metal layer 11 and the seed metal layer 12 that are outside the plated metal layer 13.

[0064] The metal plating layer 13 is used as an etching mask to etch the barrier metal layer 11 and the seed metal layer 12. Therefore, the barrier metal layer 11 and the seed metal layer 12 can have substantially the same layout structure as the metal plating layer 13. The barrier metal layer 11 and the seed metal layer 12 can be disposed in the mounting region MR, and the barrier metal layer 11 and the seed metal layer 12 in the peripheral region ER can be removed. The barrier metal layer 11 and the seed metal layer 12 can have a mesh layout structure. Thus, a heat dissipation member 10 having a structure in which the barrier metal layer 11, the seed metal layer 12, and the metal plating layer 13 are stacked is formed.

[0065] Refer to Figure 7 , and the steps of disposing the first semiconductor chip 21 to the fourth semiconductor chip 24 on the heat dissipation member 10 can be performed.

[0066] A chip mounter (not shown) used in the process of disposing the first semiconductor chip 21 to the fourth semiconductor chip 24 can identify a reference mark PM (refer to Figure 6 ) before disposing the first semiconductor chip 21 to the fourth semiconductor chip 24, and can determine the positions where the first semiconductor chip 21 to the fourth semiconductor chip 24 should be disposed by using the identified reference mark PM (refer to Figure 6 ) as a reference point (for example, a zero point). Therefore, the first semiconductor chip 21 to the fourth semiconductor chip 24 can be accurately disposed at the expected positions.

[0067] Each of the first semiconductor chip 21 to the fourth semiconductor chip 24 can be attached to a semiconductor chip (one of 21 to 23) or the heat dissipation member 10 located directly below it by using an adhesive layer (one of 61 to 64).

[0068] The first semiconductor chip 21 to the fourth semiconductor chip 24 can be stacked with offsets from each other to expose the chip pads 21A to 24A. For example, the intermediate second semiconductor chip 22 and the third semiconductor chip 23 can be stacked with an offset in a first offset direction D1 with respect to the lowermost first semiconductor chip 21, and the uppermost fourth semiconductor chip 24 can be stacked with an offset in a second offset direction D2 opposite to the first offset direction D1.

[0069] Since the fourth semiconductor chip 24 is stacked with an offset in a second offset direction D2 opposite to the first offset direction D1 which is the offset direction of the second semiconductor chip 22 and the third semiconductor chip 23, the layout area occupied by the first semiconductor chip 21 to the fourth semiconductor chip 24 can be reduced.

[0070] Refer to Figure 8 , and the steps of forming the first vertical connector 31 to the fourth vertical connector 34 and the molding member 40 are performed.

[0071] The first vertical connector 31 to the fourth vertical connector 34 may be formed of a conductive metal material such as gold (Au) or copper (Cu). The first vertical connector 31 to the fourth vertical connector 34 may be configured with interconnecting members that extend substantially vertically or substantially perpendicularly upright from the surfaces of the chip pads 21A to 24A of the first semiconductor chip 21 to the fourth semiconductor chip 24.

[0072] The first vertical connector 31 to the fourth vertical connector 34 respectively connected to the first semiconductor chip 21 to the fourth semiconductor chip 24 may be formed by a wire bonding process using a wire bonding device (not shown). Alternatively, the first vertical connector 31 to the third vertical connector 33 connected to the first semiconductor chip 21 to the third semiconductor chip 23 may be formed by a wire bonding process using a wire bonding device, and the fourth vertical connector 34 connected to the fourth semiconductor chip 24 may be formed by a bump forming process. That is, conductive bumps may be formed on the chip pad 24A of the uppermost fourth semiconductor chip 24 without forming bonding wires. The conductive bumps may include copper (Cu).

[0073] The molding member 40 may be formed to cover and encapsulate the first semiconductor chip 21 to the fourth semiconductor chip 24 and the first vertical connector 31 to the fourth vertical connector 34, cover one surface of the heat dissipation member 10, and fill the through holes OP of the heat dissipation member 10.

[0074] The molding member 40 may be formed by a molding process using a liquid sealant. The molding process may include mounting a carrier substrate 100 provided with the first semiconductor chip 21 to the fourth semiconductor chip 24 and the first vertical connector 31 to the fourth vertical connector 34 in a mold (not shown), pouring a liquid sealant into the mold, pressing the mold, and curing the poured sealant. The sealant may include EMC (epoxy molding compound).

[0075] Refer to Figure 9 , a thinning process for reducing the thickness of the molding member 40 may be performed.

[0076] The thinning process may include chemical mechanical polishing (CMP) or a grinding process. The upper surface of the molding member 40 may be lowered by the thinning process. As a result of performing the thinning process, the first vertical connector 31 to the fourth vertical connector 34 may be exposed on the upper surface of the molding member 40.

[0077] Refer to Figure 10 , a step of forming a redistribution layer 50 may be performed.

[0078] The redistribution layer 50 may include redistribution lines 51 and a dielectric layer 52 that insulates the redistribution lines 51 from each other. Some of the redistribution lines 51 may be connected to the first vertical connector 31 to the fourth vertical connector 34.

[0079] Referring to Figure 11 , steps of attaching external connection terminals 70, separating a carrier substrate 100, and individualizing the semiconductor package 1 can be performed.

[0080] Although not shown in detail, some of the redistribution lines 51 may include ball bond areas. The dielectric layer 52 may include openings exposing the ball bond areas. The external connection terminals 70 may be attached to the ball bond areas. The external connection terminals 70 may include solder balls.

[0081] After reducing the adhesion of the release layer 110 using at least one of chemical treatment and optical treatment, the carrier substrate 100 can be removed and separated.

[0082] Thereafter, the redistribution layer 50 and the molding member 40 can be cut along a sawing line defined in the peripheral region ER by a sawing process. Since the heat dissipation member 10 is not present in the peripheral region ER, the stress applied to the material during the sawing process can be reduced, and the occurrence of burrs can be alleviated or suppressed to obtain a clean cut surface.

[0083] Although some embodiments of the present disclosure have been described for illustrative purposes, those skilled in the art will understand that various modifications, additions, and / or substitutions are possible without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed above and in the drawings should be considered only in a descriptive sense and not for limiting the technical scope. The technical scope of the present disclosure is not limited by the presented embodiments and drawings.

[0084] Cross - reference to related applications

[0085] This application claims the priority of Korean Patent Application No. 10 - 2023 - 0161079, filed with the Korean Intellectual Property Office on November 20, 2023, which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor package, comprising: a heat dissipation member having a plurality of through holes passing through a first surface of the heat dissipation member; a semiconductor chip disposed on the first surface of the heat dissipation member; a vertical connector connected to the semiconductor chip; a molding member that seals the semiconductor chip, seals the vertical connector, and fills the plurality of through holes; as well as A redistribution layer is disposed on the molding member.

2. The semiconductor package according to claim 1, wherein The heat dissipation member includes a material having a larger Young's modulus than that of the molding member.

3. The semiconductor package according to claim 1, wherein: The molding member includes epoxy molding compound, and wherein the heat dissipation member includes metal.

4. The semiconductor package according to claim 1, wherein: The heat dissipation component comprises: Barrier metal layer; a seed metal layer disposed on the barrier metal layer; and A metal plating layer is disposed on the seed metal layer, and an upper surface of the metal plating layer opposite to the seed metal layer defines the first surface.

5. The semiconductor package according to claim 4, wherein: The barrier metal layer includes a metal having a lower ionization tendency than the plated metal layer.

6. The semiconductor package according to claim 4, wherein: The barrier metal layer includes at least one of titanium Ti, titanium tungsten TiW and nickel Ni, and The plated metal layer includes copper (Cu).

7. The semiconductor package according to claim 4, wherein: The plurality of vias pass through the barrier metal layer, the seed metal layer, and the plated metal layer.

8. The semiconductor package according to claim 7, further comprising: A reference mark is arranged at the same height level as the metallization layer.

9. The semiconductor package according to claim 8, wherein: The reference mark is formed of the same material as the metallization layer.

10. The semiconductor package according to claim 4, wherein The plurality of vias pass through the plated metal layer, do not pass through the seed metal layer, and do not pass through the barrier metal layer.

11. The semiconductor package according to claim 4, wherein: The thickness of the plated metal layer is greater than the sum of the thickness of the seed metal layer and the thickness of the barrier metal layer.

12. The semiconductor package according to claim 1, wherein The molding member does not cover a second surface of the heat dissipating member opposite to the first surface.

13. The semiconductor package according to claim 1, wherein The heat dissipation member includes the first surface, a second surface opposite to the first surface, and an outer side surface connecting an outer edge of the first surface and an outer edge of the second surface, and The molding member surrounds the outer side surface of the heat dissipation member.

14. The semiconductor package according to claim 1, wherein: The molding member includes a plurality of protrusions filling the plurality of through holes, and Wherein, side surfaces of the plurality of protrusions contact an inner side surface of the heat dissipation member defined by the plurality of through holes.

15. The semiconductor package according to claim 1, wherein The semiconductor chip is attached to the heat dissipation member through an adhesive layer.

16. A method for manufacturing a semiconductor package, the method comprising the steps of: forming a heat dissipation member having a plurality of through holes on a carrier substrate; Arranging a semiconductor chip on the heat dissipation component; forming a vertical connector connected to the semiconductor chip; forming a molding member that seals the semiconductor chip and the vertical connector and fills the plurality of through holes; as well as A redistribution layer is formed on the molding member.

17. The method according to claim 16, wherein: The heat dissipation member includes a material having a larger Young's modulus than that of the molding member.

18. The method according to claim 16, wherein: The molding member includes epoxy molding compound, and the heat dissipation member includes metal.

19. The method according to claim 16, wherein: The step of forming the heat dissipation member comprises the following steps: forming a barrier metal layer on the carrier substrate; forming a seed metal layer on the barrier metal layer; forming a mask pattern having mesh-shaped opening regions on the seed metal layer; and A plated metal layer is formed on the seed metal layer exposed by the mask pattern.

20. The method according to claim 19, wherein: The barrier metal layer includes a metal having a lower ionization tendency than the plated metal layer.

21. The method according to claim 19, wherein: The barrier metal layer includes at least one of titanium Ti, titanium tungsten TiW and nickel Ni, and The plated metal layer includes copper (Cu).

22. The method according to claim 19, further comprising the steps of: After forming the metallization layer, removing the mask pattern; as well as The seed metal layer and the barrier metal layer are etched using the plated metal layer as an etch mask.

23. The method according to claim 19, further comprising the steps of: A reference mark is additionally formed on the seed metal layer.

24. The method according to claim 23, wherein: The step of forming the metallization layer includes the step of forming the reference mark together with the metallization layer.

25. The method according to claim 23, wherein: The step of arranging the semiconductor chip includes the step of determining the position of the semiconductor chip using the fiducial mark as a reference point.

26. The method according to claim 16, further comprising the steps of: After forming the redistribution layer, removing the carrier substrate; and The redistribution layer and the molding member are cut along sawing lines.

27. The method according to claim 26, wherein: The heat dissipation member includes a first surface on which the semiconductor chip is disposed, a second surface opposite to the first surface, and an outer side surface connecting an outer edge of the first surface and an outer edge of the second surface, and The sawing line is disposed outside the outer side surface of the heat dissipation member.

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