Packaging structure and preparation method thereof

Abstract

The invention provides a packaging structure and a preparation method thereof. The packaging structure comprises a glass substrate, a glass adapter plate and a chip, the glass substrate comprises a first glass core plate, the glass adapter plate comprises a second glass core plate, and the substrate connecting layer close to the second surface of the first glass core plate is electrically connected with the glass adapter plate; the adapter plate connecting layer close to the third surface of the second glass core plate is electrically connected with the glass substrate, and the adapter plate connecting layer close to the fourth surface of the second glass core plate is effectively and electrically connected with the chip. The core plates of the glass substrate and the glass adapter plate are made of glass, so that the material cost is reduced, the warping problem is effectively reduced, the plate surfaces of the substrate and the adapter plate are smooth and consistent, and the electric connection reliability of the substrate and the adapter plate is improved; and meanwhile, the passive device is embedded in the glass substrate, so that the surface space of the substrate is released, the space utilization rate of the packaging structure is improved, and the mounting density of the integrated chip is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor integrated circuit manufacturing, and particularly relates to a packaging structure and a preparation method thereof. Background Art

[0002] With the rapid development of the semiconductor industry, the number of I / O (input / output) pins on a chip has increased sharply. As the connection bridge between the chip and the printed circuit board, the packaging substrate is required to have a higher wiring density, more stringent control of board surface expansion and warping. Traditional packaging substrates can no longer meet the industry's needs. Therefore, there is an urgent need for a method to solve the problem of mismatched interconnection performance between the packaging substrate and the chip.

[0003] One of the solutions to the above problems is to add a higher-performance silicon-based interposer between the packaging substrate and the integrated chip. As the bridge between the packaging substrate and the integrated chip, one side of the silicon-based interposer is connected to the integrated chip, and the other side is connected to the packaging substrate. The high flatness of the silicon-based material is beneficial to improving the interconnection reliability between the interposer and the integrated chip. However, due to its material properties, the silicon-based interposer requires a higher cost, which is also a severe test for enterprises. At the same time, during the manufacturing process of traditional packaging substrates, due to the different thermal expansion coefficients of each layer of material, after thermal process lamination, the packaging substrate is prone to warping problems. Excessive substrate warping usually leads to poor contact between the substrate and the interposer or the solder joints on the circuit board during packaging, or some solder pads on the substrate cannot contact the solder during wave soldering and cannot be soldered, seriously affecting the reliability of the product.

[0004] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solutions of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well-known to those skilled in the art just because these solutions are described in the background art part of the present application. Summary of the Invention

[0005] In view of the above disadvantages of the prior art, the purpose of the present invention is to provide a packaging structure and a preparation method thereof, which are used to solve the problem of poor contact between the packaging substrate and the interposer caused by warping of the packaging substrate in the prior art.

[0006] To achieve the above purpose, the present invention provides a packaging structure, which includes: a glass substrate, a glass interposer, and a chip;

[0007] The glass substrate includes a first glass core board, a substrate interconnection layer, and a substrate connection layer;

[0008] The glass interposer includes a second glass core board, an interposer interconnection layer, and an interposer connection layer;

[0009] The first glass core board includes a first surface and a second surface which are oppositely arranged. Substrate interconnection layers are provided on both the first surface and the second surface of the first glass core board. Substrate connection layers are provided on both the substrate interconnection layers. The substrate connection layer close to the second surface forms an effective electrical connection with the glass adapter board;

[0010] The second glass core board includes a third surface and a fourth surface which are oppositely arranged. Adapter board interconnection layers are provided on both the third surface and the fourth surface of the second glass core board. Adapter board connection layers are provided on both the adapter board interconnection layers. The adapter board connection layer close to the third surface forms an effective electrical connection with the glass substrate, and the adapter board connection layer close to the fourth surface forms an effective electrical connection with the chip.

[0011] Optionally, the first glass core board and / or the second glass core board is one of non-alkali glass, alkaline glass, aluminum oxide glass, borosilicate glass or quartz glass.

[0012] Optionally, the thermal expansion coefficient of the first glass core board and / or the second glass core board is 1 ppm / °C - 10 ppm / °C, and the thermal conductivity of the first glass core board and / or the second glass core board is 1 W / m·K - 5 W / m·K.

[0013] Optionally, the thickness of the first glass core board is 0.4 mm - 0.8 mm, and the thickness of the second glass core board is 0.1 mm - 0.2 mm.

[0014] Optionally, a first groove is provided on the second surface of the first glass core board, and a passive device is provided in the first groove. The passive device forms an effective electrical connection with the substrate interconnection layer.

[0015] Optionally, the substrate interconnection layer includes multiple layers of patterned substrate circuit layers and multiple layers of substrate dielectric layers. The gaps between each layer of patterned substrate circuit layers are filled with substrate dielectric layers, and adjacent substrate circuit layers are electrically connected through the substrate dielectric layers; and / or the adapter board interconnection layer includes multiple layers of patterned adapter board circuit layers and multiple layers of adapter board dielectric layers. The gaps between each layer of patterned adapter board circuit layers are filled with adapter board dielectric layers, and adjacent adapter board circuit layers are electrically connected through the adapter board dielectric layers.

[0016] Optionally, each layer of substrate circuit layer includes a substrate seed layer and a substrate conductive layer, and each layer of adapter board circuit layer includes an adapter board seed layer and an adapter board conductive layer.

[0017] The present invention also provides a method for preparing a packaging structure. The preparation method is used to prepare any one of the above-mentioned packaging structures, and the preparation method includes:

[0018] Provide a glass substrate, the glass substrate comprising a first glass core board;

[0019] Provide a glass interposer, the glass interposer comprising a second glass core board;

[0020] Form an effective electrical connection between one side of the glass substrate and the glass interposer;

[0021] Form an effective electrical connection between the other side of the glass interposer and a chip.

[0022] Optionally, the method for preparing the glass substrate is as follows:

[0023] Provide a first glass core board, the first glass core board comprising a first surface and a second surface disposed opposite to each other;

[0024] Provide a first through hole and a first groove on the second surface of the first glass core board, the first through hole penetrating the first glass core board, and the first groove not penetrating the first glass core board;

[0025] Wrap a first substrate seed layer on all surfaces of the first glass core board that are exposed;

[0026] Provide a patterned first substrate photosensitive layer on the first substrate seed layer on the first surface and the second surface of the first glass core board;

[0027] Fill a first substrate conductive layer in the gaps between the patterned first substrate photosensitive layers, and the first substrate conductive layer also fills the first through hole;

[0028] Remove the first substrate photosensitive layer and the first substrate seed layer below the first substrate photosensitive layer, and the patterned first substrate conductive layer and the first substrate seed layer constitute a patterned first substrate circuit layer;

[0029] Provide a passive device in the first groove;

[0030] Provide a patterned substrate dielectric layer on the first substrate circuit layer, and the gaps between the patterned substrate dielectric layers expose partial conductive connection points of the first substrate circuit layer and the passive device;

[0031] Provide a second substrate seed layer on the patterned substrate dielectric layer, and the second substrate seed layer covers the exposed substrate dielectric layer, the first substrate circuit layer, and the conductive connection points of the passive device;

[0032] Provide a patterned second substrate photosensitive layer on the first substrate seed layer;

[0033] Fill the gap between the patterned photosensitive layer of the second substrate with a second substrate conductive layer, and the second substrate conductive layer forms an effective electrical connection with the first substrate circuit layer exposed by the substrate dielectric layer through the second substrate seed layer;

[0034] Remove the second substrate photosensitive layer and the second substrate seed layer under the second substrate photosensitive layer. The patterned second substrate conductive layer and the second substrate seed layer constitute the second substrate circuit layer.

[0035] Optionally, the method for preparing the glass adapter plate is as follows:

[0036] Provide a second glass core plate, the second glass core plate including a third surface and a fourth surface arranged opposite to each other;

[0037] Set a second through hole in the second glass core plate, and the second through hole penetrates the second glass core plate;

[0038] Cover the surface of the second glass core plate with a first adapter plate seed layer, and the first adapter plate seed layer covers the surface of the second through hole;

[0039] Set a patterned first adapter plate photosensitive layer on the first adapter plate seed layer;

[0040] Fill the gap between the patterned first adapter plate photosensitive layer with a first adapter plate conductive layer, and the first adapter plate conductive layer also fills the second through hole;

[0041] Remove the first adapter plate photosensitive layer and the first adapter plate seed layer under the first adapter plate photosensitive layer. The patterned first adapter plate conductive layer and the first adapter plate seed layer constitute a patterned first adapter plate circuit layer;

[0042] Set a patterned adapter plate dielectric layer on the first adapter plate circuit layer, and a part of the first adapter plate circuit layer is exposed in the gap between the patterned adapter plate dielectric layers;

[0043] Set a second adapter plate seed layer on the patterned adapter plate dielectric layer, and the second adapter plate seed layer covers the exposed adapter plate dielectric layer and the first adapter plate circuit layer;

[0044] Set a patterned second adapter plate photosensitive layer on the first adapter plate seed layer;

[0045] Fill the gap between the patterned second adapter plate photosensitive layer with a second adapter plate conductive layer, and the second adapter plate conductive layer forms an effective electrical connection with the first adapter plate circuit layer exposed by the patterned adapter plate dielectric layer through the second adapter plate seed layer;

[0046] Remove the photosensitive layer of the second transfer board and the second transfer board seed layer below the photosensitive layer of the second transfer board. The patterned second transfer board conductive layer and the second transfer board seed layer constitute the second transfer board circuit layer.

[0047] As described above, the packaging structure and its preparation method of the present invention have the following beneficial effects:

[0048] In the present invention, by setting both the glass substrate and the core board of the glass transfer board to be glass, the material cost is reduced, the warping problem is effectively reduced, the plate surfaces of the substrate and the transfer board are flat and consistent, and the electrical connection reliability between the substrate and the transfer board is improved;

[0049] In the present invention, by embedding passive devices in the glass substrate, the surface space of the substrate is released, the space utilization rate of the packaging structure is improved, and the mounting density of the integrated chip is increased. Description of the Drawings

[0050] Figure 1 It shows a schematic structural diagram in the packaging structure of Embodiment 1 of the present invention.

[0051] Figure 2 It shows a schematic structural diagram of providing the first glass core board in an optional example of Step 1 in the preparation method of the packaging structure of Embodiment 2 of the present invention.

[0052] Figure 3 It shows a schematic structural diagram of setting the first through hole and the first groove in an optional example of Step 1 in the preparation method of the packaging structure of Embodiment 2 of the present invention.

[0053] Figure 4 It shows a schematic structural diagram of setting the first substrate seed layer in an optional example of Step 1 in the preparation method of the packaging structure of Embodiment 2 of the present invention.

[0054] Figure 5 It shows a schematic structural diagram of setting the first substrate photosensitive layer in an optional example of Step 1 in the preparation method of the packaging structure of Embodiment 2 of the present invention.

[0055] Figure 6 It shows a schematic structural diagram of setting the first substrate conductive layer in an optional example of Step 1 in the preparation method of the packaging structure of Embodiment 2 of the present invention.

[0056] Figure 7 It shows a schematic structural diagram of removing the first substrate photosensitive layer in an optional example of Step 1 in the preparation method of the packaging structure of Embodiment 2 of the present invention.

[0057] Figure 8 It shows a schematic structural diagram of setting passive devices in an optional example of Step 1 in the preparation method of the packaging structure of Embodiment 2 of the present invention.

[0058] Figure 9 It shows a schematic structural diagram of setting a substrate dielectric layer in an optional example of step 1 in the preparation method of the encapsulation structure of Embodiment 2 of the present invention.

[0059] Figure 10 It shows a schematic structural diagram of setting a second substrate seed layer in an optional example of step 1 in the preparation method of the encapsulation structure of Embodiment 2 of the present invention.

[0060] Figure 11 It shows a schematic structural diagram of setting a second substrate photosensitive layer in an optional example of step 1 in the preparation method of the encapsulation structure of Embodiment 2 of the present invention.

[0061] Figure 12 It shows a schematic structural diagram of setting a second substrate conductive layer in an optional example of step 1 in the preparation method of the encapsulation structure of Embodiment 2 of the present invention.

[0062] Figure 13 It shows a schematic structural diagram of setting a second substrate seed layer in an optional example of step 1 in the preparation method of the encapsulation structure of Embodiment 2 of the present invention.

[0063] Figure 14 It shows a schematic structural diagram of setting a multi-layer substrate dielectric layer and a multi-layer substrate circuit layer in an optional example of step 1 in the preparation method of the encapsulation structure of Embodiment 2 of the present invention.

[0064] Figure 15 It shows a schematic structural diagram of setting a substrate solder mask layer and a substrate surface treatment layer in an optional example of step 1 in the preparation method of the encapsulation structure of Embodiment 2 of the present invention.

[0065] Figure 16 It shows a schematic structural diagram of providing a second glass core board in an optional example of step 2 in the preparation method of the encapsulation structure of Embodiment 2 of the present invention.

[0066] Figure 17 It shows a schematic structural diagram of setting a second through hole in an optional example of step 2 in the preparation method of the encapsulation structure of Embodiment 2 of the present invention.

[0067] Figure 18 It shows a schematic structural diagram of setting a first adapter board seed layer in an optional example of step 2 in the preparation method of the encapsulation structure of Embodiment 2 of the present invention.

[0068] Figure 19 It shows a schematic structural diagram of providing a first adapter board photosensitive layer in an optional example of step 2 in the preparation method of the encapsulation structure of Embodiment 2 of the present invention.

[0069] Figure 20 It shows a schematic structural diagram of providing the conductive layer of the first interposer in an optional example of step 2 in the preparation method of the encapsulation structure according to the second embodiment of the present invention.

[0070] Figure 21 It shows a schematic structural diagram of removing the photosensitive layer of the first interposer in an optional example of step 2 in the preparation method of the encapsulation structure according to the second embodiment of the present invention.

[0071] Figure 22 It shows a schematic structural diagram of setting the interposer dielectric layer in an optional example of step 2 in the preparation method of the encapsulation structure according to the second embodiment of the present invention.

[0072] Figure 23 It shows a schematic structural diagram of setting the seed layer of the second interposer in an optional example of step 2 in the preparation method of the encapsulation structure according to the second embodiment of the present invention.

[0073] Figure 24 It shows a schematic structural diagram of providing the photosensitive layer of the second interposer in an optional example of step 2 in the preparation method of the encapsulation structure according to the second embodiment of the present invention.

[0074] Figure 25 It shows a schematic structural diagram of providing the conductive layer of the second interposer in an optional example of step 2 in the preparation method of the encapsulation structure according to the second embodiment of the present invention.

[0075] Figure 26 It shows a schematic structural diagram of removing the photosensitive layer of the second interposer in an optional example of step 2 in the preparation method of the encapsulation structure according to the second embodiment of the present invention.

[0076] Figure 27 It shows a schematic structural diagram of setting the multi-layer interposer dielectric layer and the multi-layer interposer circuit layer in an optional example of step 2 in the preparation method of the encapsulation structure according to the second embodiment of the present invention.

[0077] Figure 28 It shows a schematic structural diagram of setting the solder mask layer of the interposer in an optional example of step 2 in the preparation method of the encapsulation structure according to the second embodiment of the present invention.

[0078] Figure 29 It shows a schematic structural diagram of setting the surface treatment layer of the interposer in an optional example of step 2 in the preparation method of the encapsulation structure according to the second embodiment of the present invention.

[0079] Figure 30 It shows a schematic structural diagram of setting the temporary protective film in an optional example of step 2 in the preparation method of the encapsulation structure according to the second embodiment of the present invention.

[0080] Figure 31It shows a schematic structural diagram of setting a copper pillar seed layer in an optional example of step 2 in the preparation method of the encapsulation structure according to the second embodiment of the present invention.

[0081] Figure 32 It shows a schematic structural diagram of setting a photosensitive layer of the third interposer in an optional example of step 2 in the preparation method of the encapsulation structure according to the second embodiment of the present invention.

[0082] Figure 33 It shows a schematic structural diagram of setting a copper pillar interconnection layer in an optional example of step 2 in the preparation method of the encapsulation structure according to the second embodiment of the present invention.

[0083] Figure 34 It shows a schematic structural diagram of removing the temporary protective film in an optional example of step 2 in the preparation method of the encapsulation structure according to the second embodiment of the present invention.

[0084] Figure 35 It shows a schematic structural diagram of electrical connection between the glass interposer, the glass substrate and the chip from step 3 to step 4 in the preparation method of the encapsulation structure according to the second embodiment of the present invention.

[0085] Element number description

[0086] 11. First glass core board; 111. First groove; 112. First through hole; 12. Substrate interconnection layer; 121. Substrate circuit layer; 1211. First substrate seed layer; 1212. First substrate photosensitive layer; 1213. First substrate conductive layer; 1214. Second substrate seed layer; 1215. Second substrate photosensitive layer; 1216. Second substrate conductive layer; 122. Substrate dielectric layer; 123. Substrate blind hole; 13. Passive device; 14. Adhesive material layer; 15. Substrate connection layer; 151. Substrate solder mask layer; 152. Substrate surface treatment layer; 153. First solder ball layer; 154. Second solder ball layer; 155. First filling layer;

[0087] 21. Second glass core board; 211. Second through hole; 22. Interposer interconnection layer; 221. Interposer circuit layer; 2211. First interposer seed layer; 2212. First interposer photosensitive layer; 2213. First interposer conductive layer; 2214. Second interposer seed layer; 2215. Second interposer photosensitive layer; 2216. Second interposer conductive layer; 222. Interposer dielectric layer; 223. Interposer blind hole; 23. Interposer connection layer; 231. Interposer solder mask layer; 232. Interposer surface treatment layer; 233. Temporary protective film; 234. Copper pillar seed layer; 235. Photosensitive layer of the third interposer; 236. Copper pillar interconnection layer; 237. Third solder ball layer; 238. Second filling layer;

[0088] 30. Chip. Detailed implementation manners

[0089] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0090] When detailing the embodiments of the present invention, for the convenience of description, the schematic diagrams showing the device structure will be enlarged locally in a non-general proportion, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention here. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0091] For the convenience of description, spatial relationship terms such as "beneath", "below", "lower than", "under", "above", "on" may be used herein to describe the relationship between an element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to encompass other directions of the device in use or operation, in addition to the directions depicted in the drawings.

[0092] In the context of the present application, the structure in which the first feature is "above" the second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0093] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation may be arbitrarily changed, and the component layout type may also be more complex.

[0094] Embodiment 1:

[0095] As Figure 1 shown, the present invention provides a packaging structure, and the packaging structure includes: a glass substrate, a glass interposer, and a chip 30;

[0096] The glass substrate includes a first glass core board 11, a substrate interconnect layer 12, and a substrate connection layer 15;

[0097] The glass interposer includes a second glass core board 21, an interposer interconnect layer 22, and an interposer connection layer 23;

[0098] The first glass core board 11 includes a first surface and a second surface which are oppositely arranged. Substrate interconnection layers 12 are provided on both the first surface and the second surface of the first glass core board 11. Substrate connection layers 15 are provided on the substrate interconnection layers 12. The substrate connection layer 15 close to the second surface forms an effective electrical connection with the glass adapter board;

[0099] The second glass core board 21 includes a third surface and a fourth surface which are oppositely arranged. Adapter board interconnection layers 22 are provided on both the third surface and the fourth surface of the second glass core board 21. Adapter board connection layers 23 are provided on the adapter board interconnection layers 22. The adapter board connection layer 23 close to the third surface forms an effective electrical connection with the glass substrate, and the adapter board connection layer 23 close to the fourth surface forms an effective electrical connection with the chip 30.

[0100] In the present invention, by setting the core boards of the glass substrate and the glass adapter board as glass core boards, and utilizing the characteristics of low cost, high toughness, low thermal expansion coefficient, and good thermal conductivity of the glass material, not only the cost of preparing the adapter board is reduced, but also the warping problem of the packaging substrate is reduced, so that the flatness of the surfaces of the substrate and the adapter board is kept consistent. Thereby, the problem that the solder joints between the substrate and the adapter board are poorly contacted due to warping or it is difficult to solder on the pads due to misalignment of the solder joints can be reduced, greatly improving the electrical interconnection reliability of the packaging substrate and the adapter board, and being beneficial to improving the yield of the packaging structure.

[0101] In one embodiment, the chip 30 is a RAM (Random Access Memory) or / and a CPU (Central Processing Unit), or other different types of chips 30 or their combinations.

[0102] In one embodiment, the first glass core board 11 and / or the second glass core board 21 is one of non-alkali glass, alkaline glass, aluminum oxide glass, borosilicate glass, or quartz glass.

[0103] In one embodiment, the thermal expansion coefficient of the first glass core board 11 and / or the second glass core board 21 is 1 ppm / °C - 10 ppm / °C, and the thermal conductivity of the first glass core board 11 and / or the second glass core board 21 is 1 W / m·K - 5 W / m·K.

[0104] In the present invention, by setting the thermal expansion coefficient and the thermal conductivity of the glass core board, the warping of the glass substrate and the adapter board is further effectively controlled within the range allowed by the yield, so as to ensure the satisfaction of the yield requirements of the product.

[0105] In one embodiment, the thickness of the first glass core board 11 is 0.4 mm - 0.8 mm, and the thickness of the second glass core board 21 is 0.1 mm - 0.2 mm.

[0106] By setting the thickness of the glass core board, the present invention can cooperate with the material of the glass core board to minimize the influence of warping problems on line contact while improving space utilization.

[0107] In one embodiment, a first groove 111 is provided on the second surface of the first glass core board 11, and a passive device 13 is disposed in the first groove 111. The passive device 13 forms an effective electrical connection with the substrate interconnection layer 12.

[0108] By disposing the passive device 13 in the first groove 111 of the first glass core board 11, the present invention buries the passive device 13 in the substrate, thereby releasing the space on the outer surface of the substrate originally used for mounting the passive device 13, so as to improve the space utilization rate of the substrate, increase the mounting density of the integrated chip 30, and further enhance the interconnection performance of the packaging substrate.

[0109] Specifically, the first surface, the second surface, the third surface, and the fourth surface in the present invention are all surfaces for distinguishing and connecting different structures, and there is no other difference on their surfaces.

[0110] In one embodiment, the substrate interconnection layer 12 includes multiple layers of patterned substrate circuit layers 121 and multiple layers of substrate dielectric layers 122. The gaps between each layer of the patterned substrate circuit layers 121 are filled with the substrate dielectric layers 122, and adjacent substrate circuit layers 121 are electrically connected through the substrate dielectric layers 122; and / or the adapter board interconnection layer 22 includes multiple layers of patterned adapter board circuit layers 221 and multiple layers of adapter board dielectric layers 222. The gaps between each layer of the patterned adapter board circuit layers 221 are filled with the adapter board dielectric layers 222, and adjacent adapter board circuit layers 221 are electrically connected through the adapter board dielectric layers 222.

[0111] By providing multiple layers of substrate circuit layers 121 and adapter board circuit layers 221, the present invention can further increase the mounting density of the integrated chip 30, and at the same time maximize the more reliable electrical connection effect achieved by using the glass core board, and increase the density of the interconnection lines.

[0112] In one embodiment, each layer of the substrate circuit layer 121 includes a substrate seed layer and a substrate conductive layer, and each layer of the adapter board circuit layer 221 includes an adapter board seed layer and an adapter board conductive layer.

[0113] By first providing a seed layer in the circuit layer, the present invention enables the conductive layer to fit better with the underlying structural layer, thereby further improving the flatness of the substrate and the adapter board, and further ensuring the interconnection reliability of the substrate.

[0114] Embodiment Two:

[0115] The present invention also provides a method for preparing a packaging structure, which is used to prepare any one of the packaging structures in the first embodiment above. The preparation method includes:

[0116] Step 1: Provide a glass substrate, which includes a first glass core board 11;

[0117] Step 2: Provide a glass adapter board, which includes a second glass core board 21;

[0118] Step 3: Form an effective electrical connection on one side of the glass substrate and the glass adapter board;

[0119] Step 4: Form an effective electrical connection on the other side of the glass adapter board and the chip 30.

[0120] The method for preparing the packaging structure of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the above sequence does not strictly represent the sequence of the method for preparing the packaging structure protected by the present invention, and those skilled in the art can make changes according to the actual preparation steps.

[0121] First, perform Step 1 to provide a glass substrate, which includes a first glass core board 11.

[0122] In one embodiment, the method for preparing the glass substrate is:

[0123] As Figure 2 shown, provide the first glass core board 11, which includes a first surface and a second surface arranged oppositely;

[0124] As Figure 3 shown, provide a first through hole 112 and a first groove 111 on the second surface of the first glass core board 11. The first through hole 112 penetrates through the first glass core board 11, and the first groove 111 does not penetrate through the first glass core board 11;

[0125] As Figure 4 shown, wrap a first substrate seed layer 1211 on all the exposed surfaces of the first glass core board 11;

[0126] As Figure 5 shown, provide a patterned first substrate photosensitive layer 1212 on the first substrate seed layer 1211 on the first surface and the second surface of the first glass core board 11;

[0127] As Figure 6 shown, fill a first substrate conductive layer 1213 in the gaps between the patterned first substrate photosensitive layers 1212, and the first substrate conductive layer 1213 also fills the first through hole 112;

[0128] As shown in Figure 7 the figure, the photosensitive layer 1212 of the first substrate and the first substrate seed layer 1211 under the photosensitive layer 1212 of the first substrate are removed, and the patterned first substrate conductive layer 1213 and the first substrate seed layer 1211 constitute the patterned first substrate circuit layer 121;

[0129] As shown in Figure 8 the figure, a passive device 13 is disposed in the first groove 111;

[0130] As shown in Figure 9 the figure, a patterned substrate dielectric layer 122 is disposed on the first substrate circuit layer 121, and the gaps between the patterned substrate dielectric layers 122 expose the conductive connection points of part of the first substrate circuit layer 121 and the passive device 13;

[0131] As shown in Figure 10 the figure, a second substrate seed layer 1214 is disposed on the patterned substrate dielectric layer 122, and the second substrate seed layer 1214 covers the exposed substrate dielectric layer 122, the first substrate circuit layer 121, and the conductive connection points of the passive device 13;

[0132] As shown in Figure 11 the figure, a patterned second substrate photosensitive layer 1215 is disposed on the first substrate seed layer 1211;

[0133] As shown in Figure 12 the figure, a second substrate conductive layer 1216 is filled in the gaps between the patterned second substrate photosensitive layers 1215, and the second substrate conductive layer 1216 forms an effective electrical connection with the first substrate circuit layer 121 exposed by the patterned substrate dielectric layer 122 through the second substrate seed layer 1214;

[0134] As shown in Figure 13 the figure, the second substrate photosensitive layer 1215 and the second substrate seed layer 1214 under the second substrate photosensitive layer 1215 are removed, and the patterned second substrate conductive layer 1216 and the second substrate seed layer 1214 constitute the second substrate circuit layer 121.

[0135] In the present invention, by disposing the passive device 13 in the first groove 111 of the glass substrate, the passive device 13 is buried in the glass substrate, the space on the outer surface of the glass substrate where the passive device 13 needs to be mounted is released, the space utilization rate of the passive device 13 is improved, and thus the integration density of the integrated chip 30 can be increased.

[0136] In one embodiment, the first groove 111 and the first through hole 112 on the first glass core board 11 are obtained by laser-induced etching.

[0137] In one embodiment, the aperture of the first through-hole 112 is 0.05 mm - 0.15 mm.

[0138] In one embodiment, the first substrate seed layer 1211 and / or the second substrate seed layer 1214 are obtained by electroless copper plating.

[0139] In one embodiment, the first substrate conductive layer 1213 and the second substrate conductive layer 1216 are provided by electroplating.

[0140] In one embodiment, the first substrate seed layer 1211 under the first substrate photosensitive layer 1212 and the second substrate seed layer 1214 under the second substrate photosensitive layer 1215 are removed by flash etching.

[0141] In one embodiment, as Figure 8 shown, after the adhesive material layer 14 is disposed in the first groove 111, the passive device 13 is disposed in the first groove 111.

[0142] In one embodiment, after a DAF (Die Attach Film) material is disposed on the surface of the passive device 13 that fits with the first groove 111, the passive device 13 is disposed in the first groove 111.

[0143] In one embodiment, the thickness of the DAF material is 5 μm - 20 μm.

[0144] In one embodiment, the passive device 13 is any combination of one or more of a capacitor, an inductor, and a resistor.

[0145] In one embodiment, the substrate dielectric layer 122 includes ABF (Ajinomoto Build-up Film) or PID (Photosensitive Insulating Dielectric Layer).

[0146] Specifically, PID includes one of PS (polystyrene), PI (polyimide), PBO (poly-p-phenylene benzobisoxazole fiber), or EPOXY (epoxy resin).

[0147] Specifically, when the substrate dielectric layer 122 is a dry film, the substrate dielectric layer 122 is provided through steps of vacuum laminating, exposure, development, and post-curing; when the substrate dielectric layer 122 is a wet film, the substrate dielectric layer 122 is provided through steps of coating, pre-baking, exposure, development, and post-curing.

[0148] In one embodiment, when forming the patterned second substrate circuit layer 121, as Figure 9As shown, by providing a substrate blind via 123 that penetrates the substrate dielectric layer 122, the first substrate circuit layer 121 can form an effective electrical connection with the second substrate circuit layer 121.

[0149] In one embodiment, laser drilling is performed using carbon dioxide or ultraviolet light to obtain the substrate blind via 123 on the substrate dielectric layer 122.

[0150] In one embodiment, the aperture of the substrate blind via 123 on the substrate dielectric layer 122 is less than or equal to 60 microns.

[0151] In one embodiment, desmear is performed after forming the substrate blind via 123 of the substrate dielectric layer 122.

[0152] In one embodiment, as Figure 14 shown, after forming the second substrate circuit layer 121, the multi-layer substrate dielectric layer 122 and the multi-layer substrate circuit layer 121 are repeatedly provided again to form the substrate interconnection layer 12.

[0153] In one embodiment, as Figure 15 shown, a substrate solder mask layer 151 is filled in the gaps between the patterned substrate conductive layers on the surface of the substrate interconnection layer 12, and only the surface of the substrate interconnection layer 12 that needs to form an effective electrical connection with the outside is exposed.

[0154] In one embodiment, the substrate solder mask layer 151 is solder resist ink.

[0155] In one embodiment, as Figure 15 shown, a substrate surface treatment layer 152 is provided on the part of the substrate conductive layer on the surface of the substrate interconnection layer 12 that needs to be electrically connected to protect the part that needs to be electrically connected from oxidation.

[0156] Then, step 2 is performed to provide a glass interposer, and the glass interposer includes a second glass core board 21.

[0157] In one embodiment, the method for preparing the glass interposer is as follows:

[0158] As Figure 16 shown, a second glass core board 21 is provided, and the second glass core board 21 includes a third surface and a fourth surface that are oppositely arranged;

[0159] As Figure 17 shown, a second through hole 211 is provided in the second glass core board 21, and the second through hole 211 penetrates the second glass core board 21;

[0160] As Figure 18As shown, a first adapter board seed layer 2211 is covered on the surface of the second glass core board 21, and the first adapter board seed layer 2211 covers the surface of the second through hole 211;

[0161] As Figure 19 shown, a patterned first adapter board photosensitive layer 2212 is disposed on the first adapter board seed layer 2211;

[0162] As Figure 20 shown, a first adapter board conductive layer 2213 is filled in the gaps between the patterned first adapter board photosensitive layers 2212, and the first adapter board conductive layer 2213 also fills the second through hole 211;

[0163] As Figure 21 shown, the first adapter board photosensitive layer 2212 and the first adapter board seed layer 2211 under the first adapter board photosensitive layer 2212 are removed, and the patterned first adapter board conductive layer 2213 and the first adapter board seed layer 2211 form a patterned first adapter board circuit layer 221;

[0164] As Figure 22 shown, a patterned adapter board dielectric layer 222 is disposed on the first adapter board circuit layer 221, and the gaps between the patterned adapter board dielectric layers 222 expose a part of the first adapter board circuit layer 221;

[0165] As Figure 23 shown, a second adapter board seed layer 2214 is disposed on the patterned adapter board dielectric layer 222, and the second adapter board seed layer 2214 covers the exposed adapter board dielectric layer 222 and the first adapter board circuit layer 221;

[0166] As Figure 24 shown, a patterned second adapter board photosensitive layer 2215 is disposed on the first adapter board seed layer 2211;

[0167] As Figure 25 shown, a second adapter board conductive layer 2216 is filled in the gaps between the patterned second adapter board photosensitive layers 2215, and the second adapter board conductive layer 2216 forms an effective electrical connection with the first adapter board circuit layer 221 exposed by the second adapter board seed layer 2214 through the second adapter board seed layer 2214;

[0168] As Figure 26 shown, the second adapter board photosensitive layer 2215 and the second adapter board seed layer 2214 under the second adapter board photosensitive layer 2215 are removed, and the patterned second adapter board conductive layer 2216 and the second adapter board seed layer 2214 form the second adapter board circuit layer 221.

[0169] In one embodiment, the second through-hole 211 on the second glass core plate 21 is obtained by laser-induced etching.

[0170] In one embodiment, the aperture of the second through-hole 211 is 0.025 mm - 0.075 mm.

[0171] In one embodiment, the first adapter board seed layer 2211 is obtained by physical vapor deposition (PVD) or wet chemical metallization (PTH).

[0172] In one embodiment, the first adapter board seed layer 2211 includes a titanium layer and a copper layer.

[0173] In one embodiment, the first adapter board conductive layer 2213 and the second adapter board conductive layer 2216 are provided by electroplating.

[0174] In one embodiment, the first adapter board seed layer 2211 under the first adapter board photosensitive layer 2212 and the second adapter board seed layer 2214 under the second adapter board photosensitive layer 2215 are removed by flash etching.

[0175] In one embodiment, adapter board blind holes 223 are provided in the adapter board dielectric layer 222 by coating a photosensitive insulating material, lithography, and development to obtain the patterned adapter board dielectric layer 222, so that the first adapter board circuit layer 221 can form an effective electrical connection with the second adapter board circuit layer 221.

[0176] Specifically, the photosensitive insulating material is PS (polystyrene) or PI (polyimide).

[0177] In one embodiment, the second adapter board conductive layer 2216 is provided by physical vapor deposition (PVD).

[0178] In one embodiment, as Figure 27 shown, after forming the second adapter board circuit layer 221, the multi-layer adapter board dielectric layer 222 and the multi-layer adapter board circuit layer 221 are repeatedly provided again to form the adapter board interconnect layer 22.

[0179] In one embodiment, as Figure 28 shown, the adapter board solder mask layer 231 is filled in the gaps between the patterned adapter board conductive layers on the surface of the adapter board interconnect layer 22, and only the surface of the adapter board interconnect layer 22 that needs to form an effective electrical connection with the outside is exposed.

[0180] In one embodiment, the adapter board solder mask layer 231 is solder mask ink.

[0181] In one embodiment, as Figure 29 shown, a transfer board surface treatment layer 232 is provided on the portion of the transfer board conductive layer on the surface of the transfer board interconnect layer 22 on the fourth surface of the second glass core board 21 to protect the portion to be electrically connected from oxidation.

[0182] In one embodiment, as Figure 30 shown, a temporary protective film 233 is provided on the surface of the transfer board interconnect layer 22 on the fourth surface of the second glass core board 21; as Figure 31 shown, a copper pillar seed layer 234 is covered on the surface of the transfer board interconnect layer 22 on the third surface of the second glass core board 21; as Figure 32 shown, a patterned third transfer board photosensitive layer 235 is provided on the copper pillar seed layer 234; as Figure 33 shown, a copper pillar interconnect layer 236 is filled in the gaps between the patterned third transfer board photosensitive layers 235, and the copper pillar interconnect layer 236 is used to form an effective electrical connection with the chip 30; as Figure 34 shown, the third transfer board photosensitive layer 235 and the copper pillar seed layer 234 under the third transfer board photosensitive layer 235 are removed, and the temporary protective film 233 is removed.

[0183] In one embodiment, the copper pillar seed layer 234 is removed by flash etching.

[0184] In one embodiment, as Figure 35 shown, a first solder ball layer 153 is provided on the surface of the substrate interconnect layer 12 on the first surface of the first glass core board 11, and a second solder ball layer 154 is provided on the surface of the substrate interconnect layer 12 on the second surface of the first glass core board 11, and the second solder ball layer 154 is used to form an effective electrical connection with the glass transfer board; or the second solder ball layer 154 is provided on the surface of the transfer board interconnect layer 22 on the third surface of the second glass core board 21, and no solder ball layer is provided on the surface of the substrate interconnect layer 12 on the first glass core board 11.

[0185] In one embodiment, a first filling layer 155 is filled in the gaps between the second solder ball layers 154 to avoid unwanted electrical connection between the solder balls.

[0186] In one embodiment, as Figure 35 shown, a third solder ball layer 237 is provided on the copper pillar interconnect layer 236, and the third solder ball layer 237 is used to form an effective electrical connection with the chip 30.

[0187] In one case, a second filling layer 238 is filled in the gaps between the third solder ball layers 237 to avoid unwanted electrical connection between the solder balls.

[0188] Next, step 3 is carried out. As Figure 35 shown, an effective electrical connection is formed between one side of the glass substrate and the glass adapter board.

[0189] Finally, step 4 is carried out. As Figure 35 shown, an effective electrical connection is formed between the other side of the glass adapter board and the chip 30.

[0190] In the present invention, by forming an effective electrical connection between the glass substrate using a glass core board and the glass adapter board, the electrical connection points on the glass substrate and the glass adapter board during the preparation process will not cause excessive warping problems of the substrate and the adapter board due to temperature changes during the preparation process, thereby improving the reliability of substrate interconnection.

[0191] In summary, for the packaging structure and its preparation method of the present invention, by setting the core boards of both the glass substrate and the glass adapter board to be glass, the material cost is reduced, the warping problem is effectively reduced, the plate surfaces of the substrate and the adapter board are flat and consistent, and the electrical connection reliability between the substrate and the adapter board is improved; at the same time, by embedding passive devices in the glass substrate, the surface space of the substrate is released, the space utilization rate of the packaging structure is improved, and the mounting density of the integrated chip is increased.

[0192] Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0193] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A packaging structure, characterized in that: The packaging structure includes: a glass substrate, a glass transfer plate and a chip; The glass substrate comprises a first glass core board, a substrate interconnection layer and a substrate connection layer; The glass transfer plate comprises a second glass core plate, a transfer plate interconnection layer and a transfer plate connection layer; The first glass core board comprises a first surface and a second surface which are arranged opposite to each other, a substrate interconnection layer is arranged on the first surface and the second surface of the first glass core board, a substrate connection layer is arranged on the substrate interconnection layer, and the substrate connection layer close to the second surface forms an effective electrical connection with the glass transfer board; The second glass core board includes a third surface and a fourth surface arranged opposite to each other, and a transfer board interconnection layer is arranged on the third surface and the fourth surface of the second glass core board, and a transfer board connection layer is arranged on the transfer board interconnection layer, the transfer board connection layer close to the third surface forms an effective electrical connection with the glass substrate, and the transfer board connection layer close to the fourth surface forms an effective electrical connection with the chip.

2. The packaging structure according to claim 1, characterized in that: The first glass core plate and / or the second glass core plate is one of alkali-free glass, alkali glass, aluminum oxide glass, high borosilicate glass or quartz glass.

3. The packaging structure according to claim 1, characterized in that: The thermal expansion coefficient of the first glass core board and / or the second glass core board is 1 ppm / °C-10 ppm / °C, and the thermal conductivity of the first glass core board and / or the second glass core board is 1 W / m·K-5 W / m·K.

4. The packaging structure according to claim 1, characterized in that: The thickness of the first glass core board is 0.4 mm to 0.8 mm, and the thickness of the second glass core board is 0.1 mm to 0.2 mm.

5. The packaging structure according to claim 1, characterized in that: The second surface of the first glass core board is provided with a first groove, a passive device is arranged in the first groove, and the passive device forms an effective electrical connection with the substrate interconnection layer.

6. The packaging structure according to claim 1, characterized in that: The substrate interconnection layer includes multiple layers of patterned substrate circuit layers and multiple layers of substrate dielectric layers, the gaps between each layer of the patterned substrate circuit layers are filled with substrate dielectric layers, and adjacent substrate circuit layers are electrically connected by penetrating the substrate dielectric layers; and / or the adapter board interconnection layer includes multiple layers of patterned adapter board circuit layers and multiple layers of adapter board dielectric layers, the gaps between each layer of the patterned adapter board circuit layers are filled with adapter board dielectric layers, and adjacent adapter board circuit layers are electrically connected by penetrating the adapter board dielectric layers.

7. The packaging structure according to claim 6, characterized in that: Each substrate circuit layer includes a substrate seed layer and a substrate conductive layer, and each adapter board circuit layer includes an adapter board seed layer and an adapter board conductive layer.

8. A method for preparing a packaging structure, characterized in that: The preparation method is used to prepare the packaging structure according to any one of claims 1 to 7, and the preparation method comprises: Providing a glass substrate, the glass substrate comprising a first glass core board; Providing a glass transition plate, the glass transition plate comprising a second glass core plate; Forming an effective electrical connection between the glass substrate and one side of the glass transfer plate; The other side of the glass transfer plate is effectively electrically connected to the chip.

9. The method for preparing the packaging structure according to claim 8, characterized in that: The method for preparing the glass substrate comprises: providing a first glass core board, wherein the first glass core board comprises a first surface and a second surface which are arranged opposite to each other; A first through hole and a first groove are arranged on the second surface of the first glass core board, wherein the first through hole passes through the first glass core board, and the first groove does not pass through the first glass core board; Wrapping a first substrate seed layer on all exposed surfaces of the first glass core board; A patterned first substrate photosensitive layer is provided on the first substrate seed layer on the first surface and the second surface of the first glass core board; Filling the gaps between the patterned photosensitive layers of the first substrate with a first substrate conductive layer, wherein the first substrate conductive layer also fills the first through hole; The first substrate photosensitive layer and the first substrate seed layer below the first substrate photosensitive layer are removed, and the patterned first substrate conductive layer and the first substrate seed layer form a patterned first substrate circuit layer; Disposing a passive device in the first groove; A patterned substrate dielectric layer is provided on the first substrate circuit layer, and the gaps between the patterned substrate dielectric layers reveal a portion of the conductive connection points between the first substrate circuit layer and the passive device; Disposing a second substrate seed layer on the patterned substrate dielectric layer, wherein the second substrate seed layer covers the exposed substrate dielectric layer, the first substrate circuit layer and the conductive connection points of the passive device; Disposing a patterned second substrate photosensitive layer on the first substrate seed layer; Filling the gaps between the patterned photosensitive layers of the second substrate with a second substrate conductive layer, wherein the second substrate conductive layer forms an effective electrical connection with the first substrate circuit layer exposed by the patterned substrate dielectric layer through the second substrate seed layer; The second substrate photosensitive layer and the second substrate seed layer below the second substrate photosensitive layer are removed, and the patterned second substrate conductive layer and the second substrate seed layer constitute the second substrate circuit layer.

10. The method for preparing the packaging structure according to claim 8, characterized in that: The method for preparing the glass transfer plate is: Providing a second glass core board, the second glass core board comprising a third surface and a fourth surface disposed opposite to each other; A second through hole is provided in the second glass core board, wherein the second through hole passes through the second glass core board; Covering the surface of the second glass core board with a first adapter plate seed layer, wherein the first adapter plate seed layer covers the surface of the second through hole; Disposing a patterned first adapter plate photosensitive layer on the first adapter plate seed layer; Filling the first adapter plate conductive layer in the gaps between the patterned first adapter plate photosensitive layers, wherein the first adapter plate conductive layer also fills the second through hole; The first adapter board photosensitive layer and the first adapter board seed layer below the first adapter board photosensitive layer are removed, and the patterned first adapter board conductive layer and the first adapter board seed layer form a patterned first adapter board circuit layer; A patterned adapter board dielectric layer is provided on the first adapter board circuit layer, and the gaps between the patterned adapter board dielectric layers expose a portion of the first adapter board circuit layer; Disposing a second adapter plate seed layer on the patterned adapter plate dielectric layer, wherein the second adapter plate seed layer covers the exposed adapter plate dielectric layer and the first adapter plate circuit layer; Disposing a patterned second adapter plate photosensitive layer on the first adapter plate seed layer; Filling the second adapter plate conductive layer in the gap between the patterned second adapter plate photosensitive layer, the second adapter plate conductive layer forms an effective electrical connection with the first adapter plate circuit layer exposed by the patterned adapter plate dielectric layer through the second adapter plate seed layer; The second adapter board photosensitive layer and the second adapter board seed layer below the second adapter board photosensitive layer are removed, and the patterned second adapter board conductive layer and the second adapter board seed layer constitute the second adapter board circuit layer.

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