A packaging structure and a method of manufacturing the same

Abstract

This invention provides a packaging structure and its fabrication method. The packaging structure includes a glass substrate, a glass adapter plate, and a chip. The glass substrate includes a first glass core plate, and the glass adapter plate includes a second glass core plate. A substrate connection layer near the second side of the first glass core plate is electrically connected to the glass adapter plate. A adapter plate connection layer near the third side of the second glass core plate is electrically connected to the glass substrate, and a adapter plate connection layer near the fourth side of the second glass core plate forms an effective electrical connection with the chip. This invention reduces material costs and effectively minimizes warpage by using glass for both the glass substrate and the core plate of the glass adapter plate, ensuring a flat and consistent surface between the substrate and the adapter plate, and improving the reliability of the electrical connection between the substrate and the adapter plate. Simultaneously, by embedding passive devices within the glass substrate, it frees up surface space, improves the space utilization of the packaging structure, and increases the mounting density of the integrated chip.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing technology, and in particular relates to a packaging structure and its preparation method. Background Technology

[0002] With the rapid development of the semiconductor industry, the number of I / O (input / output) pins on chips has increased dramatically. As the connection bridge between the chip and the printed circuit board, the packaging substrate is required to have higher wiring density and stricter control over board expansion, contraction, and warpage. Traditional packaging substrates can no longer meet the industry's needs. Therefore, there is an urgent need for a method to solve the problem of mismatch between the interconnect performance of the packaging substrate and the chip.

[0003] Adding a high-performance silicon-based interposer between the packaging substrate and the integrated chip is one solution to the aforementioned problems. The silicon-based interposer acts as a bridge between the packaging substrate and the integrated chip, connecting the integrated chip on one side and the packaging substrate on the other. The high flatness of silicon-based materials helps improve the interconnection reliability between the interposer and the integrated chip. However, silicon-based interposers require higher costs due to their material properties, which poses a significant challenge for companies. Meanwhile, traditional packaging substrates are prone to warping during the manufacturing process due to the different thermal expansion coefficients of the various layers, especially after thermal bonding. Excessive substrate warping often leads to poor solder contact between the substrate and the interposer or circuit board during packaging, or prevents some pads from making solder contact during wave soldering, severely impacting product reliability.

[0004] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating the understanding of those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because these solutions have been described in the background section of this application. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the purpose of the present invention is to provide a packaging structure and its preparation method to solve the problem of poor contact between the packaging substrate and the adapter board caused by the warping of the packaging substrate in the prior art.

[0006] To achieve the above objectives, the present invention provides a packaging structure, the packaging structure comprising: a glass substrate, a glass adapter plate, and a chip;

[0007] The glass substrate includes a first glass core plate, a substrate interconnect layer, and a substrate connection layer;

[0008] The glass transition plate includes a second glass core plate, an interconnecting layer of the transition plate, and a connecting layer of the transition plate;

[0009] The first glass core plate includes a first side and a second side disposed opposite to each other. A substrate interconnect layer is disposed on both the first side and the second side of the first glass core plate. A substrate connection layer is disposed on each of the substrate interconnect layers. The substrate connection layer near the second side forms an effective electrical connection with the glass transition plate.

[0010] The second glass core board includes a third side and a fourth side disposed opposite to each other. A transition board interconnection layer is provided on both the third side and the fourth side of the second glass core board. A transition board connection layer is provided on each of the transition board interconnection layers. The transition board connection layer near the third side forms an effective electrical connection with the glass substrate, and the transition board connection layer near the fourth side forms an effective electrical connection with the chip.

[0011] Optionally, the first glass core board and / or the second glass core board are one of alkali-free glass, alkaline glass, alumina glass, borosilicate glass or quartz glass.

[0012] Optionally, the coefficient of thermal expansion of the first glass core plate and / or the second glass core plate is 1ppm / ℃-10ppm / ℃, and the thermal conductivity of the first glass core plate and / or the second glass core plate is 1W / m·K-5W / m·K.

[0013] Optionally, the thickness of the first glass core plate is 0.4 mm to 0.8 mm, and the thickness of the second glass core plate is 0.1 mm to 0.2 mm.

[0014] Optionally, a first groove is provided on the second surface of the first glass core plate, and a passive device is disposed in the first groove, wherein the passive device forms an effective electrical connection with the substrate interconnect layer.

[0015] Optionally, the substrate interconnect layer includes multiple patterned substrate circuit layers and multiple substrate dielectric layers, with the gaps between each patterned substrate circuit layer filled by the substrate dielectric layer, and adjacent substrate circuit layers being electrically connected through the substrate dielectric layer; and / or the adapter board interconnect layer includes multiple patterned adapter board circuit layers and multiple adapter board dielectric layers, with the gaps between each patterned adapter board circuit layer filled by the adapter board dielectric layer, and adjacent adapter board circuit layers being electrically connected through the adapter board dielectric layer.

[0016] Optionally, each substrate circuit layer includes a substrate seed layer and a substrate conductive layer, and each adapter board circuit layer includes an adapter board seed layer and an adapter board conductive layer.

[0017] The present invention also provides a method for preparing a packaging structure, the method being used to prepare any one of the packaging structures described above, the method comprising:

[0018] A glass substrate is provided, the glass substrate comprising a first glass core plate;

[0019] A glass adapter plate is provided, the glass adapter plate including a second glass core plate;

[0020] An effective electrical connection is formed between the glass substrate and one side of the glass adapter plate;

[0021] The other side of the glass adapter plate is effectively electrically connected to the chip.

[0022] Optionally, the method for preparing the glass substrate is as follows:

[0023] A first glass core panel is provided, the first glass core panel including a first surface and a second surface disposed opposite to each other;

[0024] A first through hole and a first groove are provided on the second side of the first glass core plate. The first through hole penetrates the first glass core plate, and the first groove does not penetrate the first glass core plate.

[0025] The first substrate seed layer is wrapped around all exposed surfaces of the first glass core plate;

[0026] A patterned first substrate photosensitive layer is provided on the first substrate seed layer on both the first and second sides of the first glass core plate.

[0027] The gaps between the patterned first substrate photosensitive layers are filled with a first substrate conductive layer, and the first substrate conductive layer also fills the first via.

[0028] Remove the first substrate photosensitive layer and the first substrate seed layer below the first substrate photosensitive layer, and the patterned first substrate conductive layer and the first substrate seed layer constitute a patterned first substrate circuit layer.

[0029] A passive device is disposed within the first groove;

[0030] A patterned substrate dielectric layer is provided on the first substrate circuit layer, and the gaps between the patterned substrate dielectric layers expose part of the conductive connection points between the first substrate circuit layer and the passive device.

[0031] A second substrate seed layer is disposed on the patterned substrate dielectric layer, the second substrate seed layer covering the exposed substrate dielectric layer, the first substrate circuit layer and the conductive connection points of the passive device.

[0032] A patterned second substrate photosensitive layer is disposed on the seed layer of the first substrate;

[0033] The gaps between the patterned second substrate photosensitive layers are filled with a second substrate conductive layer, and the second substrate conductive layer forms an effective electrical connection with the first substrate circuit layer exposed by the patterned substrate dielectric layer through the second substrate seed layer.

[0034] The second substrate photosensitive layer and the second substrate seed layer below the second substrate photosensitive layer are removed, and the patterned second substrate conductive layer and the second substrate seed layer constitute the second substrate circuit layer.

[0035] Optionally, the method for preparing the glass transition plate is as follows:

[0036] A second glass core panel is provided, the second glass core panel including a third side and a fourth side disposed opposite to each other;

[0037] A second through hole is provided in the second glass core plate, and the second through hole penetrates the second glass core plate;

[0038] A first adapter plate seed layer is covered on the surface of the second glass core plate, and the first adapter plate seed layer covers the surface of the second through hole;

[0039] A patterned first adapter plate photosensitive layer is provided on the first adapter plate seed layer;

[0040] The gaps between the patterned first adapter plate photosensitive layers are filled with the first adapter plate conductive layer, and the first adapter plate conductive layer is also filled with the second through hole.

[0041] Remove the photosensitive layer of the first adapter board and the seed layer of the first adapter board below the photosensitive layer of the first adapter board. The patterned conductive layer of the first adapter board and the seed layer of the first adapter board constitute a patterned circuit layer of the first adapter board.

[0042] A graphical adapter board dielectric layer is provided on the first adapter board circuit layer, and the gaps between the graphical adapter board dielectric layers expose part of the first adapter board circuit layer.

[0043] A second adapter seed layer is provided on the graphical adapter medium layer, the second adapter seed layer covering the exposed adapter medium layer and the first adapter circuit layer;

[0044] A patterned second adapter photosensitive layer is provided on the seed layer of the first adapter plate;

[0045] The gaps between the patterned second adapter plate photosensitive layers are filled with the second adapter plate conductive layer, and the second adapter plate conductive layer forms an effective electrical connection with the first adapter plate circuit layer exposed by the patterned adapter plate dielectric layer through the second adapter plate seed layer.

[0046] Remove the photosensitive layer of the second adapter board and the seed layer of the second adapter board below the photosensitive layer of the second adapter board. The patterned conductive layer of the second adapter board and the seed layer of the second adapter board constitute the circuit layer of the second adapter board.

[0047] As described above, the packaging structure and its preparation method of the present invention have the following beneficial effects:

[0048] This invention reduces material costs and effectively minimizes warping by setting both the core plate of the glass substrate and the glass adapter plate to be glass, making the surfaces of the substrate and the adapter plate flat and consistent, and improving the reliability of the electrical connection between the substrate and the adapter plate.

[0049] This invention improves the space utilization of the packaging structure and increases the mounting density of integrated chips by embedding passive devices inside the glass substrate, thereby freeing up surface space on the substrate. Attached Figure Description

[0050] Figure 1 The diagram shown is a structural schematic of the packaging structure in Embodiment 1 of the present invention.

[0051] Figure 2 The diagram shown is a schematic representation of the structure of the first glass core plate provided in step 1 of the optional example of the preparation method of the encapsulation structure in Embodiment 2 of the present invention.

[0052] Figure 3 The diagram shown is a schematic representation of the structure presented in step 1 of the optional example of the preparation method of the packaging structure in Embodiment 2 of the present invention, which involves setting a first through hole and a first groove.

[0053] Figure 4 The diagram shown is a schematic representation of the structure presented in step 1 of the optional example of the preparation method of the packaging structure in Embodiment 2 of the present invention, which involves setting a seed layer on a first substrate.

[0054] Figure 5 The diagram shown is a schematic representation of the structure presented in step 1 of the optional example of the preparation method of the packaging structure in Embodiment 2 of the present invention, which involves setting the first substrate photosensitive layer.

[0055] Figure 6 The diagram shown is a schematic representation of the structure presented in step 1 of the optional example of the preparation method of the packaging structure in Embodiment 2 of the present invention, which involves setting the first substrate conductive layer.

[0056] Figure 7 The diagram shown is a schematic representation of the structure obtained by removing the photosensitive layer of the first substrate in step 1 of the optional example of the packaging structure preparation method of Embodiment 2 of the present invention.

[0057] Figure 8 The diagram shown is a schematic representation of the structure presented in step 1 of the optional example of the preparation method of the packaging structure in Embodiment 2 of the present invention, where a passive device is set.

[0058] Figure 9 The diagram shown is a schematic representation of the structure presented in step 1 of the optional example of the packaging structure preparation method of embodiment 2 of the present invention, which involves setting a substrate dielectric layer.

[0059] Figure 10 The diagram shown is a schematic representation of the structure presented in step 1 of the optional example of the preparation method of the packaging structure in Embodiment 2 of the present invention, which involves setting a second substrate seed layer.

[0060] Figure 11 The diagram shown is a schematic representation of the structure presented in step 1 of the optional example of the packaging structure preparation method of Embodiment 2 of the present invention, which involves setting a second substrate photosensitive layer.

[0061] Figure 12 The diagram shown is a schematic representation of the structure presented in step 1 of the optional example of the preparation method of the packaging structure in Embodiment 2 of the present invention, which involves setting a second substrate conductive layer.

[0062] Figure 13 The diagram shown is a schematic representation of the structure presented in step 1 of the optional example of the preparation method of the packaging structure in Embodiment 2 of the present invention, which involves setting a second substrate seed layer.

[0063] Figure 14 The diagram shown is a schematic representation of the structure presented in step 1 of the optional example of the packaging structure preparation method of Embodiment 2 of the present invention, which involves setting a multilayer substrate dielectric layer and a multilayer substrate circuit layer.

[0064] Figure 15 The diagram shown is a schematic representation of the structure presented in step 1 of the optional example of the packaging structure preparation method of Embodiment 2 of the present invention, which involves setting a substrate solder resist layer and a substrate surface treatment layer.

[0065] Figure 16 The diagram shown is a schematic representation of the structure of the second glass core plate provided in step 2 of the optional example of the preparation method of the encapsulation structure in Embodiment 2 of the present invention.

[0066] Figure 17 The diagram shown is a schematic representation of the structure presented in step 2 of the optional example of the preparation method of the packaging structure in Embodiment 2 of the present invention, which involves setting a second through hole.

[0067] Figure 18 The diagram shown is a schematic representation of the structure presented in step 2 of the optional example of the preparation method of the packaging structure in Embodiment 2 of the present invention, which shows the setting of the seed layer of the first adapter plate.

[0068] Figure 19 The diagram shown is a schematic representation of the structure of the first adapter plate photosensitive layer provided in step 2 of the optional example of the preparation method of the packaging structure in Embodiment 2 of the present invention.

[0069] Figure 20 The diagram shown is a schematic representation of the structure of the first adapter plate conductive layer provided in step 2 of the optional example of the preparation method of the packaging structure of Embodiment 2 of the present invention.

[0070] Figure 21 The diagram shown is a schematic representation of the structure obtained by removing the photosensitive layer of the first adapter plate in step 2 of the optional example of the preparation method of the packaging structure in Embodiment 2 of the present invention.

[0071] Figure 22 The diagram shown is a schematic representation of the structure presented in step 2 of the optional example of the preparation method of the packaging structure in Embodiment 2 of the present invention, which involves setting the dielectric layer of the adapter plate.

[0072] Figure 23 The diagram shown is a schematic representation of the structure presented in step 2 of the optional example of the preparation method of the packaging structure in Embodiment 2 of the present invention, which involves setting a seed layer for a second adapter plate.

[0073] Figure 24 The diagram shown is a schematic representation of the structure of the second adapter plate photosensitive layer provided in step 2 of the optional example of the preparation method of the packaging structure in Embodiment 2 of the present invention.

[0074] Figure 25 The diagram shown is a schematic representation of the structure of the conductive layer of the second adapter plate provided in step 2 of the optional example of the preparation method of the packaging structure of Embodiment 2 of the present invention.

[0075] Figure 26 The diagram shown is a schematic representation of the structure obtained by removing the photosensitive layer of the second adapter plate in step 2 of the optional example of the preparation method of the packaging structure in Embodiment 2 of the present invention.

[0076] Figure 27 The diagram shown is a schematic representation of the structure presented in step 2 of the optional example of the packaging structure preparation method of Embodiment 2 of the present invention, which involves setting up a multilayer adapter plate dielectric layer and a multilayer adapter plate circuit layer.

[0077] Figure 28 The diagram shown is a schematic representation of the structure presented in step 2 of the optional example of the preparation method of the packaging structure of Embodiment 2 of the present invention, which involves setting the solder mask layer of the adapter board.

[0078] Figure 29 The diagram shown is a schematic representation of the structure presented in step 2 of the optional example of the preparation method of the packaging structure in Embodiment 2 of the present invention, which involves setting the surface treatment layer of the adapter plate.

[0079] Figure 30 The diagram shown is a schematic representation of the structure presented in step 2 of the optional example of the preparation method of the encapsulation structure in Embodiment 2 of the present invention, which involves setting a temporary protective film.

[0080] Figure 31The diagram shown is a schematic representation of the structure presented in step 2 of the optional example of the preparation method of the encapsulation structure in Embodiment 2 of the present invention, which involves setting a copper pillar seed layer.

[0081] Figure 32 The diagram shown is a schematic representation of the structure presented in step 2 of the optional example of the preparation method of the packaging structure in Embodiment 2 of the present invention, which involves setting a third adapter plate photosensitive layer.

[0082] Figure 33 The diagram shown is a schematic representation of the structure presented in step 2 of the optional example of the packaging structure preparation method of Embodiment 2 of the present invention, which involves setting a copper pillar interconnect layer.

[0083] Figure 34 The diagram shown is a schematic representation of the structure obtained by removing the temporary protective film in step 2 of the optional example of the preparation method of the encapsulation structure in Embodiment 2 of the present invention.

[0084] Figure 35 The diagram shows the structure of the glass adapter plate, glass substrate, and chip electrical connection in steps 3 to 4 of the preparation method of the packaging structure in Embodiment 2 of the present invention.

[0085] Component designation explanation

[0086] 11. First glass core board; 111. First groove; 112. First through hole; 12. Substrate interconnect layer; 121. Substrate circuit layer; 1211. First substrate seed layer; 1212. First substrate photosensitive layer; 1213. First substrate conductive layer; 1214. Second substrate seed layer; 1215. Second substrate photosensitive layer; 1216. Second substrate conductive layer; 122. Substrate dielectric layer; 123. Substrate blind via; 13. Passive device; 14. Adhesive material layer; 15. Substrate connection layer; 151. Substrate solder resist layer; 152. Substrate surface treatment layer; 153. First solder ball layer; 154. Second solder ball layer; 155. First filler layer;

[0087] 21. Second glass core board; 211. Second through-hole; 22. Interconnect layer of adapter board; 221. Circuit layer of adapter board; 2211. Seed layer of first adapter board; 2212. Photosensitive layer of first adapter board; 2213. Conductive layer of first adapter board; 2214. Seed layer of second adapter board; 2215. Photosensitive layer of second adapter board; 2216. Conductive layer of second adapter board; 222. Dielectric layer of adapter board; 223. Blind via of adapter board; 23. Connection layer of adapter board; 231. Solder mask layer of adapter board; 232. Surface treatment layer of adapter board; 233. Temporary protective film; 234. Seed layer of copper pillar; 235. Photosensitive layer of third adapter board; 236. Interconnect layer of copper pillar; 237. Third solder ball layer; 238. Second filler layer;

[0088] 30. Chip. Detailed Implementation

[0089] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0090] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0091] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the accompanying drawings for devices in use or operation.

[0092] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0093] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0094] Example 1:

[0095] like Figure 1 As shown, the present invention provides a packaging structure, the packaging structure comprising: a glass substrate, a glass adapter plate, and a chip 30;

[0096] The glass substrate includes a first glass core plate 11, a substrate interconnect layer 12, and a substrate connection layer 15;

[0097] The glass transition plate includes a second glass core plate 21, a transition plate interconnection layer 22, and a transition plate connection layer 23;

[0098] The first glass core plate 11 includes a first side and a second side disposed opposite to each other. A substrate interconnect layer 12 is disposed on both the first side and the second side of the first glass core plate 11. A substrate connection layer 15 is disposed on each of the substrate interconnect layers 12. The substrate connection layer 15 near the second side forms an effective electrical connection with the glass transition plate.

[0099] The second glass core board 21 includes a third side and a fourth side disposed opposite to each other. A transition board interconnection layer 22 is provided on both the third side and the fourth side of the second glass core board 21. A transition board connection layer 23 is provided on each of the transition board interconnection layers 22. The transition board connection layer 23 near the third side forms an effective electrical connection with the glass substrate, and the transition board connection layer 23 near the fourth side forms an effective electrical connection with the chip 30.

[0100] This invention uses a glass core board for both the glass substrate and the glass adapter board. By leveraging the low cost, high toughness, low coefficient of thermal expansion, and good thermal conductivity of glass, this invention not only reduces the cost of manufacturing the adapter board but also minimizes warpage of the packaging substrate. This ensures consistent flatness between the substrate and the adapter board, reducing issues such as poor solder joint contact caused by warpage or difficulty in soldering on the pads due to misaligned solder joints. This significantly improves the electrical interconnect reliability between the packaging substrate and the adapter board, thereby increasing the yield of the packaging structure.

[0101] In one embodiment, the chip 30 is RAM (random access memory) and / or CPU (central processing unit), or other different types of chips 30 or combinations thereof.

[0102] In one embodiment, the first glass core plate 11 and / or the second glass core plate 21 are one of alkali-free glass, alkaline glass, alumina glass, borosilicate glass or quartz glass.

[0103] In one embodiment, the coefficient of thermal expansion of the first glass core plate 11 and / or the second glass core plate 21 is 1ppm / ℃-10ppm / ℃, and the thermal conductivity of the first glass core plate 11 and / or the second glass core plate 21 is 1W / m·K-5W / m·K.

[0104] This invention further effectively controls the warpage of the glass substrate and the adapter plate within the allowable range of yield by setting the coefficient of thermal expansion and the thermal conductivity of the glass core plate, so as to ensure that the product yield requirements are met.

[0105] In one embodiment, the thickness of the first glass core plate 11 is 0.4 mm to 0.8 mm, and the thickness of the second glass core plate 21 is 0.1 mm to 0.2 mm.

[0106] By adjusting the thickness of the glass core board and matching it with the material of the glass core board, this invention can improve space utilization while minimizing the impact of warping on circuit contact.

[0107] In one embodiment, a first groove 111 is provided on the second surface of the first glass core plate 11, and a passive device 13 is provided in the first groove 111. The passive device 13 forms an effective electrical connection with the substrate interconnect layer 12.

[0108] The present invention provides a passive device 13 by placing the passive device 13 in the first groove 111 of the first glass core plate 11 and embedding the passive device 13 into the substrate, thereby freeing up the space on the outer surface of the substrate originally used for mounting the passive device 13, thereby improving the space utilization of the substrate, increasing the mounting density of the integrated chip 30, and further improving the interconnection performance of the packaging substrate.

[0109] Specifically, the first, second, third, and fourth surfaces in this invention are all surfaces that distinguish and connect different structures, and their surfaces have no other differences.

[0110] In one embodiment, the substrate interconnect layer 12 includes multiple patterned substrate circuit layers 121 and multiple substrate dielectric layers 122, the gaps between each patterned substrate circuit layer 121 are filled by the substrate dielectric layer 122, and adjacent substrate circuit layers 121 are electrically connected through the substrate dielectric layer 122; and / or the adapter board interconnect layer 22 includes multiple patterned adapter board circuit layers 221 and multiple adapter board dielectric layers 222, the gaps between each patterned adapter board circuit layer 221 are filled by the adapter board dielectric layer 222, and adjacent adapter board circuit layers 221 are electrically connected through the adapter board dielectric layer 222.

[0111] By setting up a multilayer substrate circuit layer 121 and an adapter board circuit layer 221, the present invention can further improve the mounting density of the integrated chip 30, while maximizing the more reliable electrical connection effect achieved by using a glass core board and increasing the density of interconnect lines.

[0112] In one embodiment, each substrate circuit layer 121 includes a substrate seed layer and a substrate conductive layer, and each adapter board circuit layer 221 includes an adapter board seed layer and an adapter board conductive layer.

[0113] This invention first sets a seed layer in the circuit layer, so that the conductive layer can fit more closely with the underlying structural layer, thereby further improving the flatness of the substrate and the adapter board, and thus further ensuring the interconnection reliability of the substrate.

[0114] Example 2:

[0115] The present invention also provides a method for preparing a packaging structure, the method being used to prepare any one of the packaging structures described in Embodiment 1 above, the method comprising:

[0116] Step 1: Provide a glass substrate, the glass substrate including a first glass core plate 11;

[0117] Step 2: Provide a glass transition plate, the glass transition plate including a second glass core plate 21;

[0118] Step 3: Form an effective electrical connection between the glass substrate and one side of the glass adapter plate;

[0119] Step 4: Make an effective electrical connection between the other side of the glass adapter plate and the chip 30.

[0120] The preparation method of the packaging structure of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the above order does not strictly represent the order of the preparation method of the packaging structure protected by the present invention, and those skilled in the art can make changes according to the actual preparation steps.

[0121] First, step 1 is performed, providing a glass substrate, the glass substrate including a first glass core plate 11.

[0122] In one embodiment, the method for preparing the glass substrate is as follows:

[0123] like Figure 2 As shown, a first glass core plate 11 is provided, the first glass core plate 11 including a first surface and a second surface disposed opposite to each other;

[0124] like Figure 3 As shown, a first through hole 112 and a first groove 111 are provided on the second surface of the first glass core plate 11. The first through hole 112 penetrates the first glass core plate 11, while the first groove 111 does not penetrate the first glass core plate 11.

[0125] like Figure 4 As shown, a first substrate seed layer 1211 is wrapped around all exposed surfaces of the first glass core plate 11;

[0126] like Figure 5 As shown, a patterned first substrate photosensitive layer 1212 is provided on the first substrate seed layer 1211 on both the first and second surfaces of the first glass core plate 11.

[0127] like Figure 6 As shown, the gaps between the patterned first substrate photosensitive layers 1212 are filled with a first substrate conductive layer 1213, and the first substrate conductive layer 1213 also fills the first through-hole 112.

[0128] like Figure 7 As shown, by removing the first substrate photosensitive layer 1212 and the first substrate seed layer 1211 below the first substrate photosensitive layer 1212, the patterned first substrate conductive layer 1213 and the first substrate seed layer 1211 constitute the patterned first substrate circuit layer 121.

[0129] like Figure 8 As shown, a passive device 13 is disposed in the first groove 111;

[0130] like Figure 9 As shown, a patterned substrate dielectric layer 122 is provided on the first substrate circuit layer 121, and the gaps between the patterned substrate dielectric layers 122 expose part of the conductive connection points of the first substrate circuit layer 121 and the passive device 13.

[0131] like Figure 10 As shown, a second substrate seed layer 1214 is provided on the patterned substrate dielectric layer 122, and the second substrate seed layer 1214 covers the exposed substrate dielectric layer 122, the first substrate circuit layer 121 and the conductive connection points of the passive device 13.

[0132] like Figure 11 As shown, a patterned second substrate photosensitive layer 1215 is provided on the first substrate seed layer 1211;

[0133] like Figure 12 As shown, the gaps between the patterned second substrate photosensitive layers 1215 are filled with a second substrate conductive layer 1216, and the second substrate conductive layer 1216 forms an effective electrical connection with the first substrate circuit layer 121 exposed by the patterned substrate dielectric layer 122 through the second substrate seed layer 1214.

[0134] like Figure 13 As shown, after removing the second substrate photosensitive layer 1215 and the second substrate seed layer 1214 below the second substrate photosensitive layer 1215, the patterned second substrate conductive layer 1216 and the second substrate seed layer 1214 constitute the second substrate circuit layer 121.

[0135] The present invention provides a passive device 13 by placing a passive device 13 in the first groove 111 of the glass substrate, thereby embedding the passive device 13 into the glass substrate, freeing up the space on the outer surface of the glass substrate that needs to be mounted on the passive device 13, improving the space utilization of the passive device 13, and thus improving the integration density of the integrated chip 30.

[0136] In one embodiment, the first groove 111 and the first through hole 112 on the first glass core plate 11 are obtained by laser-induced etching.

[0137] In one embodiment, the diameter of the first through hole 112 is 0.05 mm to 0.15 mm.

[0138] In one embodiment, the first substrate seed layer 1211 and / or the second substrate seed layer 1214 are obtained by chemical copper plating.

[0139] In one embodiment, the first substrate conductive layer 1213 and the second substrate conductive layer 1216 are formed by electroplating.

[0140] In one embodiment, the first substrate seed layer 1211 below the first substrate photosensitive layer 1212 and the second substrate seed layer 1214 below the second substrate photosensitive layer 1215 are removed by flash etching.

[0141] In one embodiment, such as Figure 8 As shown, after the adhesive material layer 14 is provided in the first groove 111, the passive device 13 is placed in the first groove 111.

[0142] In one embodiment, after applying DAF (Die Attach Film) material to the side of the passive device 13 that is in contact with the first groove 111, the passive device 13 is placed in the first groove 111.

[0143] In one embodiment, the thickness of the DAF material is 5 micrometers to 20 micrometers.

[0144] In one embodiment, the passive device 13 is one or more of capacitors, inductors, and resistors, or any combination thereof.

[0145] In one embodiment, the substrate dielectric layer 122 includes ABF (Ajinomoto deposited film) or PID (photosensitive insulating dielectric layer).

[0146] Specifically, PID includes one of PS (polystyrene), PI (polyimide), PBO (poly(p-phenylenebenzodioxazole) fiber), or EPOXY (epoxy resin).

[0147] Specifically, when the substrate dielectric layer 122 is a dry film, it is set by vacuum lamination, exposure, development, and post-curing; when the substrate dielectric layer 122 is a wet film, it is set by coating, pre-baking, exposure, development, and post-curing.

[0148] In one embodiment, when forming the patterned second substrate circuit layer 121, such as Figure 9As shown, by providing a substrate blind via 123 that penetrates the substrate dielectric layer 122, the first substrate circuit layer 121 can form an effective electrical connection with the second substrate circuit layer 121.

[0149] In one embodiment, laser drilling using carbon dioxide or ultraviolet light is used to obtain substrate blind holes 123 on the substrate dielectric layer 122.

[0150] In one embodiment, the diameter of the substrate blind via 123 on the substrate dielectric layer 122 is less than or equal to 60 micrometers.

[0151] In one embodiment, desmearing is performed after the substrate blind vias 123 of the substrate dielectric layer 122 are formed.

[0152] In one embodiment, such as Figure 14 As shown, after the second substrate circuit layer 121 is formed, the multilayer substrate dielectric layer 122 and the multilayer substrate circuit layer 121 are repeatedly formed to form the substrate interconnect layer 12.

[0153] In one embodiment, such as Figure 15 As shown, the gaps between the patterned substrate conductive layers on the surface of the substrate interconnect layer 12 are filled with the substrate solder resist layer 151, exposing only the surface of the substrate interconnect layer 12 that needs to form an effective electrical connection with the outside.

[0154] In one embodiment, the substrate solder resist layer 151 is solder resist ink.

[0155] In one embodiment, such as Figure 15 As shown, a substrate surface treatment layer 152 is provided on the portion of the substrate conductive layer on the surface of the substrate interconnect layer 12 that needs to be electrically connected, so as to protect the portion that needs to be electrically connected from oxidation.

[0156] Then, in step 2, a glass adapter plate is provided, the glass adapter plate including a second glass core plate 21.

[0157] In one embodiment, the method for preparing the glass transition plate is as follows:

[0158] like Figure 16 As shown, a second glass core plate 21 is provided, the second glass core plate 21 including a third surface and a fourth surface disposed opposite to each other;

[0159] like Figure 17 As shown, a second through hole 211 is provided in the second glass core plate 21, and the second through hole 211 penetrates the second glass core plate 21.

[0160] like Figure 18As shown, a first adapter plate seed layer 2211 is covered on the surface of the second glass core plate 21, and the first adapter plate seed layer 2211 covers the surface of the second through hole 211.

[0161] like Figure 19 As shown, a patterned first adapter plate photosensitive layer 2212 is provided on the first adapter plate seed layer 2211;

[0162] like Figure 20 As shown, the gaps between the patterned first adapter plate photosensitive layers 2212 are filled with the first adapter plate conductive layer 2213, and the first adapter plate conductive layer 2213 is also filled with the second through hole 211.

[0163] like Figure 21 As shown, by removing the first adapter plate photosensitive layer 2212 and the first adapter plate seed layer 2211 below the first adapter plate photosensitive layer 2212, the patterned first adapter plate conductive layer 2213 and the first adapter plate seed layer 2211 constitute the patterned first adapter plate circuit layer 221.

[0164] like Figure 22 As shown, a graphical adapter board dielectric layer 222 is provided on the first adapter board circuit layer 221, and the gaps between the graphical adapter board dielectric layers 222 expose a portion of the first adapter board circuit layer 221.

[0165] like Figure 23 As shown, a second adapter seed layer 2214 is provided on the graphical adapter medium layer 222, and the second adapter seed layer 2214 covers the exposed adapter medium layer 222 and the first adapter circuit layer 221.

[0166] like Figure 24 As shown, a patterned second adapter photosensitive layer 2215 is provided on the first adapter seed layer 2211;

[0167] like Figure 25 As shown, the gaps between the patterned second adapter plate photosensitive layers 2215 are filled with the second adapter plate conductive layer 2216, and the second adapter plate conductive layer 2216 forms an effective electrical connection with the first adapter plate circuit layer 221 exposed by the patterned adapter plate dielectric layer 222 through the second adapter plate seed layer 2214.

[0168] like Figure 26 As shown, after removing the second adapter plate photosensitive layer 2215 and the second adapter plate seed layer 2214 below the second adapter plate photosensitive layer 2215, the graphical second adapter plate conductive layer 2216 and the second adapter plate seed layer 2214 constitute the second adapter plate circuit layer 221.

[0169] In one embodiment, the second through hole 211 on the second glass core plate 21 is obtained by laser-induced etching.

[0170] In one embodiment, the diameter of the second through hole 211 is 0.025 mm to 0.075 mm.

[0171] In one embodiment, the first adapter plate seed layer 2211 is obtained by physical vapor deposition (PVD) or wet chemical metallization (PTH).

[0172] In one embodiment, the first adapter plate seed layer 2211 includes a titanium layer and a copper layer.

[0173] In one embodiment, the first adapter plate conductive layer 2213 and the second adapter plate conductive layer 2216 are formed by electroplating.

[0174] In one embodiment, the first adapter seed layer 2211 below the first adapter photosensitive layer 2212 and the second adapter seed layer 2214 below the second adapter photosensitive layer 2215 are removed by flash etching.

[0175] In one embodiment, by coating a photosensitive insulating material, photolithography, and development, a blind via 223 is formed on the adapter plate dielectric layer 222 to obtain a patterned adapter plate dielectric layer 222, so that the first adapter plate circuit layer 221 can form an effective electrical connection with the second adapter plate circuit layer 221.

[0176] Specifically, the photosensitive insulating material is PS (polystyrene) or PI (polyimide).

[0177] In one embodiment, the conductive layer 2216 of the second adapter plate is formed by physical vapor deposition (PVD).

[0178] In one embodiment, such as Figure 27 As shown, after the second adapter board circuit layer 221 is formed, the multi-layer adapter board dielectric layer 222 and the multi-layer adapter board circuit layer 221 are repeatedly set to form the adapter board interconnection layer 22.

[0179] In one embodiment, such as Figure 28 As shown, the gaps between the patterned conductive layers of the adapter board on the surface of the adapter board interconnect layer 22 are filled with the adapter board solder mask layer 231, exposing only the surface of the adapter board interconnect layer 22 that needs to form an effective electrical connection with the outside.

[0180] In one embodiment, the solder resist layer 231 of the adapter board is solder resist ink.

[0181] In one embodiment, such as Figure 29 As shown, a surface treatment layer 232 is provided on the conductive layer of the adapter plate on the fourth surface of the second glass core plate 21, on the portion where electrical connection is required, to protect the portion where electrical connection is required from oxidation.

[0182] In one embodiment, such as Figure 30 As shown, a temporary protective film 233 is provided on the surface of the interconnecting layer 22 of the adapter plate on the fourth surface of the second glass core plate 21; as Figure 31 As shown, a copper pillar seed layer 234 is covered on the surface of the interconnect layer 22 of the adapter plate on the third surface of the second glass core plate 21; as Figure 32 As shown, a patterned third adapter plate photosensitive layer 235 is provided on the copper pillar seed layer 234; as Figure 33 As shown, the gaps between the patterned third adapter board photosensitive layers 235 are filled with copper pillar interconnect layers 236, which are used to form an effective electrical connection with the chip 30; as Figure 34 As shown, the photosensitive layer 235 of the third adapter plate and the copper pillar seed layer 234 under the photosensitive layer 235 of the third adapter plate are removed, and the temporary protective film 233 is removed.

[0183] In one embodiment, the copper pillar seed layer 234 is removed by flash etching.

[0184] In one embodiment, such as Figure 35 As shown, a first solder ball layer 153 is provided on the surface of the substrate interconnect layer 12 on the first surface of the first glass core plate 11, and a second solder ball layer 154 is provided on the surface of the substrate interconnect layer 12 on the second surface of the first glass core plate 11. The second solder ball layer 154 is used to form an effective electrical connection with the glass transition plate; or the second solder ball layer 154 is provided on the surface of the transition plate interconnect layer 22 on the third surface of the second glass core plate 21, and no solder ball layer is provided on the surface of the substrate interconnect layer 12 on the first glass core plate 11.

[0185] In one embodiment, a first filler layer 155 is used to fill the gaps between the second solder ball layers 154 to prevent unwanted electrical connections between the solder balls.

[0186] In one embodiment, such as Figure 35 As shown, a third solder ball layer 237 is provided on the copper pillar interconnect layer 236, and the third solder ball layer 237 is used to form an effective electrical connection with the chip 30.

[0187] In one embodiment, a second filler layer 238 is filled into the gaps between the third solder ball layers 237 to prevent unwanted electrical connections between the solder balls.

[0188] Next, proceed to step 3, as follows: Figure 35 As shown, an effective electrical connection is formed between the glass substrate and one side of the glass adapter plate.

[0189] Finally, proceed to step 4, as follows: Figure 35 As shown, the other side of the glass adapter plate is effectively electrically connected to the chip 30.

[0190] This invention improves the reliability of substrate interconnection by forming an effective electrical connection between a glass substrate using a glass core plate and a glass adapter plate. During the manufacturing process, the electrical connection points on the glass substrate and the glass adapter plate will not experience excessive warping due to temperature changes, thereby preventing such warping.

[0191] In summary, the packaging structure and its fabrication method of the present invention can reduce material costs and effectively reduce warping problems by setting both the core board of the glass substrate and the glass adapter board to be glass, making the board surfaces of the substrate and the adapter board flat and consistent, and improving the electrical connection reliability between the substrate and the adapter board; at the same time, by embedding passive devices in the glass substrate, the surface space of the substrate is freed up, improving the space utilization of the packaging structure and increasing the mounting density of integrated chips.

[0192] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0193] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A packaging structure, characterized in that, The packaging structure includes: a glass substrate, a glass adapter plate, and a chip; The glass substrate includes a first glass core plate, a substrate interconnect layer, and a substrate connection layer; The glass transition plate includes a second glass core plate, an interconnecting layer of the transition plate, and a connecting layer of the transition plate; The first glass core plate includes a first surface and a second surface disposed opposite to each other. A substrate interconnect layer is disposed on both the first surface and the second surface of the first glass core plate. A substrate connection layer is disposed on each substrate interconnect layer. The substrate connection layer near the second surface forms an effective electrical connection with the glass transition plate. A first groove is disposed on the second surface of the first glass core plate. A passive device is disposed in the first groove. The passive device forms an effective electrical connection with the substrate interconnect layer. The second glass core board includes a third side and a fourth side disposed opposite to each other. A transition board interconnection layer is disposed on both the third side and the fourth side of the second glass core board. A transition board connection layer is disposed on each of the transition board interconnection layers. The transition board connection layer near the third side forms an effective electrical connection with the glass substrate, and the transition board connection layer near the fourth side forms an effective electrical connection with the chip. The thickness of the first glass core plate is 0.4 mm to 0.8 mm, and the thickness of the second glass core plate is 0.1 mm to 0.2 mm.

2. The packaging structure according to claim 1, characterized in that, The first glass core board and / or the second glass core board are one of alkali-free glass, alkaline glass, alumina glass, borosilicate glass or quartz glass.

3. The packaging structure according to claim 1, characterized in that, The coefficient of thermal expansion of the first glass core plate and / or the second glass core plate is 1ppm / ℃-10ppm / ℃, and the thermal conductivity of the first glass core plate and / or the second glass core plate is 1W / m•K-5W / m•K.

4. The packaging structure according to claim 1, characterized in that, The substrate interconnect layer includes multiple patterned substrate circuit layers and multiple substrate dielectric layers. The gaps between each patterned substrate circuit layer are filled by the substrate dielectric layer, and adjacent substrate circuit layers are electrically connected through the substrate dielectric layer; and / or the adapter board interconnect layer includes multiple patterned adapter board circuit layers and multiple adapter board dielectric layers. The gaps between each patterned adapter board circuit layer are filled by the adapter board dielectric layer, and adjacent adapter board circuit layers are electrically connected through the adapter board dielectric layer.

5. The packaging structure according to claim 4, characterized in that, Each substrate circuit layer includes a substrate seed layer and a substrate conductive layer, and each adapter board circuit layer includes an adapter board seed layer and an adapter board conductive layer.

6. A method for preparing a packaging structure, characterized in that, The preparation method is used to prepare the encapsulation structure according to any one of claims 1-5, and the preparation method includes: A glass substrate is provided, the glass substrate comprising a first glass core plate; A glass adapter plate is provided, the glass adapter plate including a second glass core plate; An effective electrical connection is formed between the glass substrate and one side of the glass adapter plate; The other side of the glass adapter plate is effectively electrically connected to the chip.

7. The method for preparing the packaging structure according to claim 6, characterized in that, The method for preparing the glass substrate is as follows: A first glass core panel is provided, the first glass core panel including a first surface and a second surface disposed opposite to each other; A first through hole and a first groove are provided on the second side of the first glass core plate. The first through hole penetrates the first glass core plate, and the first groove does not penetrate the first glass core plate. The first substrate seed layer is wrapped around all exposed surfaces of the first glass core plate; A patterned first substrate photosensitive layer is provided on the first substrate seed layer on both the first and second sides of the first glass core plate. The gaps between the patterned first substrate photosensitive layers are filled with a first substrate conductive layer, and the first substrate conductive layer also fills the first via. Remove the first substrate photosensitive layer and the first substrate seed layer below the first substrate photosensitive layer, and the patterned first substrate conductive layer and the first substrate seed layer constitute a patterned first substrate circuit layer. A passive device is disposed within the first groove; A patterned substrate dielectric layer is provided on the first substrate circuit layer, and the gaps between the patterned substrate dielectric layers expose part of the conductive connection points between the first substrate circuit layer and the passive device. A second substrate seed layer is disposed on the patterned substrate dielectric layer, the second substrate seed layer covering the exposed substrate dielectric layer, the first substrate circuit layer and the conductive connection points of the passive device. A patterned second substrate photosensitive layer is disposed on the seed layer of the first substrate; The gaps between the patterned second substrate photosensitive layers are filled with a second substrate conductive layer, and the second substrate conductive layer forms an effective electrical connection with the first substrate circuit layer exposed by the patterned substrate dielectric layer through the second substrate seed layer. The second substrate photosensitive layer and the second substrate seed layer below the second substrate photosensitive layer are removed, and the patterned second substrate conductive layer and the second substrate seed layer constitute the second substrate circuit layer.

8. The method for preparing the packaging structure according to claim 6, characterized in that, The method for preparing the glass adapter plate is as follows: A second glass core panel is provided, the second glass core panel including a third side and a fourth side disposed opposite to each other; A second through hole is provided in the second glass core plate, and the second through hole penetrates the second glass core plate; A first adapter plate seed layer is covered on the surface of the second glass core plate, and the first adapter plate seed layer covers the surface of the second through hole; A patterned first adapter plate photosensitive layer is provided on the first adapter plate seed layer; The gaps between the patterned first adapter plate photosensitive layers are filled with the first adapter plate conductive layer, and the first adapter plate conductive layer is also filled with the second through hole. Remove the photosensitive layer of the first adapter board and the seed layer of the first adapter board below the photosensitive layer of the first adapter board. The patterned conductive layer of the first adapter board and the seed layer of the first adapter board constitute a patterned circuit layer of the first adapter board. A graphical adapter board dielectric layer is provided on the first adapter board circuit layer, and the gaps between the graphical adapter board dielectric layers expose part of the first adapter board circuit layer. A second adapter seed layer is provided on the graphical adapter medium layer, the second adapter seed layer covering the exposed adapter medium layer and the first adapter circuit layer; A patterned second adapter photosensitive layer is provided on the seed layer of the first adapter plate; The gaps between the patterned second adapter plate photosensitive layers are filled with the second adapter plate conductive layer, and the second adapter plate conductive layer forms an effective electrical connection with the first adapter plate circuit layer exposed by the patterned adapter plate dielectric layer through the second adapter plate seed layer. Remove the photosensitive layer of the second adapter board and the seed layer of the second adapter board below the photosensitive layer of the second adapter board. The patterned conductive layer of the second adapter board and the seed layer of the second adapter board constitute the circuit layer of the second adapter board.

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