Crystal bar manufacturing method, silicon wafer and solar cell
In the production process of single crystal silicon solar cells, the heating power and argon gas flow rate of the single crystal furnace and the process parameters are optimized, and the problems of minus number life, impurity content and crystal defects in the prior art are solved, and the effect of improving the efficiency of the solar cell is achieved.
Patent Information
- Application Number
- CN202510228248.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-27
- Publication Date
- 2025-05-23
AI Technical Summary
In the production process of monocrystalline silicon solar cells, it is difficult to effectively improve the lifespan of minuscule, reduce impurity content and improve crystal defects, resulting in low solar cell efficiency.
By adjusting the heating power and argon flow of the single crystal furnace, process optimization is carried out in the melting silicon, crystal extraction, shoulder releasing, shoulder rotation and isometric stages to form a stable isolation layer, and the seed crystal is prepared using the zone melting method, and the crystal pulling speed and the rotation speed are adjusted in the isometric stage to reduce the generation of crystal defects and impurities.
It improves the quality of silicon wafers, extends the life of minor sub-births, reduces impurity content and crystal defects, and thus improves the photoelectric conversion efficiency of solar cells.
Smart Images
Figure CN120026388A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of photovoltaic technology, and in particular to a method for manufacturing a crystal rod, a silicon wafer and a solar cell. Background Art
[0002] With the development of photovoltaic technology, the demand for solar cells is also growing rapidly. As an important substrate for solar cells, single crystal silicon is mostly produced in a single crystal furnace using the direct pulling method.
[0003] At present, minority carrier lifetime, impurity content, and crystal defects have a significant impact on the efficiency of solar cells, and there is currently no method to improve the efficiency of solar cells at the crystal pulling end. Summary of the invention
[0004] The embodiments of the present application provide a method for manufacturing a crystal rod, a silicon wafer and a solar cell, which aim to improve the quality of the silicon wafer by increasing the minority carrier lifetime, reducing the impurity content, improving crystal defects, etc., thereby improving the efficiency of the solar cell.
[0005] The embodiment of the present application provides a method for manufacturing a crystal rod, which is used for producing a single crystal silicon rod in a single crystal furnace, wherein the single crystal furnace comprises a crucible, wherein the crucible is filled with silicon material, a main heater is arranged on the side wall of the crucible, and a bottom heater is arranged on the bottom of the crucible; The manufacturing method comprises: melting silicon, seeding, shouldering, shoulder rotation, equalizing diameters and finishing; In the silicon melting stage, the main heating power of the main heater is 100kw-120kw, the bottom heating power of the bottom heater is 90kw-100kw, and the argon flow rate into the crucible is 140slpm-160slpm; In the seeding stage, the main heating power of the main heater is 65kw-70kw, the bottom heater is turned off, and the argon flow rate introduced into the crucible from the seeding stage is adjusted to 110 slpm-130 slpm; The main heating power in the shoulder release stage is reduced by 8kw-10kw compared to the main heating power in the seeding stage.
[0006] In a possible design, during the silicon melting stage, when the silicon material has not yet melted into a liquid state, an isolation layer is formed on the inner wall surface of the crucible.
[0007] In a possible design, the seed crystals in the seeding stage are prepared by a zone melting method.
[0008] In a possible design, in the equal diameter stage, the crystal pulling speed is reduced to 80 mm / h-90 mm / h.
[0009] In a possible design, during the shoulder turning stage, the crucible to heel ratio is 0.11-0.13; In the equal diameter stage, the crucible to heel ratio is 00.07-0.08.
[0010] In a possible design, during the equal diameter stage, the manufacturing method further includes: The rotation speed of the crucible is gradually adjusted from 3 rpm to 6 rpm, and the rotation speed of the crucible is adjusted before the crystal rod reaches a reserved length; The rotation speed of the seed crystal is gradually adjusted from 7 rpm to 6 rpm, and the rotation speed of the seed crystal is adjusted before the crystal rod reaches the reserved length.
[0011] In a possible design, during the process of making the crystal rod, the manufacturing method further includes: the furnace pressure of the crucible is 3 torr-5 torr.
[0012] A silicon wafer is also provided in an embodiment of the present application, which is prepared by slicing a crystal rod based on the above-mentioned manufacturing method, and the resistivity of the silicon wafer is 8Ω.cm-24Ω.cm.
[0013] In a possible design, the element doping concentration of the silicon wafer is n, 2.393×10 14 atom / cm 3 ≤n≤1.593×10 16 tom / cm 3 .
[0014] The embodiment of the present application further provides a solar cell, the solar cell comprising the silicon wafer described above; The doping element of the silicon wafer includes at least one of phosphorus and antimony; The back of the solar cell is provided with doping regions of different polarities. In the embodiment of the present application, by adjusting the process method for making the crystal rod, the minority carrier lifetime is increased, the impurity content is reduced, the crystal defects are improved, and the quality of the silicon wafer is improved, thereby improving the photoelectric conversion efficiency of the solar cell.
[0015] Specifically, in the silicon melting stage, the main heating power is set to 100kw-120kw, the bottom heating power is set to 90kw-100kw, the argon flow rate is 140slpm-160slpm, the crucible is pre-melted and heat treated, and the water and volatile impurities in the crucible are removed by high-temperature baking, and then the impurities are taken away by the large amount of argon gas. At the same time, a stable isolation layer is formed on the surface of the crucible to isolate the silicon liquid and reduce the absorption of impurities during the crystal pulling process.
[0016] The zone melting method is used to produce seed crystals for seeding. The zone melting single crystal itself has the advantages of fewer defects and impurities. Using it as the seed crystal for the direct pulling method can effectively reduce the situation in which defects and impurities in the crystal pulling process cause the electrical performance to deteriorate.
[0017] Reducing the shoulder cooling amount to 9kw makes the temperature of the equal-diameter head higher. The higher equal-diameter temperature can make the migration of silicon atoms at the growth interface more active, so that atoms have more opportunities to arrange in the correct lattice position, thereby reducing the generation of defects such as dislocations and twins. At the same time, the diffusion rate of impurity atoms at the solid-liquid interface is accelerated, which helps to better distribute impurities in the liquid phase and solid phase, avoid local aggregation of impurities, and improve crystal quality.
[0018] The constant diameter pulling speed is pressed to 80mm / h-90mm / h, so that the crystal growth interface remains relatively stable, and silicon atoms have enough time to arrange in the correct lattice position, reducing the generation of defects such as dislocations and twins. At the same time, the low pulling speed makes the impurities in the crystal more evenly distributed, reducing the composite centers formed by impurity aggregation, thereby increasing the minority carrier lifetime.
[0019] In the equal-diameter stage, the crystal is rotated from 7rpm to 6rpm, and the crucible is rotated from 3rpm to 6rpm (completed after equal-diameter growth control), which reduces the temperature fluctuation at the crystal growth interface and thermal stress, thereby reducing the probability of defects such as dislocations inside the crystal and improving the crystal quality.
[0020] At the same time, due to the serious radial attenuation of the resistance of the high-resistance silicon rod, a lower crystal crucible rotation is used, and the doping elements have more sufficient time to diffuse in the melt, making the doping elements more evenly distributed in the crystal, reducing the radial attenuation of the silicon rod resistance, and making the electrical performance more stable.
[0021] It should be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 A schematic diagram of a single crystal furnace provided in this application; Figure 2 This is a schematic diagram of the crucible provided in this application.
[0023] Reference numerals: 1- Single crystal furnace; 11- Crucible; 111- isolation layer; 12- Main heater; 13- bottom heater; 14-heat preservation tube; 141- upper insulation cylinder; 142-medium insulation cylinder; 143-lower insulation cylinder; 2-Silicon material.
[0024] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application. DETAILED DESCRIPTION
[0025] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.
[0026] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.
[0027] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.
[0028] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.
[0029] It should be noted that the directional words such as "upper", "lower", "left", and "right" described in the embodiments of the present application are described at the angles shown in the accompanying drawings and should not be understood as limiting the embodiments of the present application. In addition, in the context, it is also necessary to understand that when it is mentioned that an element is connected to another element "upper" or "lower", it can not only be directly connected to another element "upper" or "lower", but also indirectly connected to another element "upper" or "lower" through an intermediate element.
[0030] This embodiment provides a method for manufacturing a crystal rod, which is used in a single crystal furnace to produce a single crystal silicon rod. Figure 1The figure shows a schematic diagram of a single crystal furnace 1 with a crucible 11. The single crystal furnace 1 includes a crucible 11, a main heater 12, a bottom heater 13 and an insulation barrel 14. The crucible 11 contains silicon material 2, i.e., crystalline silicon raw material. The main heater 12 and the bottom heater 13 are both arranged in the single crystal furnace 1 to heat the crucible 11. The main heater 12 is arranged on the side wall of the crucible 11, and the bottom heater 13 is arranged at the bottom of the crucible 11. The insulation barrel 14 is arranged on the outer periphery of the main heater 12. The insulation barrel 14 includes an upper insulation barrel 141, a middle insulation barrel 142 and a lower insulation barrel 143. The upper insulation barrel 141, the middle insulation barrel 142 and the lower insulation barrel are arranged in sequence along the height direction of the single crystal furnace 1. The diameters of the middle insulation tube 142 and the lower insulation tube 143 are the same, and the middle insulation tube 142 can be directly connected to the lower insulation tube 143. The diameter of the upper insulation tube 141 is smaller than that of the middle insulation tube 142, and a support ring (not shown in the figure) is required to be arranged between the upper insulation tube 141 and the middle insulation tube 142 for transition support to achieve the connection between the upper insulation tube 141 and the middle insulation tube 142. The basic principle of crystal pulling is that the crystalline silicon raw material is placed in the crucible 11, and there is a rotatable and liftable rod above the crucible 11, and a seed crystal is fixed at the lower end of the rod. After the crystalline silicon raw material is melted by the heater, it is inserted into the melt through the seed crystal, and the appropriate temperature is controlled to reach the supersaturation temperature. The desired single crystal silicon rod can be obtained while rotating and pulling the crystal.
[0031] Among them, the production method of single crystal silicon rod includes: melting silicon, seeding, shoulder release, shoulder rotation, equal diameter and finishing.
[0032] To elaborate, in the silicon melting stage, after placing the crystalline silicon raw material in the crucible 11, the main heater 12 and the bottom heater 13 are turned on to melt the crystalline silicon raw material. In the seeding stage, the bottom heater 13 is turned off, and the seed crystal is placed in the crystalline silicon melt. By reducing the diameter of the seed crystal to a certain extent and generating a sufficient length, it is discharged to the surface by using the angle of dislocation growth. In the shoulder release stage, the crystal diameter gradually grows to the required diameter through the coordinated control of temperature and pulling speed. In the shoulder turning stage, by increasing the temperature and pulling speed, the crystal diameter no longer grows and begins to grow in equal diameter in length. In the equal diameter stage, the crystal maintains equal diameter growth by controlling the temperature and pulling speed. In the finishing stage, when the crystal grows to the required length of the product, the crystal diameter is rapidly reduced by increasing the temperature and pulling speed, and finally the tail is separated from the liquid surface. After stopping the furnace, the single crystal furnace 1 is disassembled for cleaning, and the furnace is closed after cleaning and drying for standby use.
[0033] Specifically, in the silicon melting stage, the main heating power of the main heater 12 can be set to 100kw-120kw. Exemplarily, the main heating power of the main heater 12 can be set to 100kw, 102kw, 104kw, 106kw, 108kw, 110kw, 112kw, 114kw, 116kw, 118kw, 120kw, etc.
[0034] Among them, the main heating power of the main heater 12 can be adjusted according to actual conditions, and can be further expanded or reduced. It can be specifically set according to actual conditions, and this embodiment does not limit it here.
[0035] In the silicon melting stage, the bottom heating power of the bottom heater 13 can be set to 90kw-100kw. For example, the bottom heating power of the bottom heater 13 can be set to 90kw, 91kw, 92kw, 93kw, 94kw, 95kw, 96kw, 97kw, 98kw, 99kw, 100kw, etc.
[0036] The bottom heating power of the bottom heater 13 can be adjusted according to actual conditions, and can be further enlarged or reduced. The specific setting can be based on actual conditions, and this embodiment does not limit this.
[0037] In this embodiment, in the silicon melting stage, the crystalline silicon raw material is placed in the crucible 11, the main heater 12 and the bottom heater 13 are turned on, the main heating power of the silicon melting stage is increased from the current 90kw-100kw to 100kw-120kw, and the bottom heating power of the silicon melting stage is increased from the current 80kw-90kw to 90kw-100kw, the temperature in the crucible 11 of the silicon melting stage is increased, the crucible 11 is pre-melted and heat treated, and the moisture and volatile impurities in the crucible 11 are removed by high-temperature baking.
[0038] In the silicon melting stage, the argon flow rate of the crucible 11 can be set to 140 slpm-160 slpm. For example, in the silicon melting stage, the argon flow rate of the crucible 11 can be 140 slpm, 145 slpm, 150 slpm, 155 slpm, 160 slpm, etc.
[0039] The flow rate of argon gas introduced into the crucible 11 can be adjusted according to actual conditions, and can be further increased or decreased. The specific flow rate can be set according to actual conditions, and this embodiment does not limit this.
[0040] In this embodiment, during the silicon melting stage, the flow rate of argon gas introduced into the crucible 11 is increased from the current 110 slpm-120 slpm to 140 slpm-160 slpm. While the crucible 11 is preheated at high temperature, a large amount of argon gas is introduced into the crucible 11 so that the argon gas can carry away the volatile impurities.
[0041] At the same time, when the crystalline silicon raw material is not melted to a liquid state, a stable isolation layer 111 is formed on the inner wall surface of the crucible 11. The isolation layer 111 isolates the crucible 11 and the crystalline silicon raw material to reduce the absorption of oxygen and impurities during the crystal pulling process. For details, please refer to Figure 2 .
[0042] The isolation layer 111 is formed by the reaction between the inner wall of the crucible 11 and water. For example, the inner wall of the crucible 11 may be barium oxide, and the isolation layer 111 may be barium hydroxide formed by the reaction between barium oxide and water. Barium hydroxide is an inorganic compound that reduces the absorption of impurities in the crystal rod and promotes the improvement of the production efficiency of the crystal rod.
[0043] Alternatively, in some embodiments, the material of the inner wall of the crucible 11 is different, and the isolation layer 111 can also be a coating of other materials, which is not limited in this embodiment.
[0044] In the silicon melting stage, the furnace pressure of the single crystal furnace 1 is set to 3 torr-5 torr. Exemplarily, in the silicon melting stage, the furnace pressure of the single crystal furnace 1 can be set to 3 torr, 4 torr, or 5 torr.
[0045] In this embodiment, the furnace pressure of the single crystal furnace 1 is adjusted from the current 8 torr to 3 torr-5 torr, which can reduce the thermal convection of the molten silicon, thereby making the growth interface more stable and reducing dislocations.
[0046] In the silicon melting stage, the rotation speed of the seed crystal can be set to 7 rpm, and the rotation speed of the crucible 11 can be set to 3 rpm.
[0047] In the seeding stage, the seed crystals in the seeding stage are prepared by the zone melting method, that is, the seed crystals produced by the zone melting method are used as the seed crystals for seeding when producing the crystal rods in this embodiment. The seed crystals produced by the zone melting method have the advantages of fewer defects and fewer impurities. The seed crystals produced by the zone melting method are used as the seed crystals for the Czochralski method for crystal pulling, which can effectively reduce the situation where the defects and impurities in the crystal pulling process cause the electrical properties to be reduced.
[0048] In the seeding stage, the main heating power of the main heater 12 can be set to 65kw-70kw, and the bottom heater 13 is turned off. The main heating power of the main heater 12 can be set to 65kw, 66kw, 67kw, 68kw, 69kw, 70kw, etc.
[0049] In the seeding stage, the flow rate of argon gas introduced into the crucible 11 can be set to 110 slpm-130 slpm. For example, the flow rate of argon gas introduced into the crucible 11 can be set to 110 slpm, 115 slpm, 120 slpm, 125 slpm, 130 slpm, etc.
[0050] In the seeding stage, the furnace pressure of the single crystal furnace 1 is set to 3 torr-5 torr. Exemplarily, in the seeding stage, the furnace pressure of the single crystal furnace 1 can be set to 3 torr, 4 torr, or 5 torr.
[0051] In this embodiment, the furnace pressure of the single crystal furnace 1 is adjusted from the current 8torr to 3torr-5torr, which can reduce the thermal convection of the molten silicon, thereby making the growth interface more stable and reducing dislocations. At the same time, the gas distribution on the crystal surface can be adjusted to reduce the risk of defects such as pores and oxidation on the crystal surface, thereby improving product quality.
[0052] In the seeding stage, the rotation speed of the seed crystal is 7 rpm, and the rotation speed of the crucible 11 is 3 rpm.
[0053] During the crystal seeding stage, the crystal pulling speed is 250mm / h-340mm / h.
[0054] In the shoulder release stage, the main heating power in the shoulder release stage is reduced by 8kw-10kw compared with the main heating power in the seeding stage. Exemplarily, the main heating power in the shoulder release stage is reduced by 8kw, 9kw, and 10kw compared with the main heating power in the seeding stage. That is, the main heating power in the shoulder release stage can be set to 55kw-62kw.
[0055] In this embodiment, the temperature reduction amount of 10kw-11kw is adjusted to 8kw-10kw, and the temperature reduction amount in the shoulder release stage is reduced, so that the temperature of the equal-diameter head is relatively high. The higher equal-diameter temperature can make the migration of silicon atoms at the growth interface more active, so that atoms have more opportunities to arrange in the correct lattice position, thereby reducing the generation of defects such as dislocations and twins. At the same time, the diffusion rate of impurity atoms at the solid-liquid interface is accelerated, which helps the impurities to be better distributed in the liquid phase and the solid phase, avoids the local aggregation of impurities, and improves the quality of the crystal.
[0056] In the shoulder release stage, the flow rate of argon gas introduced into the crucible 11 can be set to 110 slpm-130 slpm. Exemplarily, the flow rate of argon gas introduced into the crucible 11 can be set to 110 slpm, 115 slpm, 120 slpm, 125 slpm, 130 slpm.
[0057] In the shoulder release stage, the furnace pressure of the single crystal furnace 1 is set to 3 torr-5 torr. Exemplarily, in the shoulder release stage, the furnace pressure of the single crystal furnace 1 can be set to 3 torr, 4 torr, or 5 torr.
[0058] In this embodiment, the furnace pressure of the single crystal furnace 1 is adjusted from the current 8torr to 3torr-5torr, which can reduce the thermal convection of the molten silicon, thereby making the growth interface more stable and reducing dislocations. At the same time, the gas distribution on the crystal surface can be adjusted to reduce the risk of defects such as pores and oxidation on the crystal surface, thereby improving product quality.
[0059] During the shoulder release stage, the rotation speed of the seed crystal is 7 rpm, and the rotation speed of the crucible 11 is 3 rpm.
[0060] In the shoulder release stage, the crystal pulling speed is 45 mm / h-85 mm / h. Exemplarily, the crystal pulling speed can be set to 45 mm / h, 50 mm / h, 55 mm / h, 60 mm / h, 65 mm / h, 70 mm / h, 75 mm / h, 80 mm / h, 85 mm / h, etc.
[0061] In the shoulder stage, the main heating power of the main heater 12 can be set to 56kw-61kw. Exemplarily, the main heating power of the main heater 12 can be set to 56kw, 57kw, 58kw, 59kw, 60kw, 61kw, etc.
[0062] In the shoulder rotation stage, the flow rate of argon gas introduced into the crucible 11 can be set to 110 slpm-130 slpm. For example, the flow rate of argon gas introduced into the crucible 11 can be set to 110 slpm, 115 slpm, 120 slpm, 125 slpm, 130 slpm, etc.
[0063] During the shoulder rotation stage, the rotation speed of the seed crystal is 7 rpm, and the rotation speed of the crucible 11 is 3 rpm.
[0064] During the shoulder rotation stage, the crystal pulling speed is controlled by the crucible-to-heel ratio.
[0065] In the shoulder turning stage, the crucible to heel ratio can be set to 0.11-0.13. Exemplarily, the crucible to heel ratio can be set to 0.115, 0.12, 0.125, 0.13, etc.
[0066] Among them, the crucible to heel ratio in the shoulder turning stage can be adjusted according to the design situation, and can be further enlarged or reduced. It can be specifically set according to the actual situation, and this embodiment does not limit it here.
[0067] In the equal diameter stage, the main heating power of the main heater 12 can be set to 56kw-61kw. For example, the main heating power of the main heater 12 can be set to 56kw, 57kw, 58kw, 59kw, 60kw, 61kw, etc.
[0068] In the equal diameter stage, the argon flow rate through the crucible 11 can be set to 110 slpm-130 slpm. For example, the argon flow rate into the crucible 11 can be set to 110 slpm, 115 slpm, 120 slpm, 125 slpm, 130 slpm, etc.
[0069] In the equal diameter stage, the furnace pressure of the single crystal furnace 1 is set to 3 torr-5 torr. Exemplarily, in the equal diameter stage, the furnace pressure of the single crystal furnace 1 can be set to 3 torr, 4 torr, or 5 torr.
[0070] In this embodiment, the furnace pressure of the single crystal furnace 1 is adjusted from the current 8 torr to 3 torr - 5 torr, which can reduce the thermal convection of the molten silicon, thereby making the growth interface more stable and reducing dislocations. At the same time, the gas distribution on the crystal surface can be adjusted, reducing the risk of defects such as pores and oxidation on the crystal surface and improving the product quality.
[0071] In the equal diameter stage, the rotation speed of the crucible 11 is gradually adjusted from 3 rpm to 6 rpm, and the rotation speed of the crucible 11 is adjusted before the crystal bar reaches the reserved length. The rotation speed of the seed crystal is gradually adjusted from 7 rpm to 6 rpm, and the rotation speed of the seed crystal is adjusted before the crystal bar reaches the reserved length.
[0072] Specifically, if the length after the crystal bar grows 600 mm in the equal diameter stage is the reserved length of the crystal bar, then during the process of the crystal bar growing from 0 to 600 mm in the equal diameter stage, the rotation speed of the crucible is gradually adjusted from 3 rpm to 6 rpm, so that the rotation speed of the crucible is adjusted before the crystal bar reaches 600 mm.
[0073] And, if the length after the crystal bar grows 600 mm in the equal diameter stage is the reserved length of the crystal bar, then during the process of the crystal bar growing from 0 to 600 mm in the equal diameter stage, the rotation speed of the seed crystal is gradually adjusted from 7 rpm to 6 rpm, so that the rotation speed of the seed crystal is adjusted before the crystal bar reaches 600 mm.
[0074] In this embodiment, by adjusting the rotation speed of the crucible 11 in the equal diameter stage from the current 8 rpm to 6 rpm to 7 rpm to 6 rpm, and adjusting the rotation speed of the seed crystal in the equal diameter stage from the current 4 rpm to 7 rpm to 3 rpm to 6 rpm, the temperature condition generated inside the melt is effectively improved, the temperature fluctuation at the crystal growth interface is reduced, and the thermal stress is reduced, thereby reducing the generation probability of defects such as dislocations inside the crystal and improving the crystal quality.
[0075] At the same time, due to the serious radial attenuation of the resistance of the high-resistance silicon rod, with a lower rotation speed of the crucible, the doping elements have more sufficient time to diffuse in the melt, making the distribution of the doping elements in the crystal more uniform, reducing the radial attenuation of the silicon rod resistance, and making the electrical performance more stable.
[0076] In addition, using a lower rotation speed of the crucible can reduce the movement generated by the melt itself, avoid further decomposition of the inner wall of the crucible, and reduce the impurity content of the crystal bar.
[0077] In the equal diameter stage, the crystal pulling speed is reduced to 80 mm / h - 90 mm / h. Exemplarily, the crystal pulling speed can be set to 80 mm / h, 81 mm / h, 82 mm / h, 83 mm / h, 84 mm / h, 85 mm / h, 86 mm / h, 87 mm / h, 88 mm / h, 89 mm / h, 90 mm / h, etc.
[0078] Among them, the crystal pulling speed in the equal diameter stage can be adjusted according to the setting conditions, and can be further expanded or reduced. It can be set specifically according to the actual situation, and this embodiment does not limit it here.
[0079] In this embodiment, the crystal pulling speed is adjusted from the current 100mm / h-110mm / h to 80mm / h-90mm / h, so that the crystal growth interface remains relatively stable, and silicon atoms have enough time to arrange in the correct lattice position, reducing the generation of defects such as dislocations and twins. At the same time, the low pulling speed makes the impurities in the crystal more evenly distributed, reduces the recombination centers formed by impurities, and thus improves the minority carrier lifetime.
[0080] In the equal diameter stage, the crucible to heel ratio is 0.07-0.08. Exemplarily, the crucible to heel ratio can be set to 0.075, 0.076, 0.077, 0.078, 0.079, 0.080, etc.
[0081] The crucible to heel ratio in the equal diameter stage can be adjusted according to the design situation, further enlarged or reduced, and can be specifically set according to the actual situation, which is not limited in this embodiment.
[0082] The specific parameters of each stage of the crystal pulling process in the above content can be referred to in Table 1 below: Table 1
[0083] This embodiment also provides a silicon wafer, which is prepared by slicing a crystal rod after being made according to the above-mentioned manufacturing method. The element doping concentration of the prepared silicon wafer is n, 2.393×10 14 atom / cm 3 ≤n≤1.593×10 16 tom / cm 3 The minority carrier lifetime of the prepared silicon wafer is 7100us-7600us. The silicon wafer formed by the above manufacturing process can increase the minority carrier lifetime of the silicon wafer, thereby improving the efficiency of the silicon wafer.
[0084] This embodiment also provides a solar cell, the solar cell includes the above-mentioned silicon wafer, and the doping element of the silicon wafer includes at least one of phosphorus and antimony. The back of the solar cell is provided with doping regions of different polarities. For example, the solar cell can be a BC (Back Contact) cell.
[0085] Specifically, the N-type silicon substrate is doped to form alternating n+ doped areas and p+ doped areas on the back surface, so that the back of the solar cell has both positive and negative electrodes, so that all grid lines can be completely set on the back of the solar cell.
[0086] Table 2 below shows the performance values of silicon wafers prepared with different resistivities under the same doping element (phosphorus) when the crystal rod is made using the above method: Table 2
[0087] From Table 2 above, we can see that when the resistivity of the silicon wafer is 1.5Ω.cm-2.5Ω.cm, the power generation efficiency is 26.73%, the minority carrier lifetime is 6200us, the oxygen content is 10.5ppma, and the element doping concentration is 1.852×10 15 ~3.161×10 15 .
[0088] When the resistivity of the silicon wafer is 8Ω.cm-24Ω.cm, the power generation efficiency is 26.89%, the minority carrier lifetime is 7500us, the oxygen content is 10.5ppma, and the element doping concentration is 2.440×10 14 tom / cm 3 ~5.585×10 14 tom / cm 3 .
[0089] Table 3 below shows the performance values of silicon wafers prepared with different resistivities under the same doping element (phosphorus antimony doping) when the above method is used to make the crystal rod: Table 3
[0090] From Table 3 above, we can see that when the resistivity of the silicon wafer is 1.5Ω.cm-2.5Ω.cm, the power generation efficiency is 26.69%, the minority carrier lifetime is 6300us, the oxygen content is 10.5ppma, and the phosphorus doping concentration is 1.872×10 15 ~3.137×10 15 , the antimony doping concentration is 5.320×10 16 tom / cm 3 ~9.135×10 16 tom / cm 3 .
[0091] When the resistivity of the silicon wafer is 8Ω.cm-24Ω.cm, the power generation efficiency is 26.83%, the minority carrier lifetime is 7400us, the oxygen content is 10.5ppma, and the phosphorus doping concentration is 2.393×10 14 ~5.472×10 14 , the antimony doping concentration is 66.967×10 14 tom / cm 3 ~1.593×10 16 tom / cm 3 .
[0092] Please refer to the data on efficiency, minority carrier lifetime, and oxygen content corresponding to each resistor of the silicon wafer in the embodiment of the present application in Table 2 and Table 3 above, which show that under the same process conditions, the electrical performance of the silicon wafer is better when the resistivity range is in the range of 8Ω.cm-24Ω.cm.
[0093] Table 4 below is a comparison table of some parameters of the silicon wafer prepared in the embodiment of the present application and the existing silicon wafer. Among them, the doping element in the existing silicon wafer and the silicon wafer prepared in the embodiment of the present application is phosphorus.
[0094] Table 4
[0095] As can be seen from Table 4 above, in the silicon wafers prepared by the existing method, the resistivity in the existing scheme 1 is 1.5-2.5Ω.cm, the power generation efficiency is 26.52%, the minority carrier lifetime is 5235.72us, the oxygen content is 8.86ppma, the resistivity of the recycled material is 2, and the doping amount of phosphorus element is 227.35g.
[0096] In the existing scheme 2, the resistivity is 1.5-2.5Ω.cm, the power generation efficiency is 26.49%, the minority carrier lifetime is 5084.85us, the oxygen content is 9.25ppma, the resistivity of the recycled material is 2, and the doping amount of phosphorus element is 227.35g.
[0097] In the existing scheme 3, the resistivity is 1.5-2.5Ω.cm, the power generation efficiency is 26.48%, the minority carrier lifetime is 4644.06us, the oxygen content is 9.04ppma, the resistivity of the recycled material is 2, and the doping amount of phosphorus element is 227.35g.
[0098] In the silicon wafer prepared by the preparation method of the embodiment of the present application, the resistivity in Scheme 1 is 1.5-2.5Ω.cm, the power generation efficiency is 26.64%, the minority carrier lifetime is 6212.09us, the oxygen content is 9.04ppma, the resistivity of the recycled material is 2, and the doping amount of phosphorus element is 227.35g.
[0099] In this scheme 2, the resistivity is 1.5-2.5Ω.cm, the power generation efficiency is 26.55%, the minority carrier lifetime is 6002.44 us, the oxygen content is 9.08ppma, the resistivity of the recycled material is 2, and the doping amount of phosphorus element is 227.35g.
[0100] In this scheme 3, the resistivity is 14Ω.cm, the power generation efficiency is 26.76%, the minority carrier lifetime is 7134us, the oxygen content is 8.89ppma, the resistivity of the recycled material is 10, and the doping amount of phosphorus element is 21.2g.
[0101] In this scheme 4, the resistivity is 14Ω.cm, the power generation efficiency is 26.84%, the minority carrier lifetime is 7585 us, the oxygen content is 9.06 ppma, the resistivity of the recycled material is 10, and the doping amount of phosphorus is 21.2g.
[0102] In summary, according to the comparison results in Table 4 above, under the condition of the same resistance yield (1.5-2.5), the resistivity, power generation efficiency, minority carrier lifetime, process oxygen content, and element content of the silicon wafers produced by the embodiments of the present application (this solution 1-2) are all better than those of the existing silicon wafers (existing solutions 1-3).
[0103] Furthermore, according to the comparison between Scheme 1-2 and Scheme 3-4 of the silicon wafer of the present application in Table 4 above, it can be seen that by adjusting the resistivity of the silicon wafer by adjusting the resistivity of the silicon wafer and the element amount of the recycled material, the electrical performance of the silicon wafer can be further improved, thereby further improving the photoelectric conversion efficiency of the solar cell.
[0104] The following further describes the optimized silicon wafer parameters corresponding to each process stage in combination with Table 4 above and the crystal pulling process of the present application.
[0105] Specifically, by adjusting the main heating power of the main heater 12 in the silicon melting stage to 110kw, the bottom heating power of the bottom heater 13 to 95kw, and the argon gas to 150, the temperature in the crucible is increased, and the moisture and volatile impurities in the crucible are removed, so that an isolation layer is formed on the inner wall of the crucible, reducing the absorption of oxygen and impurities during the crystal pulling process, thereby reducing the oxygen content of the subsequently prepared silicon wafers, so that the oxygen content of the silicon wafers of the present application is reduced by 0.19-0.36 compared with the oxygen content of the existing silicon wafers.
[0106] The zone melting single crystal itself has the advantages of fewer defects and impurities. By using the zone melting method to prepare the seed crystal in the seeding stage, and using it as the seed crystal for the Czochralski method, the situation of electrical performance degradation caused by defects and impurities in the crystal pulling process is effectively reduced, thereby improving the power generation efficiency of the silicon wafer prepared subsequently, so that the power generation efficiency of the silicon wafer of the present application is improved by 0.32% compared with the power generation efficiency of the existing silicon wafer.
[0107] By adjusting the cooling amount in the shoulder release stage to 9kw, the temperature of the equal-diameter head is relatively high. The higher equal-diameter temperature can make the migration of silicon atoms at the growth interface more active, so that atoms have more opportunities to arrange in the correct lattice position, thereby reducing the generation of defects such as dislocations and twins. At the same time, the diffusion rate of impurity atoms at the solid-liquid interface is accelerated, which helps to better distribute them in the liquid phase and solid phase, avoid local aggregation of impurities, and improve crystal quality.
[0108] By reducing the crystal pulling speed in the equal diameter stage to 80mm / h-90mm / h, the crystal growth interface is kept in a relatively stable state, and silicon atoms have enough time to arrange in the correct lattice position, reducing the generation of defects such as dislocations and twins. At the same time, the low crystal pulling speed makes the impurities in the crystal more evenly distributed, reducing the composite center formed by impurity aggregation, thereby improving the minority carrier lifetime of the silicon wafer prepared subsequently, so that the minority carrier lifetime of the silicon wafer of the present application is increased to 2349.28us compared with the minority carrier lifetime of the existing silicon wafer.
[0109] By gradually adjusting the rotation speed of the seed crystal in the equal-diameter stage from 7rpm to 6rpm, and the rotation speed of the crucible from 3rpm to 6rpm (the rotation speeds of the seed crystal 1 and the crucible are adjusted before the crystal rod reaches the reserved length), the temperature fluctuation at the crystal growth interface is reduced, the thermal stress is reduced, and the probability of defects such as dislocations inside the crystal is reduced, thereby improving the crystal quality and thus the quality of the prepared silicon wafer.
[0110] At the same time, due to the serious radial attenuation of the resistance of the high-resistance silicon rod, a lower crystal crucible rotation is used, and the doping elements have more time to diffuse in the melt, making the doping elements more evenly distributed in the crystal, reducing the radial attenuation of the silicon rod resistance, and making the electrical properties more stable. As shown in Table 2 above, the doping element in the crystal pulling process is 21.2g, the resistance level of the recycled material is 10Ω.cm, and the prepared resistivity is 14Ω.cm.
[0111] In the above preparation process, the resistivity of the silicon wafer is adjusted by adjusting the doping elements of the silicon wafer, and the crucible rotation speed and the seed crystal rotation speed are adjusted to allow the doping elements to have more sufficient time to diffuse in the melt, so that the doping elements are more evenly distributed in the crystal, and the radial attenuation of the silicon rod resistance is reduced, so as to obtain a high-resistance silicon rod by pulling the crystal. Therefore, in each silicon wafer prepared by slicing the crystal rod after making the crystal rod through the above preparation process, the resistivity of the silicon wafer is 8Ω.cm-24Ω.cm, so that the silicon wafer becomes a high-resistance silicon wafer, so that the silicon wafer is suitable for BC batteries (Back Contact).
[0112] In summary, this embodiment improves the photoelectric conversion efficiency of solar cells by adjusting the process method for making crystal rods, increasing the minority carrier lifetime, reducing the impurity content, improving crystal defects, and improving the quality of silicon wafers by adjusting the process method for making crystal rods. In addition, by adjusting the process method for making crystal rods, high-resistance crystal rods are obtained, so that high-resistance silicon wafers can be obtained after slicing the high-resistance crystal rods, and the high-resistance silicon wafers can be used to prepare BC cells.
[0113] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A method for producing a crystal rod, used for producing a single crystal silicon rod in a single crystal furnace, the single crystal furnace comprising a crucible (1), the crucible (1) containing silicon material (2), a main heater being arranged on the side wall of the crucible (1), and a bottom heater being arranged on the bottom of the crucible (1); characterized in that: The manufacturing method comprises: melting silicon, seeding, shouldering, shoulder rotation, equalizing diameters and finishing; In the silicon melting stage, the main heating power of the main heater is 100kw-120kw, the bottom heating power of the bottom heater is 90kw-100kw, and the argon flow rate into the crucible (1) is 140slpm-160slpm; In the seeding stage, the main heating power of the main heater is 65kw-70kw, the bottom heater is turned off, and the argon flow rate introduced into the crucible (1) from the seeding stage is adjusted to 110 slpm-130 slpm; The main heating power in the shoulder release stage is reduced by 8kw-10kw compared to the main heating power in the seeding stage.
2. The method for manufacturing a crystal rod according to claim 1, characterized in that: In the silicon melting stage, when the silicon material (2) has not yet melted into a liquid state, an isolation layer (11) is formed on the inner wall surface of the crucible (1).
3. The method for manufacturing a crystal rod according to claim 1, characterized in that: The seed crystals in the seeding stage are prepared by a zone melting method.
4. The method for manufacturing a crystal rod according to claim 1, characterized in that: In the equal diameter stage, the crystal pulling speed is reduced to 80 mm / h-90 mm / h.
5. The method for manufacturing a crystal rod according to claim 1, characterized in that: In the shoulder turning stage, the crucible to heel ratio is 0.11-0.13; In the equal diameter stage, the crucible to heel ratio is 00.07-0.
08.
6. The method for manufacturing a crystal rod according to claim 1, characterized in that: In the equal diameter stage, the manufacturing method further comprises: The rotation speed of the crucible (1) is gradually adjusted from 3 rpm to 6 rpm, and the rotation speed of the crucible (1) is adjusted before the crystal rod reaches a reserved length; The rotation speed of the seed crystal is gradually adjusted from 7 rpm to 6 rpm, and the rotation speed of the seed crystal is adjusted before the crystal rod reaches the reserved length.
7. The method for manufacturing a crystal rod according to claim 1, characterized in that: In the process of manufacturing the crystal rod, the manufacturing method further comprises: the furnace pressure of the crucible (1) is 3 torr-5 torr.
8. A silicon wafer, prepared by slicing a crystal rod after manufacturing it according to the manufacturing method of any one of claims 1 to 7, characterized in that: The resistivity of the silicon wafer is 8Ω.m-24Ω.m.
9. The silicon wafer according to claim 8, characterized in that: The element doping concentration of the silicon wafer is n, 2.393×10 14 atom / cm 3 ≤n≤1.593×10 16 tom / cm 3 .
10. A solar cell, characterized in that: The solar cell comprises the silicon wafer according to claim 8 or 9; The doping element of the silicon wafer includes at least one of phosphorus and antimony; The back side of the solar cell is provided with doping regions with different polarities.