Processing method for abnormal resistance value of vacancy type monocrystalline silicon wafer

Abstract

The invention belongs to the field of semiconductor monocrystalline silicon, and discloses a processing method for abnormal resistance of a vacancy type monocrystalline silicon wafer, which comprises the following steps of: S1, judging a silicon wafer defect type as a vacancy type abnormal resistance silicon wafer; s2, the heat treatment furnace is started, protective gas is introduced, the temperature is raised to 600-1000 DEG C, the silicon wafer with the abnormal resistance value is put in, and heat preservation is conducted for 10-120 min; s3, quickly transferring the silicon wafer to the outside of the heating furnace, and cooling the silicon wafer to room temperature in air; s4, carrying out acid corrosion cleaning treatment on the silicon wafer; and S5, after the treated silicon wafer is cleaned by pure water and dried by nitrogen blowing, a resistivity test is carried out by adopting four-probe resistivity equipment. The method can effectively eliminate the resistivity abnormity of the silicon wafer caused by the thermal donor effect, the silicon wafer mechanical damage layer and the V2O combination body are removed through the acid corrosion cleaning treatment, the surface of the silicon wafer is smooth and clean, the internal chemical bond is stable, the real resistivity value of the vacancy type monocrystalline silicon wafer with the abnormal resistance value can be rapidly and accurately recovered, and the method is suitable for large-scale popularization and application. And the measurement result is stable and reliable.

Description

Technical Field

[0001] The invention relates to the field of semiconductor single crystal silicon, and in particular to a method for processing abnormal resistance of a vacancy type single crystal silicon wafer. Background Art

[0002] During the CZ method of growing single crystal silicon crystals, the quartz crucible inevitably reacts under the high-temperature erosion of molten silicon. The oxygen produced by decomposition enters the melt and eventually enters the silicon crystal, which causes the CZ single crystal silicon to often contain a higher concentration of oxygen.

[0003] Usually, oxygen atoms in single crystal silicon exist in the form of interstitial oxygen, which is electrically neutral. However, due to the supersaturated oxygen in the crystal, the supersaturated interstitial oxygen will aggregate to form oxygen clusters (SiO4) during the crystal cooling process, becoming a donor for releasing electrons, called thermal donors. The initial rate of thermal donor formation is proportional to the fourth power of the original oxygen concentration, and the maximum thermal donor concentration is generated when annealing at 450℃, which is approximately the cube of the original oxygen concentration.

[0004] The thermal donors in single crystal silicon provide additional electrons to the silicon crystal due to their donor effect, which directly changes the carrier concentration in the single crystal silicon. Specifically, the electron concentration of the n-type silicon crystal increases, the carrier concentration increases, and the resistivity decreases; the holes in the p-type silicon crystal are recombined by electrons, the carrier concentration decreases, and the high resistivity is compensated. When the number of thermal donors is greater than the acceptor boron, the silicon crystal may even undergo a conductivity type inversion, changing from p-type silicon to n-type silicon, which destroys the electrical performance of the device.

[0005] At present, there are some literatures that record how to solve the problem of high resistivity of silicon rods caused by thermal donors. For example, CN115097209A introduces a pretreatment method for P-type lightly doped (boron-doped) single crystal silicon wafers before resistivity testing, which specifically includes (1) high-temperature annealing and rapid cooling of silicon crystals; (2) grinding and removing the iron-boron metal composite layer on the surface of the single crystal silicon wafer; (3) placing the single crystal silicon wafer in a constant temperature box for 4-8 hours of constant temperature treatment. This method can restore the resistance of the single crystal rod to the normal range, but grinding is a mechanical hard processing, which inevitably leaves microcracks and residual stress on the surface of the silicon wafer. The silicon wafer may be broken during the process of the test probe pressing the contact surface; in addition, the presence of residual stress will also cause the silicon wafer to warp or deform at the stress residual position, which is not conducive to resistivity measurement.

[0006] CN115369486A introduces a method for solving the problem of abnormal silicon rod resistance and conductivity type reversal, which specifically includes (1) heating the abnormal silicon rod to 600-700℃ and keeping it warm for 50-100min; (2) continuing to heat it to 850-950℃ and keeping it warm for 50-70min; (3) continuing to heat it to 1000-1200℃ and keeping it warm for 50-70min; (4) reducing the temperature of the silicon rod to 700-900℃ and keeping it warm for 50-70min; (5) continuing to cool the silicon rod to room temperature at a cooling rate greater than 120℃ / min. This method can solve the problem of conductivity type reversal and false high resistivity of P-type single crystal silicon rods with a target resistivity greater than 70 ohm-cm, but the heat treatment process is cumbersome and time-consuming, and is not suitable for actual production. In addition, if the heat treatment temperature is too high and the insulation time is too long, it is easy to generate secondary heat donors that are difficult to eliminate.

[0007] However, there are no reports on the treatment of certain defect types and target low-resistance single-crystal silicon wafers in the prior art. In the process of Czochralski single-crystal silicon growth, the ratio V / G of the pulling speed (V) and the temperature gradient (G) determines the type of native defects in the crystal. When V / G>ξ, vacancy defects appear. Since holes are carriers of p-type silicon wafers, and holes are easily combined with interstitial oxygen in silicon to form V2O complexes, the carrier concentration of vacancy-type silicon wafers is still low after traditional thermal annealing, and the resistivity is still abnormally high due to the influence of V2O complexes; at the same time, dislocations will be induced on the surface of the silicon wafer during the heat treatment process, resulting in surface mechanical damage and internal stress of the silicon wafer. There is no effective solution to the above two problems in the prior art. Therefore, it is urgent to develop a treatment method for restoring abnormal resistance for vacancy-type abnormal resistance silicon wafers. Summary of the invention

[0008] The purpose of the present invention is to provide a method for processing abnormal resistance of vacancy type single crystal silicon wafers, which has the advantages of stable detection and accurate results, and is used to solve the problems that after traditional thermal annealing of vacancy type single crystal silicon wafers, the carrier concentration is still low due to the influence of V2O combination, the resistivity is still abnormally high, fluctuates unstably, and the stable resistivity cannot be quickly measured.

[0009] In order to achieve the above object, the present invention adopts the following technical solution:

[0010] A method for processing abnormal resistance of vacancy type single crystal silicon wafer, comprising the following steps:

[0011] S1: Take a silicon wafer with abnormal resistance value whose defect type is determined to be vacancy type;

[0012] S2: Start the heat treatment furnace, fill it with protective gas, raise the temperature to 600-1000°C, put in the abnormal resistance silicon wafer, and keep it warm for 10-120 minutes;

[0013] S3: quickly transferring the abnormal resistance silicon wafer in step S2 outside the heating furnace and cooling it to room temperature in air;

[0014] S4: performing acid cleaning treatment on the silicon wafer after cooling in step S3;

[0015] S5: After washing and drying the silicon wafer processed in step S4, a resistivity test is performed.

[0016] In some specific implementation schemes, the abnormal resistance silicon wafer in step S1 is a silicon wafer whose resistivity test result differs from the target resistivity by more than 50%, or whose conductivity type is changed from p to n.

[0017] In some specific embodiments, the silicon wafer in step S1 is any one of a silicon wafer obtained after slicing a crystal rod, a silicon wafer after rolling, or a silicon wafer after grinding or polishing.

[0018] In some specific embodiments, the protective gas in step S2 is any one of helium, nitrogen and argon.

[0019] In some specific embodiments, the cooling in step S3 has an average cooling rate of not less than 50° C. / s.

[0020] In some specific embodiments, the cleaning solution used in the acid cleaning treatment in step S4 includes HF, an oxidant and an optional reaction buffer; preferably HF, HNO 3 and CH 3 COOH.

[0021] In some specific embodiments, the volume ratio of the components in the cleaning solution is HF:HNO 3 :CH 3 COOH=1: (0.5-10): (0.5-10).

[0022] In some specific embodiments, the cleaning time of the acid-corrosion cleaning treatment in step S4 is 5-30 minutes.

[0023] In some specific implementation schemes, the thickness of the silicon wafer removed from one side after the acid-etching cleaning treatment in step S4 is 100-250 μm.

[0024] In some specific implementation schemes, a four-probe resistivity device is used to perform resistivity testing in step S5.

[0025] In some specific implementation schemes, resistivity testing is performed at multiple points along the radial direction, preferably 5-11 testing points.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] The present invention can effectively eliminate a large number of thermal donors generated in the silicon wafer in the 450°C thermal history by performing rapid heat treatment on the single crystal silicon wafer with vacancy type abnormal resistance, and the heat treatment temperature and the holding time are properly controlled to avoid the regeneration of secondary new donors due to excessively high heat treatment temperature and excessively long holding time, resulting in the resistivity still seriously deviating from the target value; and after the acid corrosion cleaning treatment, the surface of the silicon wafer is flat and smooth, the internal chemical bonds are stable, and the V2O combination is cleaned and removed. The present invention can quickly and accurately restore the true resistivity value of the single crystal silicon wafer with vacancy type abnormal resistance, and the measurement result is stable and reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a schematic diagram of the distribution of radial resistivity measurement points of the silicon wafer of the present invention. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in combination with the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.

[0030] In the present invention, abnormal resistance refers to the situation that the resistivity of the single crystal silicon wafer is falsely high due to the thermal donor effect of the CZ method direct-pulled single crystal silicon, exceeding the target resistivity by 50% or more, and the conductivity type is inverted. The target resistivity is based on the actual dopant concentration added before pulling and is converted according to the "GB / T 13389-2014 Conversion Procedure for Resistivity and Dopant Concentration of Boron-doped, Phosphorus-doped and Arsenic-doped Silicon Single Crystals".

[0031] According to the target resistivity conversion formula (1) in boron-doped silicon single crystal, the actual dopant concentration is introduced to convert the theoretical target resistivity:

[0032]

[0033] Where:

[0034] ρ——resistivity, in ohm centimeter (Ω·cm);

[0035] N A ——Boron dopant concentration, per cubic centimeter (cm -3 ).

[0036] In the present invention, for example, in the crystal growth process, a single crystal silicon wafer with a target resistivity of ≤20 ohm·cm is obtained by doping, and the actual resistivity test result of the silicon wafer is ≥30 ohm·cm, it can be determined that the resistivity is abnormal; or the silicon wafer with the target resistivity should be a p-type silicon wafer, but the resistivity test result is determined to be n-type, it can also be determined that the resistivity is abnormal.

[0037] A method for processing abnormal resistance of vacancy type single crystal silicon wafer, comprising the following steps:

[0038] S1: Take a single crystal silicon wafer with a vacancy defect type and use a four-probe resistivity device to perform a resistivity test. If the test result is significantly different from the target resistivity, for example, greater than 50%, or the conductivity type changes from p to n, it is judged to be an abnormal resistance silicon wafer.

[0039] In the present invention, there is no particular limitation on the silicon wafer, as long as it is a vacancy type single crystal silicon wafer with a target resistivity of ≤20 ohm·cm, whether it is a silicon wafer obtained by slicing a crystal rod, a silicon wafer after rolling, or a silicon wafer after grinding or polishing. Among them, the aforementioned target resistivity of ≤20 ohm·cm is only for example, and does not limit the technical solution of the present invention to only be applicable to abnormal silicon wafers with a target resistivity of ≤20 ohm·cm.

[0040] S2: Start the heat treatment furnace and fill it with protective gas, such as helium, nitrogen or argon, raise the temperature to 600-1000℃ (for example, 600℃, 660℃, 700℃, 750℃, 800℃, 850℃, 900℃, 950℃, 1000℃, etc.), put in the abnormal resistance silicon wafer, and keep it warm for 10-120min, for example, 10min, 20min, 30min, 40min, 50min, 60min, 70min, 80min, 90min, 100min, 110min, 120min, etc.

[0041] S3: Quickly transfer the abnormal resistance silicon wafer outside the heating furnace and cool it to room temperature in the air; wherein, the cooling in step S3 has an average cooling rate of not less than 50°C / s, for example, the average cooling rate is 50°C / s, 55°C / s, 60°C / s, 65°C / s, 70°C / s, 80°C / s, etc.

[0042] S4: performing acid cleaning treatment on the silicon wafer.

[0043] In this step, the main components of the cleaning solution for acid corrosion cleaning treatment include HF, an oxidant and an optional reaction buffer; wherein the oxidant can be, for example, common nitric acid or hydrogen peroxide, and the reaction buffer is acetic acid; the cleaning solution is preferably nitric acid, acetic acid, and hydrofluoric acid. Preferably, the volume ratio of the three is about HF:HNO 3 :CH3 COOH=1:(0.5-10):(0.5-10), for example, 1:2:0.6, 1:3:0.8, 1:4:1, 1:3.5:1.5, etc. Among them, HNO 3 As an oxidant, HF is used to strip the oxide layer on the surface of the silicon wafer, and CH 3 COOH mainly plays a dilution and buffering role. The treatment method of the present invention is to use the oxidant HNO to clean the vacant single crystal silicon wafer by acid corrosion. 3 Oxidize the surface of silicon wafer to generate SiO 2 , and then use the etching agent HF to strip SiO 2 Combined with V2O, exposing the internal silicon crystal, buffer CH 3 COOH is used to stabilize the reaction rate, which can quickly and evenly remove the surface mechanical damage layer and release the internal stress of the silicon crystal.

[0044] In this step, the acid cleaning time is 5-30min, for example, 5min, 8min, 10min, 15min, 20min, 25min, 30min, etc.; the single-sided removal thickness of the silicon wafer after acid cleaning is about 100-250μm, for example, 110μm, 130μm, 150μm, 160μm, 175μm, 200μm, 210μm, 215μm, 230μm, 240μm, etc., so that the acid-washed silicon wafer has a smooth and bright silicon wafer surface after polishing.

[0045] S5: After the silicon wafers treated as above are cleaned with pure water and dried with nitrogen, a resistivity test is performed using a four-probe resistivity device.

[0046] In this step, the steps of washing the silicon wafer with pure water and drying with nitrogen can refer to the prior art without special limitation. The resistivity test using a four-probe resistivity device can also refer to the prior art for testing. Preferably, multiple points are tested continuously along the radial direction for multiple times, for example, 5-11 points are selected in the radial direction, such as 5, 6, 7, 8, 9, 10 points, etc., for continuous testing, and the average is taken.

[0047] The present invention is further explained below by more specific examples, but does not constitute any limitation.

[0048] Example 1

[0049] S1: Take the truncated single crystal silicon wafer p 1,1 , use running pure water and detergent to clean, remove silicon mud, fingerprints and other dirt on the surface of the silicon wafer, blow dry with nitrogen, and use a four-probe resistivity device to test the resistivity. If the test result differs from the target resistivity by more than 50%, it is judged to be an abnormal resistance silicon wafer;

[0050] S2: Take the single crystal silicon wafer p at the same position 1.2 , perform defect detection, and judge the defect type of silicon wafer to be vacancy type;

[0051] S3: Start the heat treatment furnace and fill it with nitrogen protective gas. Raise the temperature to 600℃ at a rate of 20℃ / min and put the abnormal resistance silicon wafer p 1.2 , keep warm for 10 minutes;

[0052] S4: Place the single crystal silicon wafer p 1.2 Quickly transfer outside the heating furnace and cool to room temperature in air with an average cooling rate of not less than 50℃ / s;

[0053] S5: The silicon wafer is subjected to an acid cleaning treatment, wherein the volume ratio of the acid cleaning solution is approximately HF:HNO 3 :CH 3 COOH = 1:0.5:0.5, cleaning time is maintained for 10 minutes;

[0054] S6: The processed p 1.2 After the silicon wafer is cleaned with pure water and dried with nitrogen, a four-probe resistivity test is performed.

[0055] Example 2

[0056] S1: Take the truncated single crystal silicon wafer p 2,1 , cleaned with running pure water and detergent to remove silicon mud, fingerprints and other dirt on the surface of the silicon wafer, dried with nitrogen, and then tested with a four-probe resistivity device. The test results showed that the conductivity type changed from p to n, and it was judged to be an abnormal resistance silicon wafer;

[0057] S2: Take the single crystal silicon wafer p at the same position 2.2 , perform defect detection, and judge the defect type of silicon wafer to be vacancy type;

[0058] S3: Start the heat treatment furnace and fill it with nitrogen protective gas. Raise the temperature to 650℃ at a rate of 20℃ / min and put the abnormal resistance silicon wafer p 2.2 , keep warm for 30 minutes;

[0059] S4: Place the single crystal silicon wafer p 2.2 Quickly transfer outside the heating furnace and cool to room temperature in air with an average cooling rate of not less than 50℃ / s;

[0060] S5: The silicon wafer is subjected to an acid cleaning treatment, wherein the volume ratio of the acid cleaning solution is approximately HF:HNO 3 :CH 3 COOH=1:2:3, cleaning time is kept at 5min;

[0061] S6: The processed p2.2 After the silicon wafer is cleaned with pure water and dried with nitrogen, a four-probe resistivity test is performed.

[0062] Example 3

[0063] S1: Take the truncated single crystal silicon wafer p 3,1 , use running pure water and detergent to clean, remove silicon mud, fingerprints and other dirt on the surface of the silicon wafer, blow dry with nitrogen, and use a four-probe resistivity device to test the resistivity. If the test result differs from the target resistivity by more than 50%, it is judged to be an abnormal resistance silicon wafer;

[0064] S2: Take the single crystal silicon wafer p at the same position 3,2 , perform defect detection, and judge the defect type of silicon wafer to be vacancy type;

[0065] S3: Start the heat treatment furnace and fill it with nitrogen protective gas, raise the temperature to 700°C at a rate of 20°C / min, put the abnormal resistance silicon wafer p1 in, and keep it warm for 60 minutes;

[0066] S4: Place the single crystal silicon wafer p 3,2 Quickly transfer outside the heating furnace and cool to room temperature in air with an average cooling rate of not less than 50℃ / s;

[0067] S5: The silicon wafer is subjected to an acid cleaning treatment, wherein the volume ratio of the acid cleaning solution is approximately HF:HNO 3 :CH 3 COOH=1:5:3, cleaning time is maintained at 20min;

[0068] S6: The processed p 3,2 After the silicon wafer is cleaned with pure water and dried with nitrogen, a four-probe resistivity test is performed.

[0069] Example 4

[0070] S1: Take the truncated single crystal silicon wafer p 4,1 , cleaned with running pure water and detergent to remove silicon mud, fingerprints and other dirt on the surface of the silicon wafer, dried with nitrogen, and then tested with a four-probe resistivity device. The test results showed that the conductivity type changed from p to n, and it was judged to be an abnormal resistance silicon wafer;

[0071] S2: Take the single crystal silicon wafer p at the same position 4,2 , perform defect detection, and judge the defect type of silicon wafer to be vacancy type;

[0072] S3: Start the heat treatment furnace and fill it with nitrogen protective gas, raise the temperature to 750°C at a rate of 20°C / min, put the abnormal resistance silicon wafer p1 in, and keep it warm for 90 minutes;

[0073] S4: Place the single crystal silicon wafer p4,2 Quickly transfer outside the heating furnace and cool to room temperature in air with an average cooling rate of not less than 50℃ / s;

[0074] S5: The silicon wafer is subjected to an acid cleaning treatment, wherein the volume ratio of the acid cleaning solution is approximately HF:HNO 3 :CH 3 COOH = 1:3:1, cleaning time is maintained for 10 minutes;

[0075] S6: The processed p 4,2 After the silicon wafer is cleaned with pure water and dried with nitrogen, a four-probe resistivity test is performed.

[0076] Example 5

[0077] S1: Take the truncated single crystal silicon wafer p 5,1 , use running pure water and detergent to clean, remove silicon mud, fingerprints and other dirt on the surface of the silicon wafer, blow dry with nitrogen, and use a four-probe resistivity device to test the resistivity. If the test result differs from the target resistivity by more than 50%, it is judged to be an abnormal resistance silicon wafer;

[0078] S2: Take the single crystal silicon wafer p at the same position 5,2 , perform defect detection, and judge the defect type of silicon wafer to be vacancy type;

[0079] S3: Start the heat treatment furnace and fill it with nitrogen protective gas, raise the temperature to 800°C at a rate of 20°C / min, put the abnormal resistance silicon wafer p1 in, and keep it warm for 120 minutes;

[0080] S4: Place the single crystal silicon wafer p 5,2 Quickly transfer outside the heating furnace and cool to room temperature in air with an average cooling rate of not less than 50℃ / s;

[0081] S5: The silicon wafer is subjected to an acid cleaning treatment, wherein the volume ratio of the acid cleaning solution is approximately HF:HNO 3 :CH 3 COOH = 1:3:10, cleaning time is maintained for 30 minutes;

[0082] S6: The processed p 5,2 After the silicon wafer is cleaned with pure water and dried with nitrogen, a four-probe resistivity test is performed.

[0083] Example 6

[0084] S1: Take the truncated single crystal silicon wafer p 6,1, cleaned with running pure water and detergent to remove silicon mud, fingerprints and other dirt on the surface of the silicon wafer, dried with nitrogen, and then tested with a four-probe resistivity device. The test results showed that the conductivity type changed from p to n, and it was judged to be an abnormal resistance silicon wafer;

[0085] S2: Take the single crystal silicon wafer p at the same position 6,2 , perform defect detection, and judge the defect type of silicon wafer to be vacancy type;

[0086] S3: Start the heat treatment furnace and fill it with nitrogen protective gas, raise the temperature to 850°C at a rate of 20°C / min, put the abnormal resistance silicon wafer p1 in, and keep it warm for 90 minutes;

[0087] S4: Place the single crystal silicon wafer p 6,2 Quickly transfer outside the heating furnace and cool to room temperature in air with an average cooling rate of not less than 50℃ / s;

[0088] S5: The silicon wafer is subjected to an acid cleaning treatment, wherein the volume ratio of the acid cleaning solution is approximately HF:HNO 3 :CH 3 COOH = 1:3:5, cleaning time is maintained at 50min;

[0089] S6: The processed p 6,2 After the silicon wafer is cleaned with pure water and dried with nitrogen, a four-probe resistivity test is performed.

[0090] Example 7

[0091] S1: Take the truncated single crystal silicon wafer p 7,1 , use running pure water and detergent to clean, remove silicon mud, fingerprints and other dirt on the surface of the silicon wafer, blow dry with nitrogen, and use a four-probe resistivity device to test the resistivity. If the test result differs from the target resistivity by more than 50%, it is judged to be an abnormal resistance silicon wafer;

[0092] S2: Take the single crystal silicon wafer p at the same position 7,2 , perform defect detection, and judge the defect type of silicon wafer to be vacancy type;

[0093] S3: Start the heat treatment furnace and fill it with nitrogen protective gas, raise the temperature to 900°C at a rate of 20°C / min, put the abnormal resistance silicon wafer p1 in, and keep it warm for 60 minutes;

[0094] S4: Place the single crystal silicon wafer p 7,2 Quickly transfer outside the heating furnace and cool to room temperature in air with an average cooling rate of not less than 50℃ / s;

[0095] S5: The silicon wafer is subjected to an acid cleaning treatment, wherein the volume ratio of the acid cleaning solution is approximately HF:HNO 3 :CH3 COOH = 1:7:1, cleaning time is maintained for 10 minutes;

[0096] S6: The processed p 7,2 After the silicon wafer is cleaned with pure water and dried with nitrogen, a four-probe resistivity test is performed.

[0097] Example 8

[0098] S1: Take the truncated single crystal silicon wafer p 8,1 , cleaned with running pure water and detergent to remove silicon mud, fingerprints and other dirt on the surface of the silicon wafer, dried with nitrogen, and then tested with a four-probe resistivity device. The test results showed that the conductivity type changed from p to n, and it was judged to be an abnormal resistance silicon wafer;

[0099] S2: Take the single crystal silicon wafer p at the same position 8,2 , perform defect detection, and judge the defect type of silicon wafer to be vacancy type;

[0100] S3: Start the heat treatment furnace and fill it with nitrogen protective gas, raise the temperature to 950°C at a rate of 20°C / min, put the abnormal resistance silicon wafer p1 in, and keep it warm for 30 minutes;

[0101] S4: Place the single crystal silicon wafer p 8,2 Quickly transfer outside the heating furnace and cool to room temperature in air with an average cooling rate of not less than 50℃ / s;

[0102] S5: The silicon wafer is subjected to an acid cleaning treatment, wherein the volume ratio of the acid cleaning solution is approximately HF:HNO 3 :CH 3 COOH = 1:10:1, cleaning time is maintained at 20 min;

[0103] S6: The processed p 8,2 After the silicon wafer is cleaned with pure water and dried with nitrogen, a four-probe resistivity test is performed.

[0104] Example 9

[0105] S1: Take the truncated single crystal silicon wafer p 9,1 , use running pure water and detergent to clean, remove silicon mud, fingerprints and other dirt on the surface of the silicon wafer, blow dry with nitrogen, and use a four-probe resistivity device to test the resistivity. If the test result differs from the target resistivity by more than 50%, it is judged to be an abnormal resistance silicon wafer;

[0106] S2: Take the single crystal silicon wafer p at the same position 9,2 , perform defect detection, and judge the defect type of silicon wafer to be vacancy type;

[0107] S3: Start the heat treatment furnace and fill it with nitrogen protective gas, raise the temperature to 1000°C at a rate of 20°C / min, put the abnormal resistance silicon wafer p1 in, and keep it warm for 10 minutes;

[0108] S4: Place the single crystal silicon wafer p 9,2 Quickly transfer outside the heating furnace and cool to room temperature in air with an average cooling rate of not less than 50℃ / s;

[0109] S5: The silicon wafer is subjected to an acid cleaning treatment, wherein the volume ratio of the acid cleaning solution is approximately HF:HNO 3 :CH 3 COOH = 1:4:8, cleaning time is maintained for 30 minutes;

[0110] S6: The processed p 9,2 After the silicon wafer is cleaned with pure water and dried with nitrogen, a four-probe resistivity test is performed.

[0111] Comparative Example 1

[0112] S1: Take the truncated single crystal silicon wafer p in Example 4 4,1 , cleaned with running pure water and detergent to remove silicon mud, fingerprints and other dirt on the surface of the silicon wafer, dried with nitrogen, and then tested with a four-probe resistivity device. The test results showed that the conductivity type changed from p to n, and it was judged to be an abnormal resistance silicon wafer;

[0113] S2: Take the single crystal silicon wafer p at the same position 4,3 , perform defect detection, and judge the defect type of silicon wafer to be vacancy type;

[0114] S3: The silicon wafer is subjected to an acid cleaning treatment, wherein the volume ratio of the acid cleaning solution is approximately HF:HNO 3 :CH 3 COOH = 1:3:1, cleaning time is maintained for 10 minutes;

[0115] S4: The p 4,3 After the silicon wafer is cleaned with pure water and dried with nitrogen, a four-probe resistivity test is performed.

[0116] Comparative Example 2

[0117] S1: Take the truncated single crystal silicon wafer p in Example 4 4,1 , cleaned with running pure water and detergent to remove silicon mud, fingerprints and other dirt on the surface of the silicon wafer, dried with nitrogen, and then tested with a four-probe resistivity device. The test results showed that the conductivity type changed from p to n, and it was judged to be an abnormal resistance silicon wafer;

[0118] S2: Take the single crystal silicon wafer p at the same position 4,4, perform defect detection, and judge the defect type of silicon wafer to be vacancy type;

[0119] S3: Start the heat treatment furnace and fill it with nitrogen protective gas, raise the temperature to 750°C at a rate of 20°C / min, put the abnormal resistance silicon wafer p1 in, and keep it warm for 90 minutes;

[0120] S4: Place the single crystal silicon wafer p 4,4 Quickly transfer outside the heating furnace and cool to room temperature in air with an average cooling rate of not less than 50℃ / s;

[0121] S5: The processed p 4,4 After the silicon wafer is cleaned with pure water and dried with nitrogen, a four-probe resistivity test is performed.

[0122] Comparative Example 3

[0123] S1: Take the truncated single crystal silicon wafer p in Example 4 4,1 , use running pure water and detergent to clean, remove silicon mud, fingerprints and other dirt on the surface of the silicon wafer, dry with nitrogen, and use a four-probe resistivity device to perform a resistivity test. The test results show that the conductivity type changes from p to n, and it is judged to be an abnormal resistance silicon wafer.

[0124] S2: Take the single crystal silicon wafer p at the same position 4,5 , defect detection is performed, and the defect type of the silicon wafer is judged to be vacancy type.

[0125] S3: The above p 4,5 After the silicon wafer is cleaned with pure water and dried with nitrogen, a four-probe resistivity test is performed.

[0126] (Data Analysis)

[0127] The resistivity of the single crystal silicon wafers processed by Examples 1-9 and Comparative Example 1 was tested respectively, and the test results are shown in Table 1.

[0128] Resistivity test table 1 (unit: ohm centimeter)

[0129]

[0130] The test points are distributed as follows: Figure 1 shown.

[0131] Compared with Examples 1-9, according to the doping concentration calculation formula, the target resistivity of the selected silicon wafers is 20±1 ohm-cm. After being processed by the solution of the present invention, the target resistivity is achieved, which proves that the method is accurate and effective.

[0132] Comparing Example 4 with Comparative Example 1, it can be shown that the annealing treatment of the method of the present invention can effectively eliminate the thermal donors generated in large quantities in the silicon wafer during the 450°C thermal history, restore the conductivity type, and the heat treatment temperature and holding time are properly controlled to avoid the re-generation of secondary new donors due to excessively high heat treatment temperature and excessively long holding time, resulting in the resistivity still seriously deviating from the target value.

[0133] Comparing Example 4 with Comparative Example 2, it can be shown that the method of the present invention performs acid corrosion cleaning treatment on the vacancy-type single crystal silicon wafer after annealing, which can remove the V2O complex generated by the combination of the vacancy and the interstitial oxygen in the silicon, restore the carrier concentration, and solve the problem of abnormally high resistivity; at the same time, the mechanical damage layer caused by the stress introduced on the silicon wafer surface due to the rapid thermal treatment is removed, and the internal silicon crystal is exposed. After the acid corrosion cleaning treatment, the surface of the silicon wafer is smooth and clean, the internal chemical bonds are stable, and its surface changes very little during the subsequent testing process.

[0134] By comparing Example 4 with Comparative Example 3, it can be determined that the resistivity of the vacancy-type single crystal silicon wafer treated by thermal annealing + acid corrosion cleaning according to the method of the present invention is significantly restored to normal, and fluctuates around the target resistivity value within the allowable error range. The present invention can quickly and accurately restore the true resistivity value of the single crystal silicon wafer with vacancy-type abnormal resistance, and has the advantages of stable and reliable measurement results and accurate testing.

[0135] Although the embodiments of the present invention have been disclosed as above, they are not limited to those listed in the specification and the implementation mode. They can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and shown here.

Claims

1. A method for treating abnormal resistance of vacancy type single crystal silicon wafers. It is characterized in that The following steps are involved: S1: Take a silicon wafer with abnormal resistance value whose defect type is determined to be vacancy type; S2: Start the heat treatment furnace, fill it with protective gas, raise the temperature to 600-1000°C, put in the abnormal resistance silicon wafer, and keep it warm for 10-120 minutes; S3: quickly transferring the abnormal resistance silicon wafer obtained in step S2 outside the heating furnace and cooling it to room temperature in air; S4: performing acid cleaning treatment on the silicon wafer cooled in step S3; S5: After washing and drying the silicon wafer processed in step S4, a resistivity test is performed.

2. The method for treating abnormal resistance of vacancy-type single crystal silicon wafer according to claim 1, It is characterized in that The abnormal resistance silicon wafer in step S1 is a silicon wafer whose resistivity test result differs from the target resistivity by more than 50% or whose conductivity type changes from p to n; and / or The silicon wafer in step S1 is any one of a silicon wafer obtained by slicing a crystal rod, a silicon wafer obtained by rolling, or a silicon wafer obtained by grinding or polishing.

3. The method for treating abnormal resistance of vacancy-type single crystal silicon wafer according to claim 1, It is characterized in that The protective gas in step S2 is any one of helium, nitrogen and argon.

4. The method for treating abnormal resistance of vacancy-type single crystal silicon wafer according to claim 1, It is characterized in that The cooling in step S3 has an average cooling rate of not less than 50°C / s.

5. The method for treating abnormal resistance of vacancy-type single crystal silicon wafer according to claim 1, It is characterized in that The cleaning solution used in the acid cleaning treatment in step S4 includes HF, an oxidant and an optional reaction buffer; preferably HF, HNO 3 and CH 3 COOH.

6. The method for treating abnormal resistance of vacancy-type single crystal silicon wafer according to claim 5, It is characterized in that The volume ratio of each component in the cleaning solution is HF:HNO 3 :CH 3 COOH=1: (0.5-10): (0.5-10).

7. The method for treating abnormal resistance of vacancy-type single crystal silicon wafer according to claim 6, It is characterized in that The cleaning time of the acid corrosion cleaning treatment in step S4 is 5-30 minutes.

8. The method for treating abnormal resistance of vacancy-type single crystal silicon wafer according to claim 7, It is characterized in that The thickness of the silicon wafer removed from one side after the acid-etching cleaning treatment in step S4 is 100-250 μm.

9. The method for treating abnormal resistance of vacancy-type single crystal silicon wafer according to claim 1, It is characterized in that In step S5, a four-probe resistivity device is used to perform resistivity testing.

10. The method for treating abnormal resistance of vacancy-type single crystal silicon wafer according to claim 9, It is characterized in that Conduct resistivity tests at multiple points along the radial direction, preferably 5 to 11 test points.

Images