Array substrate, display panel and display device

Abstract

The invention discloses an array substrate, a display panel and a display device, and aims to solve the problems of light leakage and non-uniform light leakage at a via hole where a touch electrode is conducted with a touch wire and a via hole where a pixel electrode is conducted with a transistor, and the problem that a lap joint is easy to break and poor when the pixel electrode is in lap joint with a drain electrode. The array substrate comprises: a substrate; a first metal layer; a first insulating layer; the first lap joint electrode is electrically connected with the first electrode through the first via hole; the second lap joint electrode is electrically connected with the first signal line through the second via hole; a second insulating layer; a second electrode layer; the second electrode is electrically connected with the first lap electrode through the third via hole, a part of the first bridge electrode is electrically connected with the second lap electrode through the fourth via hole, and the other part of the first bridge electrode is electrically connected with the first electrode through the fifth via hole.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] With the popularity of automotive, head-mounted and other types of products, curved screen LCD products with a certain curvature have appeared in more and more application scenarios. Hard screen LCDs are very prone to color deviation and light leakage during the bending process. In order to improve the display quality of LCD curved screen display devices, the color filter substrate and array base integration (COA) technology has been applied. This technology can effectively avoid the deviation of the array substrate and the color filter (CF) substrate during the bending process, which affects the aperture ratio of the display device and causes color deviation and light leakage. Since the COA substrate can effectively reduce the risk of light leakage caused by the deviation of the cell, the width of the black matrix can be effectively reduced during the design, which can effectively increase the pixel aperture ratio and thus increase the panel transmittance.

[0003] The current COA structure display panel, see Figure 1 As shown, there are problems of light leakage and uneven light leakage at the via holes where the touch electrode and the touch line are connected, and at the via holes where the pixel electrode and the transistor are connected. In addition, when the pixel electrode and the drain are overlapped, the overlapped joint is prone to breakage. Summary of the Invention

[0004] The present invention provides an array substrate, a display panel and a display device to improve the problems of light leakage and uneven light leakage at the via holes where the touch electrodes and touch lines are connected, and at the via holes where the pixel electrodes and transistors are connected, as well as the problem of fracture easily occurring at the overlap when the pixel electrodes and drain electrodes are overlapped.

[0005] An embodiment of the present invention provides an array substrate, comprising:

[0006] substrate;

[0007] A first metal layer, located on one side of the substrate, includes: a first electrode and a first signal line;

[0008] a first insulating layer, located on a side of the first metal layer facing away from the substrate, and having a first via hole and a second via hole;

[0009] A first electrode layer is located on a side of the first insulating layer away from the first metal layer, comprising: a plurality of first electrodes, a first strapping electrode, and a second strapping electrode; the first strapping electrode is electrically connected to the first electrode through the first via hole; the second strapping electrode is electrically connected to the first signal line through the second via hole;

[0010] a second insulating layer, located on a side of the first electrode layer facing away from the first insulating layer, having a third via hole, a fourth via hole, and a fifth via hole; an orthographic projection of the third via hole on the substrate having an overlapping area with an orthographic projection of the first strapping electrode on the substrate; and an orthographic projection of the fourth via hole on the substrate having an overlapping area with an orthographic projection of the second strapping electrode on the substrate;

[0011] The second electrode layer is located on the side of the first electrode layer away from the first metal layer, and includes: multiple second electrodes and a first bridging electrode; the second electrode is electrically connected to the first bridging electrode through the third via, part of the first bridging electrode is electrically connected to the second bridging electrode through the fourth via, and the other part is electrically connected to the first electrode through the fifth via.

[0012] In a possible implementation manner, the third via hole is located at a center of an orthographic projection of the substrate, and coincides with a center of an orthographic projection of the first via hole of the substrate.

[0013] In a possible implementation manner, the fourth via hole is located at a center of an orthographic projection of the substrate, and coincides with a center of an orthographic projection of the second via hole on the substrate.

[0014] In a possible implementation manner, the orthographic projection area of ​​the first bonding electrode on the substrate is equal to the orthographic projection area of ​​the second bonding electrode on the substrate.

[0015] In a possible implementation, the second electrode includes: a second electrode body, and a second electrode bridging portion connected to the second electrode body; the second electrode is electrically connected to the first bridging electrode via the second electrode bridging portion;

[0016] The second electrode overlapping portion includes: a first sub-electrode portion filled in the third via hole; the first overlapping electrode includes: a first sub-overlapping portion located at the bottom of the first via hole, and a second sub-overlapping portion covering the side wall of the third via hole;

[0017] The second insulating layer further includes a first filling portion filled between the first sub-electrode portion and the second sub-lap portion.

[0018] In a possible implementation, the first bridging electrode includes: a second sub-electrode portion filled in the fourth via hole; the second bridging electrode includes: a third sub-bridging portion located at the bottom of the second via hole, and a fourth sub-bridging portion covering the sidewall of the second via hole;

[0019] The second insulating layer further includes a second filling portion filled between the second sub-electrode portion and the fourth sub-bridging portion.

[0020] In a possible implementation manner, the orthographic projection of the first bridging electrode on the substrate covers the orthographic projection of the fourth via hole on the substrate.

[0021] In a possible implementation manner, a minimum distance between the first bridging electrode and the second electrode is greater than 3.0 μm.

[0022] In a possible implementation manner, the minimum distance between the first bonding electrode and the first electrode is greater than 2.7 μm; and the minimum distance between the second bonding electrode and the first electrode is greater than 2.7 μm.

[0023] In a possible implementation, the array substrate includes: a color filter layer; and the first insulating layer includes the color filter layer.

[0024] In a possible implementation, the array substrate further includes: a black matrix layer located on a side of the color filter layer facing the substrate; the first insulating layer includes the black matrix layer;

[0025] The black matrix layer has a first black matrix via hole and a second black matrix via hole; the first via hole includes the first black matrix via hole, and the second via hole includes the second black matrix via hole.

[0026] In a possible implementation, the array substrate further includes: a planar layer located between the color filter layer and the first electrode layer, and a first passivation layer located between the black matrix layer and the first metal layer;

[0027] The first insulating layer further includes: the planar layer, and the first passivation layer.

[0028] In a possible implementation, the first electrode is a touch electrode, and the second electrode is a pixel electrode.

[0029] An embodiment of the present invention further provides a display panel, comprising the array substrate provided by the embodiment of the present invention.

[0030] An embodiment of the present invention further provides a display device, comprising the display panel provided by the embodiment of the present invention.

[0031] The beneficial effects of the embodiments of the present invention are as follows: In the embodiments of the present invention, the first electrode layer includes: a first electrode, a first overlapping electrode, and a second overlapping electrode, and the second electrode layer includes a second electrode and a first bridging electrode; the second electrode is electrically connected to the first electrode through the first overlapping electrode, and the first electrode is electrically connected to the first signal line through the first bridging electrode and the second overlapping electrode, so that the conductive structure between the first electrode and the first signal line at the location of the fourth via hole is consistent with the conductive structure between the second electrode and the first electrode, thereby effectively reducing light leakage at the location of the fourth via hole when the first electrode and the first signal line are conductive. In this case, the light leakage at the via hole where the first electrode is connected to the first signal line and the light leakage at the via hole where the second electrode is connected to the first electrode are roughly the same; moreover, compared with the direct electrical connection between the second electrode and the first electrode, the required via hole is deeper, and the second electrode is prone to breakage. In the embodiment of the present invention, the second electrode is electrically connected to the first electrode through the first overlapping electrode, and a good overlap can be achieved through the first overlapping electrode, thereby improving the problem of the second electrode being affected by the deep hole and breaking. Moreover, the thickness of the first overlapping electrode is used to reduce the hole depth, thereby reducing the difficulty of exposing the film layer above the first overlapping electrode and reducing the risk of residue in the hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 Schematic diagram of light leakage at the touch hole and pixel hole in the prior art;

[0033] Figure 2 for Figure 3A Corresponding cross-sectional schematic diagram;

[0034] Figure 3A A schematic top view of a portion of film layers in an array substrate provided by an embodiment of the present invention;

[0035] Figure 3B for Figure 3A Schematic diagram of a single film layer of the corresponding first electrode layer;

[0036] Figure 3C for Figure 3A Schematic diagram of a single film layer of the corresponding second electrode layer;

[0037] Figure 4A Schematic diagram of a single film layer of the light-shielding layer;

[0038] Figure 4B Schematic diagram of a single film layer of the active layer;

[0039] Figure 4C Schematic diagram of a single film layer of the gate line layer;

[0040] Figure 4D Schematic diagram of a single film of the interlayer dielectric layer;

[0041] Figure 4E Schematic diagram of a single film layer of the source and drain layer;

[0042] Figure 4F Schematic diagram of a flat single film layer;

[0043] Figure 4G Schematic diagram of a single film layer of a touch electrode layer;

[0044] Figure 4H Schematic diagram of a single film layer of the second passivation layer;

[0045] Figure 4I Schematic diagram of a single film layer of the pixel electrode layer. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0047] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0048] As used herein, "about" or "approximately the same" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "approximately the same" can mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%.

[0049] In the accompanying drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes of the figures are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Thus, the embodiments described herein should not be construed as limited to the specific shapes of the regions as shown herein, but rather include deviations in shape that result from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp corners illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0050] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0051] See also Figure 2 、 Figure 3A-3C As shown, Figure 2 for Figure 3A The corresponding cross-sectional diagram, Figure 3A A schematic top view of a portion of a film layer in an array substrate provided by an embodiment of the present invention is shown. Figure 3B for Figure 3A The corresponding single film schematic diagram of the first electrode layer, Figure 3C for Figure 3A A schematic diagram of a single film layer of a corresponding second electrode layer. An embodiment of the present invention provides an array substrate, including:

[0052] Substrate 1;

[0053] The first metal layer 2 is located on one side of the substrate 1 and includes: a first electrode 21 and a first signal line 22; specifically, the first metal layer 2 may be a source-drain metal layer, the first electrode 21 may be a drain of the transistor, and the first metal layer 2 may further include a second electrode 23, which may be a drain of the transistor;

[0054] The first insulating layer 3 is located on a side of the first metal layer 2 facing away from the substrate 1 and has a first via K1 and a second via K2; specifically, the first via K1 can expose a portion of the first electrode 21, and the second via K2 can expose a portion of the first signal line 22;

[0055] The first electrode layer 4 is located on the side of the first insulating layer 3 away from the first metal layer 2, and includes: a plurality of first electrodes 40, a first strapping electrode 41, and a second strapping electrode 42; the first strapping electrode 41 is electrically connected to the first electrode 21 through the first via K1; the second strapping electrode 42 is electrically connected to the first signal line 22 through the second via K2; specifically, the first electrode layer 4 can be a touch electrode layer, which can be reused as a common electrode layer; the first electrode layer 4 can be a transparent electrode layer; the orthographic projection of the first strapping electrode 41 on the substrate 1 has an overlapping area with the orthographic projection of the first via K1 on the substrate 1; the orthographic projection of the second strapping electrode 42 on the substrate 1 has an overlapping area with the orthographic projection of the second via K2 on the substrate 1; specifically, the first electrode 40 can be a touch electrode block;

[0056] The second insulating layer 5 is located on a side of the first electrode layer 4 facing away from the first insulating layer 3, and has a third via hole K3, a fourth via hole K4, and a fifth via hole K5; the orthographic projection of the third via hole K3 on the substrate 1 overlaps with the orthographic projection of the first strapping electrode 41 on the substrate 1; the orthographic projection of the fourth via hole K4 on the substrate 1 overlaps with the orthographic projection of the second strapping electrode 42 on the substrate 1; the third via hole K3 exposes a portion of the first strapping electrode 41, the fourth via hole K4 exposes a portion of the second strapping electrode 42, and the fifth via hole K5 exposes a portion of the first electrode 40;

[0057] The second electrode layer 6 is located on the side of the first electrode layer 4 facing away from the first metal layer 2 and includes: a plurality of second electrodes 60 and a first bridging electrode 61; the second electrode 60 is electrically connected to the first strapping electrode 41 through the third via K3, a portion of the first bridging electrode 61 is electrically connected to the second strapping electrode 42 through the fourth via K4, and another portion is electrically connected to the first electrode 40 through the fifth via K5. The orthographic projection of the second electrode 60 on the substrate 1 overlaps with the orthographic projection of the third via K3 on the substrate 1; the orthographic projection of the first bridging electrode 61 on the substrate 1 overlaps with the orthographic projection of the fourth via K4 on the substrate 1, and overlaps with the orthographic projection of the fifth via K5 on the substrate 1. The second electrode 60 can be a pixel electrode;

[0058] In the embodiment of the present invention, the first electrode layer 4 includes: a first electrode 40, a first strapping electrode 41, and a second strapping electrode 42, and the second electrode layer 6 includes a second electrode 60 and a first bridging electrode 61; the second electrode 60 is electrically connected to the first electrode 21 through the first strapping electrode 41, and the first electrode 40 is electrically connected to the first signal line 22 through the first bridging electrode 61 and the second strapping electrode 42, so that the conductive structure between the first electrode 40 and the first signal line 22 at the location of the fourth via K4 is consistent with the conductive structure between the second electrode 60 and the first electrode 21, thereby effectively reducing light leakage at the location of the fourth via K4 when the first electrode 40 and the first signal line 22 are conductive. In this case, the light leakage at the via hole where the first electrode 40 is connected to the first signal line 22 and the light leakage at the via hole where the second electrode 60 is connected to the first electrode 21 are roughly the same; moreover, compared with the direct electrical connection between the second electrode 60 and the first electrode 21, the required via hole is deeper, and the second electrode 60 is prone to breakage. In the embodiment of the present invention, the second electrode 60 is electrically connected to the first electrode 21 through the first overlapping electrode 41, and a good overlap can be achieved through the first overlapping electrode 41, thereby improving the situation where the second electrode 60 is affected by the deep hole and breaks. Moreover, the thickness of the first overlapping electrode 41 is used to reduce the hole depth, thereby reducing the difficulty of exposing the film layer above the first overlapping electrode 41 and reducing the risk of residue in the hole.

[0059] In one possible implementation, see Figure 2 、 Figure 3A-3C As shown, the third via hole K3 is located at the center of the orthographic projection of the substrate 1 , and coincides with the center of the orthographic projection of the first via hole K1 on the substrate 1 .

[0060] In one possible implementation, see Figure 2 、 Figure 3A-3C As shown, the fourth via hole K4 is located at the center of the orthographic projection of the substrate 1 , and coincides with the center of the orthographic projection of the second via hole K2 on the substrate 1 .

[0061] In one possible implementation, see Figure 2 、 Figure 3A-3C As shown, the orthographic projection area of ​​the first bonding electrode 41 on the substrate 1 is equal to the orthographic projection area of ​​the second bonding electrode 42 on the substrate 1 .

[0062] In one possible implementation, see Figure 2 、 Figure 3A-3C As shown, the second electrode 60 includes: a second electrode body 601, and a second electrode connecting portion 602 connected to the second electrode body 601; the second electrode 60 is electrically connected to the first connecting electrode 41 through the second electrode connecting portion 602;

[0063] The second electrode overlapping portion 602 includes: a first sub-electrode portion P1 filled in the third via hole K3; the first overlapping electrode 41 includes: a first sub-lapping portion 411 located at the bottom of the first via hole K1, and a second sub-lapping portion 412 covering the side wall of the third via hole K3; the second insulating layer 5 also includes: a first filling portion 51 filled between the first sub-electrode portion P1 and the second sub-lapping portion 412.

[0064] In an embodiment of the present invention, the second insulating layer 5 also includes: a first filling portion 51 filled between the first sub-electrode portion P1 and the second sub-overlap portion 412, so that the third via hole K3 contains the first filling portion 51 and the first sub-electrode portion P1. The light reflected by the first electrode 21 will be affected by the slope formed by the first filling portion 51 in the hole and the first sub-electrode portion P1, and the light becomes divergent, so that the light leakage at the via hole where the second electrode 60 and the first electrode 21 are connected is significantly improved.

[0065] In one possible implementation, see Figure 2 、 Figure 3A-3C As shown, the first bridging electrode includes: a second sub-electrode portion P2 filled in the fourth via hole K4; the second bridging electrode 42 includes: a third sub-bridging portion 421 located at the bottom of the second via hole K2, and a fourth sub-bridging portion 422 covering the side wall of the second via hole K2;

[0066] The second insulating layer 5 further includes a second filling portion 52 filled between the second sub-electrode portion P2 and the fourth sub-bridge portion 422 .

[0067] In an embodiment of the present invention, the second insulating layer 5 also includes: a second filling portion 52 filled between the second sub-electrode portion P2 and the fourth sub-overlap portion 422, so that the fourth via hole K4 has the second filling portion 52 and the second sub-electrode portion P2. The light reflected by the first signal line 22 will be affected by the slope formed by the second filling portion 52 in the hole and the second sub-electrode portion P2, and the light becomes divergent, so that the light leakage at the via hole where the first electrode 40 and the first signal line 22 are connected is significantly improved.

[0068] In one possible implementation, see Figure 2 、 Figure 3A-3C As shown, the orthographic projection of the first bridging electrode 61 on the substrate 1 covers the orthographic projection of the fourth via K4 on the substrate 1. This ensures that the first bridging electrode 61 can be well connected to the first signal line 22 and the first electrode 40 through the fourth via K4 and the fifth via K5.

[0069] In one possible implementation, see Figure 2 、 Figure 3A-3CAs shown, the minimum spacing a1 between the first bridging electrode 61 and the second electrode 60 is greater than 3.0 μm. Because the second electrode layer 6 and the first electrode layer 4 are not directly aligned, the alignment margin between them is 1.3 μm. Furthermore, the second insulating layer 5 has a 1.7 μm slope at the fourth via K4. This can easily leave residue on the slope of the first bridging electrode 61, causing a short circuit between the first bridging electrode 61 and the second electrodes 60 on either side, resulting in a dark spot. Setting the minimum spacing a1 between the first bridging electrode 61 and the second electrode 60 to greater than 3.0 μm can prevent short circuits between the first bridging electrode 61 and the second electrode 60.

[0070] Specifically, the width of the first bridging electrode 61 in the second direction Y can range from 3.0μm to 8.0μm, which is 5.0um. Specifically, it can be 3.0μm, 4.0μm, 5.0μm, 6.0μm, 7.0μm, and 8.0μm. Specifically, the width of the first bridging electrode 61 in the second direction Y can be the same as the width of the fourth via hole K4 in the second direction Y, or the width of the first bridging electrode 61 in the second direction Y can be greater than the width of the fourth via hole K4 in the second direction Y, which can ensure that the fourth via hole K4 is fully covered and that there is a 1.0μm design deviation margin on both sides of the fourth via hole K4, thereby ensuring that the first bridging electrode 61 can be well overlapped with the first signal line 22 and the first electrode 40 through the fourth via hole K4.

[0071] While meeting the above design requirements, the width of the first bridging electrode 61 in the second direction Y can be as wide as possible to ensure proper overlap between the first bridging electrode 61, the first signal line 22, and the first electrode 40, thereby enhancing touch signal transmission. Therefore, the upper limit of the width of the first bridging electrode 61 in the second direction Y is determined by the spacing between the second electrodes 60, while the lower limit of the width of the first bridging electrode 61 in the second direction Y is determined by the minimum dimension (CD) of the fourth via K4 (and / or the fifth via K5). In actual production, a design margin of at least 0.8 μm per side between the first bridging electrode 61 and the fourth via K4 (and / or the fifth via K5) is required to ensure good overlap. The length of the first bridging electrode 61 in the first direction X is determined by the distance between the fourth via K4 and the fifth via K5. The outer edge of the first bridging electrode 61 only needs to overlap the outer edges of the fourth via K4 and the fifth via K5 to ensure good overlap.

[0072] In a possible implementation, the first direction X may be parallel to the direction of the pixel electrode rows, and the second direction Y may be parallel to the direction of the pixel electrode columns.

[0073] In one possible implementation, see Figure 3A-3CAs shown, the minimum distance a2 between the first bonding electrode 41 and the first electrode 40 is greater than 2.7 μm; the minimum distance a3 between the second bonding electrode 42 and the first electrode 40 is greater than 2.7 μm.

[0074] In the embodiment of the present invention, in order to ensure the overall design consistency of the first electrode layer 4, the first electrode layer 4 is evenly grooved within and between the first electrode 40 blocks, and there needs to be a gap of more than 2.7 μm between the edge of the groove and the first strap electrode 41 and the second strap electrode 42 (that is, the minimum spacing a2 between the first strap electrode 41 and the first electrode 40 is greater than 2.7 μm; the minimum spacing a3 between the second strap electrode 42 and the first electrode 40 is greater than 2.7 μm). This is because the presence or absence of a metal film layer in the film layer below the groove of the first electrode layer 4 causes a step difference near the groove. When the gap is less than 2.7 μm, it is very easy to cause a short circuit between the first electrode 40 and the first strap electrode 41 (the second strap electrode 42), thereby causing a short circuit between the first electrode layer 4 and the second electrode layer 6. The first electrode layer 4 and the second electrode layer 6 cannot form an electric field, resulting in an inability to drive the liquid crystal to rotate or to transmit the touch signal, resulting in abnormal display, poor dark spots or poor touch failure.

[0075] In one possible implementation, see Figure 2 、 Figure 3A-3C As shown, the array substrate includes: a color filter layer 33; and the first insulating layer 3 includes a color filter layer.

[0076] In one possible implementation, see Figure 2 、 Figure 3A-3C As shown, the array substrate also includes: a black matrix layer 32 located on the side of the color filter layer 33 facing the substrate 1; the first insulating layer 3 includes the black matrix layer 32; the black matrix layer 32 has a first black matrix via, and a second black matrix via; the first via K1 includes a first black matrix via, and the second via K2 includes a second black matrix via.

[0077] In one possible implementation, see Figure 2 、 Figure 3A-3C As shown, the array substrate further includes: a planar layer 34 located between the color filter layer 33 and the first electrode layer 4, and a first passivation layer 31 located between the black matrix layer 32 and the first metal layer 2; the first insulating layer 3 further includes: a planar layer 34, and a first passivation layer 31.

[0078] The second insulating layer 5 may include a second passivation layer.

[0079] In one possible implementation, see Figure 2 、 Figure 3A-3C As shown, the first electrode 40 may be a touch electrode, the second electrode 60 may be a pixel electrode, and the first metal layer 2 may be a source and drain electrode layer.

[0080] In one possible implementation, see Figure 2 As shown, the array substrate may include, in sequence, on one side of the substrate 1: a light-shielding layer 108, an active layer 7, a gate insulating layer 101, a gate layer 8, an interlayer dielectric layer 102, a first metal layer 2 (source and drain layer), a first passivation layer 31, a black matrix layer 32, a color filter layer 33, a flat layer 34, a first electrode layer 4 (touch electrode layer), a second insulating layer 5 (second passivation layer), a second electrode layer 6 (pixel electrode layer), and a first alignment film layer 103.

[0081] See also Figures 4A-4I FIG. 1 is a schematic diagram of a portion of film layers of an array substrate provided by the present invention, wherein: Figure 4A is a schematic diagram of a single film layer of the light-shielding layer. Figure 4B is a schematic diagram of a single film layer of the active layer. Figure 4C is a schematic diagram of a single film layer of the gate line layer. Figure 4D Schematic diagram of a single film layer of the interlayer dielectric layer. Figure 4E Schematic diagram of a single film layer of the source and drain layer. Figure 4F Schematic diagram of a flat single film layer. Figure 4G Schematic diagram of a single touch electrode layer. Figure 4H Schematic diagram of a single film layer of the second passivation layer. Figure 4I is a schematic diagram of a single film layer of a pixel electrode layer; Figure 4A As shown, the light shielding layer 108 can shield the channel region of the active layer 7 from light to prevent external light from affecting the characteristics of the transistor; Figure 4D As shown, the interlayer dielectric layer 102 may include a plurality of interlayer dielectric vias 102a to connect the first electrode 21 to the source region of the active layer 7 and the second electrode 23 to the drain region of the active layer 7; Figure 4E As shown, the first metal layer 2 includes: a first electrode 21, a first signal line 23, and a second signal line 24 (which can be a data line). The first signal line 23 can transmit a touch signal, and the second signal line 24 can transmit a pixel signal; Figure 4F As shown, the first insulating layer 3 (including the flat layer 34) may include a first via hole K1 and a second via hole K2, which are the connection channels between the upper first electrode layer 4 and the first metal layer 2; Figure 4G As shown, the first electrode layer 4 has two functions: one is to form a voltage difference with the second electrode layer 6 to drive the liquid crystal to rotate; the other is to use the first electrode 40 to block and connect with the first signal line 22 of the first metal layer 2 to transmit the touch signal; Figure 4H As shown, the second insulating layer 5 (second passivation layer) includes a third via K3, a fourth via K4, and a fifth via K5, which are overlapping channels between the second electrode layer 6 and the first electrode layer 4. The third via K3 is sleeved in the first via K1, and the fourth via K4 is sleeved in the second via K2; Figure 4I As shown, the second electrode layer 6 is a pixel electrode layer, and drives the liquid crystal to rotate together with the first electrode layer 4 .

[0082] The solution described in the present invention is suitable for curved vehicle-mounted display products, desktop display products (MNT) and head-mounted display products with lower specifications. With the update and iteration of exposure machines, this solution will be applicable to most product types that require the use of COA.

[0083] Based on the same inventive concept, an embodiment of the present invention further provides a display panel, including the array substrate provided by the embodiment of the present invention.

[0084] In one possible implementation, see Figure 2 As shown, the array substrate may include, in sequence, on one side of the substrate 1: a light-shielding layer 108, an active layer 7, a gate insulating layer 101, a gate layer 8, an interlayer dielectric layer 102, a first metal layer 2 (source and drain layer), a first passivation layer 31, a black matrix layer 32, a color filter layer 33, a flat layer 34, a first electrode layer 4 (touch electrode layer), a second insulating layer 34 (second passivation layer), a second electrode layer 6 (pixel electrode layer), and a first alignment film layer 103.

[0085] In one possible implementation, see Figure 2 As shown, the display panel further includes an opposing substrate, which may include an opposing substrate 106, an optical adhesive layer 105 located on the side of the opposing substrate 106 facing the array substrate, and a second alignment film layer 104 located on the side of the optical adhesive layer 105 facing the array substrate.

[0086] In one possible implementation, see Figure 2 As shown, the display panel further includes a liquid crystal layer 109 and a spacer 107 located between the array substrate and the opposite substrate.

[0087] Based on the same inventive concept, an embodiment of the present invention further provides a display device, including the display panel provided in the embodiment of the present invention. The implementation of the display device can refer to the embodiment of the display panel above, and the repeated parts will not be repeated.

[0088] In specific implementations, in the embodiments of the present disclosure, the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, or the like. Other essential components of the display device are well understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0089] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0090] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An array substrate, It is characterized in that include: substrate; A first metal layer, located on one side of the substrate, includes: a first electrode and a first signal line; A first insulating layer, located on a side of the first metal layer facing away from the substrate, having a first via hole and a second via hole; A first electrode layer, located on a side of the first insulating layer away from the first metal layer, includes: a plurality of first electrodes, a first bridging electrode, and a second bridging electrode; the first bridging electrode is electrically connected to the first electrode through the first via hole; the second bridging electrode is electrically connected to the first signal line through the second via hole; a second insulating layer, located on a side of the first electrode layer away from the first insulating layer, having a third via hole, a fourth via hole, and a fifth via hole; an orthographic projection of the third via hole on the substrate has an overlapping area with an orthographic projection of the first lap electrode on the substrate; an orthographic projection of the fourth via hole on the substrate has an overlapping area with an orthographic projection of the second lap electrode on the substrate; The second electrode layer is located on the side of the first electrode layer away from the first metal layer, and includes: multiple second electrodes and a first bridging electrode; the second electrode is electrically connected to the first bridging electrode through the third via, part of the first bridging electrode is electrically connected to the second bridging electrode through the fourth via, and the other part is electrically connected to the first electrode through the fifth via.

2. The array substrate according to claim 1, It is characterized in that The orthographic projection center of the third via hole on the substrate coincides with the orthographic projection center of the first via hole on the substrate.

3. The array substrate according to claim 1 or 2, It is characterized in that The orthographic projection center of the fourth via hole on the substrate coincides with the orthographic projection center of the second via hole on the substrate.

4. The array substrate according to claim 3, It is characterized in that The orthographic projection area of ​​the first bonding electrode on the substrate is equal to the orthographic projection area of ​​the second bonding electrode on the substrate.

5. The array substrate according to claim 1, It is characterized in that The second electrode comprises: a second electrode body, and a second electrode lap portion connected to the second electrode body; the second electrode is electrically connected to the first lap electrode via the second electrode lap portion; The second electrode overlapping portion includes: a first sub-electrode portion filled in the third via hole; the first overlapping electrode includes: a first sub-overlapping portion located at the bottom of the first via hole, and a second sub-overlapping portion covering the side wall of the third via hole; The second insulating layer further includes: a first filling portion filled between the first sub-electrode portion and the second sub-lapping portion.

6. The array substrate according to claim 5, It is characterized in that The first bridging electrode includes: a second sub-electrode portion filled in the fourth via hole; the second bridging electrode includes: a third sub-bridging portion located at the bottom of the second via hole, and a fourth sub-bridging portion covering the side wall of the second via hole; The second insulating layer further includes: a second filling portion filled between the second sub-electrode portion and the fourth sub-lapping portion.

7. The array substrate according to claim 1, It is characterized in that The orthographic projection of the first bridging electrode on the substrate covers the orthographic projection of the fourth via hole on the substrate.

8. The array substrate according to claim 7, It is characterized in that The minimum distance between the first bridging electrode and the second electrode is greater than 3.0 μm.

9. The array substrate according to claim 1, It is characterized in that The minimum distance between the first bonding electrode and the first electrode is greater than 2.7 μm; the minimum distance between the second bonding electrode and the first electrode is greater than 2.7 μm.

10. The array substrate according to claim 1, It is characterized in that The array substrate includes: a color filter layer; and the first insulating layer includes the color filter layer.

11. The array substrate according to claim 10, It is characterized in that The array substrate further comprises: a black matrix layer located on a side of the color filter layer facing the substrate; the first insulating layer comprises the black matrix layer; The black matrix layer has a first black matrix via hole and a second black matrix via hole; the first via hole includes the first black matrix via hole, and the second via hole includes the second black matrix via hole.

12. The array substrate according to claim 10, It is characterized in that The array substrate further includes: a planar layer located between the color filter layer and the first electrode layer, and a first passivation layer located between the black matrix layer and the first metal layer; The first insulating layer further includes: the planarization layer, and the first passivation layer.

13. The array substrate according to claim 1, It is characterized in that The first electrode is a touch electrode, and the second electrode is a pixel electrode.

14. A display panel, It is characterized in that It comprises the array substrate as described in any one of claims 1 to 13.

15. A display device, It is characterized in that Comprising the display panel as claimed in claim 14.

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