Low power small area high psr all-mos voltage reference circuit and apparatus

Abstract

The application relates to a low-power-consumption small-area high-PSR full-MOS voltage reference circuit and equipment, which adopts a depletion-mode MOS transistor and an enhancement-mode transistor to design a reference current generation circuit and a core reference circuit on a circuit process, so that a tiny reference current can be generated under a smaller circuit area, a full-MOS transistor structure design is adopted on a core circuit structure, the area cost of the circuit is greatly saved, a power supply voltage preprocessing circuit is designed to provide power supply voltage preprocessing, the PSR of the full-MOS voltage reference circuit is effectively improved, the full-MOS voltage reference circuit has the characteristics of low power consumption, small area and high PSR, and the purpose of designing a low-power-consumption small-area high-PSR voltage reference circuit is achieved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of electronic circuit design, and relates to a full-MOS voltage reference circuit with low power consumption, small area and high PSR and an electronic device. BACKGROUND

[0002] The voltage reference source is a kind of voltage reference source obtained through linear superposition of different temperature characteristics between devices, and the reference voltage generated thereby can be maintained as stable and accurate as possible in the presence of factors such as process deviation, working temperature and working voltage fluctuation, so as to ensure the circuit reliability and accuracy of the electronic device to which the voltage reference source is applied.

[0003] Many circuits of electronic devices need to be compared with a fixed reference voltage, at present, most voltage reference sources adopt the structure of a bandgap reference to realize this function, although the circuit stability of the traditional bandgap voltage reference source is generally good, and the reference voltage output thereby is less affected by process, power voltage and temperature change. However, in order to realize the design of low power consumption, a very large resistance is often needed, which undoubtedly increases the circuit area and cost, is not conducive to integration, and the PSR (Power Supply Rejection Ratio) of the traditional bandgap voltage reference source is not high, and is easily affected by power voltage fluctuation. Therefore, how to realize the design of a voltage reference circuit with low power consumption, small area and high PSR has become a technical problem to be solved. SUMMARY

[0004] In view of the problems in the prior art, the application provides a full-MOS voltage reference circuit with low power consumption, small area and high PSR, and an electronic device, which can realize the design of a voltage reference circuit with low power consumption, small area and high PSR.

[0005] In order to achieve the above-mentioned purpose, the embodiments of the application adopt the following technical solutions:

[0006] On the one hand, a full-MOS voltage reference circuit with low power consumption, small area and high PSR and an electronic device are provided, which comprise an inverter, a reference current generation circuit, a current biasing circuit, a power voltage preprocessing circuit, a core reference circuit, a power switch circuit and a filter circuit.

[0007] The enable control end of the reference current generating circuit, the power supply switch circuit, the power supply voltage preprocessing circuit and the core reference circuit is used for accessing the enable signal, the input end of the inverter is used for accessing the enable signal, the output end of the inverter is connected with the auxiliary enable control end of the reference current generating circuit and the power supply switch circuit respectively, the reference current generating circuit is connected with the current bias circuit, the current bias circuit is connected with the core reference circuit and the power supply voltage preprocessing circuit respectively, the power supply voltage preprocessing circuit is connected with the power supply switch circuit and the core reference circuit respectively, and the core reference circuit is connected with the filter circuit.

[0008] The reference current generating circuit and the core reference circuit are circuits composed of depletion mode transistors and enhancement mode transistors, the current bias circuit, the power supply voltage preprocessing circuit and the power supply switch circuit are circuits composed of enhancement mode transistors, the reference current generating circuit is used for generating a reference current, the current bias circuit is used for copying the reference current to the core reference circuit and the power supply voltage preprocessing circuit respectively, the power supply voltage preprocessing circuit is used for preprocessing the power supply voltage to pull up the PSR of the full-MOS voltage reference circuit, the power supply switch circuit is used for transmitting the preprocessed power supply voltage into the core reference circuit, the core reference circuit is used for generating a reference voltage, and the filter circuit is used for filtering the reference voltage and then outputting.

[0009] In addition, the application also provides an electronic device loaded with the low-power-consumption small-area high-PSR full-MOS voltage reference circuit.

[0010] One of the above technical solutions has the following advantages and beneficial effects:

[0011] The low-power-consumption small-area high-PSR full-MOS voltage reference circuit and the device have the following advantages and beneficial effects: the depletion mode MOS transistors and the enhancement mode transistors are used to design the reference current generating circuit and the core reference circuit on the circuit process, so that the reference current generating circuit and the core reference circuit can generate a small reference current in a small circuit area; the full-MOS transistor structure is used in the core circuit structure, so that the area cost of the circuit is greatly saved; the power supply voltage preprocessing circuit is designed to provide power supply voltage preprocessing, so that the PSR of the full-MOS voltage reference circuit is effectively improved, and the full-MOS voltage reference circuit has the characteristics of low power consumption, small area and high PSR, and finally the purpose of designing the low-power-consumption small-area high-PSR voltage reference circuit is achieved. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0013] Figure 1 Circuit structure diagram of a conventional bandgap voltage reference source;

[0014] Figure 2 Module structure diagram of a full-MOS voltage reference circuit with low power consumption, small area and high PSR in one embodiment;

[0015] Figure 3 Module structure diagram of a full-MOS voltage reference circuit with low power consumption, small area and high PSR in another embodiment;

[0016] Figure 4 Specific circuit structure diagram of a full-MOS voltage reference circuit with low power consumption, small area and high PSR in one embodiment. DETAILED DESCRIPTION

[0017] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not intended to limit the present application. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used in the specification of the present application are only for the purpose of describing the specific embodiments and are not intended to limit the present application.

[0018] It should be noted that the term "embodiment" mentioned herein means that the specific features, structures or characteristics described in connection with the embodiment can be included in at least one embodiment of the present application. The phrase is shown at various places in the specification does not necessarily refer to the same embodiment, nor is it independent or alternative to other embodiments. Those skilled in the art can understand that the embodiments described herein can be combined with other embodiments. The term "and / or" used in the specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0019] The embodiments of the present application will be described in detail below with reference to the accompanying drawings of the embodiments of the present application.

[0020] The circuit of a conventional bandgap voltage reference source is as follows Figure 1As shown, it mainly includes operational amplifier OP1, transistor Q1, transistor Q2, transistor Q3, resistor R01, resistor R02, transistor M01, transistor M02 and transistor M03, and the reference voltage output by the bandgap voltage reference source is VREF. Among them, transistor Q1, transistor Q2 and transistor Q3 are key elements in the circuit, which usually work at different current densities, and use the base-emitter voltage (VBE) of the transistor to generate a bandgap reference voltage. Among them, transistor Q1 and transistor Q2 constitute a basic current mirror structure, which is used to generate a positive temperature coefficient voltage, and the positive temperature coefficient voltage generates a positive temperature coefficient current on resistor R01, which is copied to the output stage through transistor M02 above, thereby generating a positive temperature voltage on resistor R02, and generating a negative temperature voltage on transistor Q3. By reasonably selecting the resistance values of resistor R01 and resistor R02, the size and temperature coefficient of the output reference voltage can be adjusted.

[0021] The operational amplifier OP1 plays a role of clamping in the circuit through feedback control, so that the positive and negative input voltages are approximately equal. Its input end is connected to the emitter of transistor Q1 and one end of resistor R01, and its output end is connected to the gate of transistor M01, transistor M02 and transistor M03. Through the negative feedback mechanism, the operational amplifier OP1 ensures that the base voltages of transistor Q1 and transistor Q2 are equal, thereby stabilizing the current and voltage relationship in the circuit and improving the accuracy and stability of the reference voltage. Transistors M01, M02 and M03 constitute a current mirror structure for copying and mirroring the current in the circuit. The currents of transistor M01 and transistor M02 are equal, and the current of transistor M03 is in a certain proportional relationship with the currents of transistor M01 and transistor M02. Through this current mirror structure, the voltage signal output by the operational amplifier OP1 can be converted into a stable current signal, and then a stable voltage drop is generated on the resistor to realize the output of the reference voltage. VREF is the output end of the entire circuit, which outputs the reference voltage. This reference voltage has relatively stable characteristics and is not greatly affected by factors such as power supply voltage and temperature, and can be used as a reference voltage for other circuit modules, such as in analog-to-digital converters (ADCs), digital-to-analog converters (DACs) and other circuits, to provide accurate voltage references for them and ensure the normal operation and performance of the circuit.

[0022] The PSR is used to measure the anti-interference ability of the voltage reference source to the power supply voltage change, which is defined as the ratio of the change of the input voltage to the change of the output reference voltage, and the unit is decibel (dB). The higher the PSR is, the less the voltage reference source is affected by the power supply voltage fluctuation, and the output voltage is more stable; on the contrary, the lower the PSR is, the more the power supply voltage change is transmitted to the output end, resulting in a larger fluctuation of the output reference voltage. However, the circuit of the traditional bandgap voltage reference source is difficult to achieve low power consumption, small area and high PSR, therefore, a new circuit design is proposed in this specification to achieve this purpose.

[0023] In one embodiment, as shown in Figure 2 A low-power small-area high-PSR all-MOS voltage reference circuit is provided, which includes an inverter INV, a reference current generating circuit 12, a current biasing circuit 14, a power supply voltage preprocessing circuit 16, a core reference circuit 18, a power supply switching circuit 20 and a filtering circuit 22. The enable control terminals of the reference current generating circuit 12, the power supply switching circuit 20, the power supply voltage preprocessing circuit 16 and the core reference circuit 18 are used to access the enable signal. The input terminal of the inverter INV is used to access the enable signal, and the output terminal of the inverter INV is connected to the auxiliary enable control terminals of the reference current generating circuit 12 and the power supply switching circuit 20, respectively. The reference current generating circuit 12 is connected to the current biasing circuit 14, the current biasing circuit 14 is connected to the core reference circuit 18 and the power supply voltage preprocessing circuit 16, respectively, the power supply voltage preprocessing circuit 16 is connected to the power supply switching circuit 20 and the core reference circuit 18, respectively, and the core reference circuit 18 is connected to the filtering circuit 22.

[0024] The reference current generating circuit 12 and the core reference circuit 18 are both circuits composed of depletion mode transistors and enhancement mode transistors, the current biasing circuit 14, the power supply voltage preprocessing circuit 16 and the power supply switching circuit 20 are all circuits composed of enhancement mode transistors, the reference current generating circuit 12 is used to generate a reference current, the current biasing circuit 14 is used to copy the reference current to the core reference circuit 18 and the power supply voltage preprocessing circuit 16, respectively, the power supply voltage preprocessing circuit 16 is used to preprocess the power supply voltage to pull up the PSR of the all-MOS voltage reference circuit, the power supply switching circuit 20 is used to transmit the preprocessed power supply voltage into the core reference circuit 18, the core reference circuit 18 is used to generate a reference voltage, and the filtering circuit 22 is used to output the reference voltage after filtering.

[0025] It can be understood that the enable signal, i.e. EN, is one of the input signals of the full-MOS voltage reference circuit, and is used to realize the enable control of the circuit. The secondary enable control end of the power switch circuit 20 is another enable control end relative to the enable control end (i.e. the terminal connected to the enable signal EN) of the power switch circuit 20, which is controlled by the enable signal ENB output by the inverter INV, and together realizes the on-off control of the power switch circuit 20. The circuit state of the reference current generating circuit 12, the power switch circuit 20 and the power voltage preprocessing circuit 16 is controlled by the enable signal EN and the enable signal ENB output by the inverter INV respectively, so as to control whether the full-MOS voltage reference circuit works or not.

[0026] After the reference current is generated by the reference current generating circuit 12, the reference current is transmitted to the core reference circuit 18 and the power voltage preprocessing circuit 16 through the current biasing circuit 14. In the power voltage preprocessing circuit 16, the power voltage (VDD) is preprocessed, for example, after the power voltage is divided by the power voltage preprocessing circuit 16, the power voltage is transformed and subjected to a voltage dividing adjustment in the process of transforming the power voltage to the core reference circuit, so as to adjust the ratio of the change of the power voltage to the change of the output reference voltage, improve the PSR of the full-MOS voltage reference circuit, and then transfer the preprocessed power voltage to the core reference circuit 18. The core reference circuit 18 generates a reference voltage according to the input reference current and the preprocessed power voltage. The reference voltage is finally filtered by the filtering circuit 22 and output as an accurate and stable reference voltage.

[0027] It should be noted that those skilled in the art can use depletion mode transistors and enhancement mode transistors to design various specific circuit structures according to the functions of the above-mentioned module circuits, combined with the inverter INV, resistors and capacitors, according to the circuit layout design rules in the art, as long as the functions of the above-mentioned module circuits can be realized based on the above-mentioned design concept.

[0028] The above-mentioned low-power-consumption, small-area and high-PSR full-MOS voltage reference circuit can generate a small reference current in a small circuit area by using depletion mode MOS transistors and enhancement mode transistors to design the reference current generating circuit 12 and the core reference circuit 18, and can greatly save the area cost of the circuit by using the structure of full-MOS transistors in the core circuit structure, and can effectively improve the PSR of the full-MOS voltage reference circuit by designing the power voltage preprocessing circuit 16 to provide power voltage preprocessing, so as to have the characteristics of low power consumption, small area and high PSR, and finally realize the purpose of low-power-consumption, small-area and high-PSR voltage reference circuit design.

[0029] In one embodiment, as Figure 3As shown, the reference current generating circuit 12 comprises a mirror unit, a switch unit and a proportional unit. The input terminal of the mirror unit is used to access the power supply voltage, the output terminal of the mirror unit is connected to the input terminal of the proportional unit through the switch unit, and the output terminal of the proportional unit is grounded. The mirror unit is used to generate a reference current, the switch unit is used to control the on-off between the mirror unit and the proportional unit, and the proportional unit is used for current proportional control.

[0030] It can be understood that the mirror unit is a main circuit unit for generating a reference current, which is designed by using an enhancement transistor, the proportional unit is a circuit unit for generating a small reference current of a required size in cooperation with the mirror unit, which is designed by using a depletion transistor, and the switch unit is a circuit unit for controlling whether the reference current generating circuit 12 works under the control of an enable signal, which can be designed by using a pair of enhancement PMOS transistors and enhancement NMOS transistors. The mirror unit and the proportional unit can adopt various mirror circuit structures in the prior art. The proportional unit can make the current in its series structure in a certain proportional relationship with the current of other branches by accurately controlling the size and biasing condition of the depletion transistor, so as to meet the generation requirement of the reference current of a required size. Therefore, the specific number of the depletion transistors in series in the proportional unit can be selected according to the generation requirement of the reference current.

[0031] Through the structural design of the mirror unit, the switch unit and the proportional unit, the reference current required in a specific application scenario can be accurately controlled in a small circuit area.

[0032] In one embodiment, as shown in Figure 4 The proportional unit comprises transistors M1, M2, M3, M4, M5, M6, M7 and M8 with their gates grounded and connected in series, and the sources of the transistors M1 to M8 are grounded. The switch unit comprises transistors M9 and M10, the drain of the transistor M9 and the source of the transistor M10 are both connected to the drain of the transistor M8, the source of the transistor M10 is grounded, the gate of the transistor M9 is used to access an enable signal, the source of the transistor M9 is used to access a power supply voltage, and the gate of the transistor M10 is connected to the output terminal of the inverter INV.

[0033] The mirror unit includes transistors M11, M12 and resistor R1. One end of resistor R1 is connected to the source of transistor M9, the drain of transistor M10 and the gate of transistor M11 respectively, the source of transistor M11 is used to access the power supply voltage, the drain of transistor M11 is connected to the gate of transistor M12 and the other end of resistor R1 respectively, the gate of transistor M11 and the gate of transistor M12 are connected to current bias circuit 14 respectively, the drain of transistor M12 is connected to the source of transistor M11, and the source of transistor M12 is used to access the power supply voltage. Transistors M1 to M8 are all depletion-mode NMOS transistors, transistors M9, M11 and M12 are all enhancement-mode PMOS transistors, and transistor M10 is an enhancement-mode NMOS transistor.

[0034] It can be understood that in the present embodiment, a specific reference current generating circuit 12 structure as shown in Figure 4 is provided, in which depletion-mode MOS tubes are used and a full-MOS tube design is adopted, so that a large resistor is no longer needed to generate the required tiny reference current with low power consumption.

[0035] In the switch unit, for example, when the enable signal EN is high and the enable signal ENB is low, transistor M9 is turned on, transistor M10 is turned off, and the power supply voltage VDD is accessed, so as to realize the opening of the power supply; on the contrary, when the enable signal EN is low and the enable signal ENB is high, transistor M9 is turned off, transistor M10 is turned on, and the power supply voltage VDD is disconnected, so as to realize the closing of the power supply. By controlling the opening and closing of the power supply through such a circuit, the power supply of the circuit module can be turned off when it is not needed to work, so as to reduce the overall power consumption of the system.

[0036] In one embodiment, as shown in Figure 4 , the current bias circuit 14 includes transistors M13, M14, M15, M16, M17, M18, M19, M20, M21, M22 and resistor R2. The sources of transistors M13, M19 and M21 are used to access the power supply voltage, the gates of transistors M13, M19 and M21 are connected to the reference current generating circuit 12, the gates of transistors M14, M20 and M22 are connected to the reference current generating circuit 12, the source of transistor M14 is connected to the drain of transistor M13 and used to access the power supply voltage, the source of transistor M20 is connected to the drain of transistor M19 and used to access the power supply voltage, the drain of transistor M20 is connected to the core reference circuit 18, the source of transistor M22 is connected to the drain of transistor M21 and used to access the power supply voltage, and the drain of transistor M22 is connected to the power supply voltage preprocessing circuit 16.

[0037] One end of the resistor R2 is connected to the drain of the transistor M14, the gate of the transistor M15 and the gate of the transistor M17 respectively, the other end of the resistor R2 is connected to the drain of the transistor M15, the gate of the transistor M16 and the gate of the transistor M18 respectively, the source of the transistor M15 is connected to the drain of the transistor M16 and grounded, the source of the transistor M17 is connected to the drain of the transistor M18 and grounded, the source of the transistor M16 and the source of the transistor M18 are both grounded, and the drain of the transistor M17 is connected to the core reference circuit 18. The transistors M13 to M14 and the transistors M19 to M22 are all enhancement-mode PMOS transistors, and the transistors M15 to M18 are all enhancement-mode NMOS transistors.

[0038] It can be understood that, in the embodiment, a specific current bias circuit 14 structure is provided as shown in Figure 4 , in which a full-MOS design is adopted, and a large resistor is no longer needed to achieve low-power consumption, accurate copying and transmission of the reference current, and the occupied circuit area is greatly reduced.

[0039] In one embodiment, as shown in Figure 4 , the power supply voltage preprocessing circuit 16 includes the transistors M23, M24, M25, M26 and M27. The transistors M23 and M24 are enhancement-mode PMOS transistors, and the transistors M25 to M27 are all enhancement-mode NMOS transistors. The source of the transistor M23 is connected to the gate of the transistor M27 and the drain of the transistor M22 respectively, the source of the transistor M23 is used to access the power supply voltage, the source of the transistor M24 is connected to the drain of the transistor M23 and used to access the power supply voltage, the gate of the transistor M23 is connected to the drain of the transistor M26, the source of the transistor M26 is grounded, and the gate of the transistor M26 is used to access the enable signal. The drain of the transistor M24 is grounded, the gate of the transistor M24 is connected to the drain of the transistor M25 and the core reference circuit 18 respectively, the source of the transistor M25 is grounded, the gate of the transistor M25 is used to access the enable signal, the drain of the transistor M27 is connected to the power supply switch circuit 20, and the source of the transistor M27 is connected to the core reference circuit 18 and grounded.

[0040] It can be understood that, in the embodiment, a specific current bias circuit 14 structure is provided as shown in Figure 4A specific power supply voltage preprocessing circuit 16 structure is shown in FIG. 1, in which a full-MOS design is adopted to efficiently provide the required power supply voltage preprocessing and greatly reduce the circuit area occupied. In this structure, the power supply voltage is divided by transistors M21, M22, M23 and M24, and is output from the source of transistor M23. The voltage at the gate of transistor M27 is reduced by the gate-source voltage Vgs of transistor M27, and is output from the source of transistor M27 to supply power to transistor M31. The power supply is converted to the core reference circuit 18, and the process of dividing the voltage is performed to adjust the ratio of the change in the power supply voltage to the change in the output reference voltage, thereby improving the PSR of the full-MOS voltage reference circuit.

[0041] In one embodiment, as shown in FIG. 2, the power switch circuit 20 includes an enhanced PMOS transistor M28 and an enhanced NMOS transistor M29. The source of transistor M28 is connected to the power supply voltage, the gate of transistor M28 is connected to the enable signal, the drain of transistor M28 is connected to the drain of transistor M27, the drain of transistor M29 is connected to the power supply voltage, the gate of transistor M29 is connected to the output of the inverter INV, and the source of transistor M29 is connected to the drain of transistor M27 and to ground. Figure 4

[0042] It can be understood that in this embodiment, the specific circuit structure of the power switch circuit 20 can adopt the same circuit structure as the switching unit, thereby effectively implementing the on-off control between the core reference circuit 18 and the power supply voltage, reducing the complexity of the circuit design through circuit structure reuse, and reducing the circuit area occupied by the full-MOS design.

[0043] In one embodiment, as shown in FIG. 3, the core reference circuit 18 includes transistors M30, M31 and M32, which are all enhanced NMOS transistors. The gate of transistor M30 is connected to the gate of transistor M31, the drain of transistor M32 and the drain of transistor M30, respectively. The drain of transistor M30 is connected to the drain of transistor M20, and the source of transistor M30 is connected to ground. The drain of transistor M31 is connected to the source of transistor M27, the source of transistor M31 is connected to the gate of transistor M24, the filter circuit 22 and the drain of transistor M17, respectively, and is connected to ground. The gate of transistor M32 is connected to the enable signal, and the source of transistor M32 is connected to ground. Figure 4

[0044] It can be understood that in this embodiment, a specific core reference circuit 18 structure is provided as shown in FIG. 4, in which a full-MOS design is adopted to accurately output the reference voltage before filtering and greatly reduce the circuit area occupied, supporting low-power operation. Figure 4 It can be understood that in this embodiment, a specific core reference circuit 18 structure is provided as shown in FIG. 4, in which a full-MOS design is adopted to accurately output the reference voltage before filtering and greatly reduce the circuit area occupied, supporting low-power operation. ​

[0045] In one embodiment, as shown in Figure 4 The filter circuit 22 includes a resistor R3 and a capacitor C1. One end of the resistor R3 is used to output a filtered reference voltage (VREF), the other end of the resistor R3 is connected to one end of the capacitor C1 and the source of the transistor M31 respectively, and the other end of the capacitor C1 is grounded.

[0046] It can be understood that in the present embodiment, a specific filter circuit 22 structure as shown in Figure 4 is provided, in which the simplest filter design is adopted, and the spurs in the reference voltage can be accurately filtered out to achieve stable and accurate reference voltage output.

[0047] In one embodiment, an electronic device is also provided, which is equipped with the low-power small-area high-PSR all-MOS voltage reference circuit described above.

[0048] It can be understood that the electronic device in the present embodiment can be, but is not limited to, a car sensor (such as a sensor for measuring parameters such as vehicle speed, tire pressure, and oil temperature), a vehicle-mounted electronic device (such as a navigation system, a vehicle-mounted entertainment system, and the like), a smart phone, a smart wearable device (such as a smart watch, a bracelet, and the like), a smart meter (such as a smart electricity meter, a water meter, and a gas meter, and the like), and a portable medical instrument (such as a portable blood glucose meter, a sphygmomanometer, and the like). The low-power small-area high-PSR all-MOS voltage reference circuit described above can be used in these electronic devices to improve the accurate and stable reference voltage source, thereby ensuring the stable operation, accurate measurement, and control of the device. In these electronic devices, the original reference circuit module with relatively large circuit area can be replaced by the low-power small-area high-PSR all-MOS voltage reference circuit described above, so that a higher performance reference voltage source can be obtained.

[0049] The electronic device described above can effectively save the circuit area of the device, reduce the power consumption of the device, and improve the stability of the reference voltage of the device by applying the low-power small-area high-PSR all-MOS voltage reference circuit described above.

[0050] It can be understood that the explanation and description of the low-power small-area high-PSR all-MOS voltage reference circuit in the electronic device described above can be understood in the same way by referring to the corresponding explanation and description of each embodiment of the low-power small-area high-PSR all-MOS voltage reference circuit described above, and will not be repeated here.

[0051] The technical features of the above embodiments can be combined in any way. To make the description concise, not all possible combinations of the technical features in the above embodiments are described, but as long as the combinations of the technical features do not exist, they should be considered as the scope of the present disclosure.

[0052] The above embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but cannot be understood as the limitation of the protection scope of the present application. It should be noted that, for ordinary skilled in the art, several modifications and improvements can be made without departing from the concept of the present application, and all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A low power small area high PSR all-MOS voltage reference circuit, characterized by, The all-MOS voltage reference circuit comprises an inverter, a reference current generating circuit, a current biasing circuit, a power supply voltage preprocessing circuit, a core reference circuit, a power supply switch circuit and a filter circuit. The enable control terminals of the reference current generating circuit, the power supply switch circuit, the power supply voltage preprocessing circuit and the core reference circuit are used for accessing an enable signal, the input terminal of the inverter is used for accessing the enable signal, the output terminal of the inverter is connected to the auxiliary enable control terminals of the reference current generating circuit and the power supply switch circuit respectively, the reference current generating circuit is connected to the current biasing circuit, the current biasing circuit is connected to the core reference circuit and the power supply voltage preprocessing circuit respectively, the power supply voltage preprocessing circuit is connected to the power supply switch circuit and the core reference circuit respectively, and the core reference circuit is connected to the filter circuit. The reference current generating circuit and the core reference circuit are circuits composed of depletion mode transistors and enhancement mode transistors, the current biasing circuit, the power supply voltage preprocessing circuit and the power supply switch circuit are circuits composed of enhancement mode transistors, the reference current generating circuit is used for generating a reference current, the current biasing circuit is used for copying the reference current to the core reference circuit and the power supply voltage preprocessing circuit respectively, the power supply voltage preprocessing circuit is used for preprocessing a power supply voltage to pull up the PSR of the all-MOS voltage reference circuit, the power supply switch circuit is used for transmitting the preprocessed power supply voltage into the core reference circuit, the core reference circuit is used for generating a reference voltage, and the filter circuit is used for filtering and outputting the reference voltage.

2. The low power small area high PSR all-MOS voltage reference circuit according to claim 1, wherein, The reference current generating circuit comprises a mirror unit, a switch unit and a proportional unit, the input terminal of the mirror unit is used for accessing a power supply voltage, the output terminal of the mirror unit is connected to the input terminal of the proportional unit through the switch unit, and the output terminal of the proportional unit is grounded. The mirror unit is used for generating a reference current, the switch unit is used for controlling the on-off between the mirror unit and the proportional unit, and the proportional unit is used for current proportional control.

3. The low power small area high PSR all-MOS voltage reference circuit of claim 2, wherein, The proportional unit comprises transistors M1, M2, M3, M4, M5, M6, M7 and M8 which are connected in series and whose gates are grounded, and the sources of the transistors M1 to M8 are grounded respectively. The switch unit comprises transistors M9 and M10, the drain of the transistor M9 and the source of the transistor M10 are both connected to the drain of the transistor M8, the source of the transistor M10 is grounded, the gate of the transistor M9 is used for accessing the enable signal, the source of the transistor M9 is used for accessing a power supply voltage, and the gate of the transistor M10 is connected to the output terminal of the inverter. The mirror unit comprises a transistor M11, a transistor M12 and a resistor R1, one end of the resistor R1 is connected to the source of the transistor M9, the drain of the transistor M10 and the gate of the transistor M11 respectively, the source of the transistor M11 is used to access a power supply voltage, the drain of the transistor M11 is connected to the gate of the transistor M12 and the other end of the resistor R1 respectively, the gate of the transistor M11 and the gate of the transistor M12 are connected to the current bias circuit respectively, the drain of the transistor M12 is connected to the source of the transistor M11, and the source of the transistor M12 is used to access a power supply voltage; The transistors M1 to M8 are all depletion-mode NMOS transistors, the transistors M9, M11 and M12 are all enhancement-mode PMOS transistors, and the transistor M10 is an enhancement-mode NMOS transistor.

4. The low power small area high PSR all-MOS voltage reference circuit according to any one of claims 1 to 3, characterized in that, The current bias circuit comprises a transistor M13, a transistor M14, a transistor M15, a transistor M16, a transistor M17, a transistor M18, a transistor M19, a transistor M20, a transistor M21, a transistor M22 and a resistor R2; The sources of the transistors M13, M19 and M21 are all used to access a power supply voltage, the gates of the transistors M13, M19 and M21 are all connected to the reference current generating circuit, the gates of the transistors M14, M20 and M22 are all connected to the reference current generating circuit, the source of the transistor M14 is connected to the drain of the transistor M13 and used to access a power supply voltage, the source of the transistor M20 is connected to the drain of the transistor M19 and used to access a power supply voltage, the drain of the transistor M20 is connected to the core reference circuit, the source of the transistor M22 is connected to the drain of the transistor M21 and used to access a power supply voltage, and the drain of the transistor M22 is connected to the power supply voltage preprocessing circuit; One end of the resistor R2 is connected to the drain of the transistor M14, the gate of the transistor M15 and the gate of the transistor M17 respectively, the other end of the resistor R2 is connected to the drain of the transistor M15, the gate of the transistor M16 and the gate of the transistor M18 respectively, the source of the transistor M15 is connected to the drain of the transistor M16 and grounded, the source of the transistor M17 is connected to the drain of the transistor M18 and grounded, the sources of the transistors M16 and M18 are both grounded, and the drain of the transistor M17 is connected to the core reference circuit; The transistors M13 to M14 and the transistors M19 to M22 are all enhancement-mode PMOS transistors, and the transistors M15 to M18 are all enhancement-mode NMOS transistors.

5. The low power small area high PSR all-MOS voltage reference circuit of claim 4, wherein, The power supply voltage preprocessing circuit comprises transistors M23, M24, M25, M26 and M27, the transistors M23 and M24 are enhancement mode PMOS transistors, and the transistors M25 to M27 are enhancement mode NMOS transistors; The source of the transistor M23 is connected to the gate of the transistor M27 and the drain of the transistor M22, and is used to access a power supply voltage; the source of the transistor M24 is connected to the drain of the transistor M23 and is used to access the power supply voltage; the gate of the transistor M23 is connected to the drain of the transistor M26; the source of the transistor M26 is grounded; and the gate of the transistor M26 is used to access the enable signal; The drain of the transistor M24 is grounded; the gate of the transistor M24 is connected to the drain of the transistor M25 and the core reference circuit; the source of the transistor M25 is grounded; the gate of the transistor M25 is used to access the enable signal; the drain of the transistor M27 is connected to the power switch circuit; and the source of the transistor M27 is connected to the core reference circuit and grounded.

6. The low power small area high PSR all-MOS voltage reference circuit according to claim 5, wherein, The power switch circuit comprises an enhancement mode PMOS transistor M28 and an enhancement mode NMOS transistor M29; the source of the transistor M28 is used to access a power supply voltage; the gate of the transistor M28 is used to access the enable signal; the drain of the transistor M28 is connected to the drain of the transistor M27; the drain of the transistor M29 is used to access a power supply voltage; the gate of the transistor M29 is connected to the output of the inverter; and the source of the transistor M29 is connected to the drain of the transistor M27 and grounded.

7. The low power small area high PSR all-MOS voltage reference circuit according to claim 5, wherein, The core reference circuit comprises transistors M30, M31 and M32, which are all enhancement mode NMOS transistors; the gate of the transistor M30 is connected to the gate of the transistor M31, the drain of the transistor M32 and the drain of the transistor M30; the drain of the transistor M30 is connected to the drain of the transistor M20; and the source of the transistor M30 is grounded; The drain of the transistor M31 is connected to the source of the transistor M27; the source of the transistor M31 is connected to the gate of the transistor M24, the filter circuit, the drain of the transistor M17 and grounded; the gate of the transistor M32 is used to access the enable signal; and the source of the transistor M32 is grounded.

8. The low power small area high PSR all-MOS voltage reference circuit according to claim 7, wherein, The filter circuit comprises a resistor R3 and a capacitor C1; one end of the resistor R3 is used to output a filtered reference voltage; the other end of the resistor R3 is connected to one end of the capacitor C1 and the source of the transistor M31; and the other end of the capacitor C1 is grounded.

9. An electronic device, comprising: The low-power small-area high-PSR all-MOS voltage reference circuit as claimed in any one of claims 1 to 8 is mounted. The low-power small-area high-PSR all-MOS voltage reference circuit as claimed in any one of claims 1 to 8 is mounted.

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