Low dropout regulator (LDO) circuit with fast transient response and without off-chip capacitor

Abstract

The invention provides a fast transient response LDO circuit without an off-chip capacitor. The fast transient response LDO circuit comprises a partial pressure feedback unit, an error amplification output unit, a fast response unit and a load tracking unit. The input end of the voltage division feedback unit is connected with the output end of the fast transient response LDO circuit without the off-chip capacitor, and the voltage division feedback unit is used for dividing output voltage to obtain feedback voltage; the error amplification output unit is used for comparing the feedback voltage with the external reference voltage and generating output for controlling a power tube in the quick response unit; the fast response unit is used for controlling the power tube according to the output from the error amplification output unit and enabling the control end voltage of the power tube to change along with the output voltage of the power tube, and the output end of the power tube serves as the output end of the fast transient response LDO circuit without the off-chip capacitor; and the load tracking unit is connected with the power tube and the output side of the error amplification output unit.

Description

Technical Field

[0001] The invention relates to the technical field of electronic circuits, and in particular to a fast transient response LDO circuit without an external capacitor. Background Art

[0002] A low dropout regulator (LDO) is a DC voltage regulator circuit that mainly realizes voltage conversion. It is used in electronic equipment systems to provide stable and low-noise power supply for other circuit components.

[0003] The output end of a traditional LDO chip is usually configured with an off-chip capacitor to provide a transient current through a large off-chip capacitor when the load current increases instantaneously, so as to avoid a large dive or overshoot voltage generated by the LDO chip due to the inability of the power tube to react instantly. In the prior art, with the development of system on chip (SoC) technology, multiple discrete chips of the original system are integrated into one chip, and the chip integration is getting higher and higher. Therefore, it has gradually become a development trend for LDO chips to be integrated into SoC systems. Since the off-chip capacitors configured by the LDO chip occupy a large area and cannot be placed inside the SoC, the design of LDO circuits without off-chip capacitors has gradually become a research hotspot.

[0004] Currently, the design of LDO circuits without off-chip capacitors has the following two problems: (1) Since there is no large off-chip capacitor to provide transient current, the output voltage will produce a large dive or overshoot voltage when the load current jumps instantly, and the load transient response performance is poor; (2) Since there is no off-chip capacitor, the LDO circuit has no off-chip zero point, making it difficult to ensure the stability of the LDO circuit within a large load current range. Summary of the invention

[0005] The present invention provides a fast transient response LDO circuit without external capacitors, aiming to solve the problem of poor transient response performance and stability of the current LDO circuit without external capacitors. Specifically, the problem of poor transient response performance is solved by a fast response unit inside the circuit, and the problem of poor stability is solved by a load tracking unit inside the circuit.

[0006] In order to solve the above problems, the present invention provides a fast transient response LDO circuit without external capacitor, including a voltage divider feedback unit, an error amplification output unit, a fast response unit and a load tracking unit; wherein,

[0007] The input end of the voltage division feedback unit is connected to the output end of the fast transient response LDO circuit without external capacitor, and is used to divide the output voltage of the fast transient response LDO circuit without external capacitor to obtain a feedback voltage;

[0008] The error amplification output unit is connected to the external reference voltage and the output end of the voltage-dividing feedback unit, and is used to compare the feedback voltage with the external reference voltage, and to generate an output to control the power tube in the fast response unit;

[0009] The fast response unit is connected to the output side of the error amplification output unit, and is used to control the power tube according to the output from the error amplification output unit, and make the control terminal voltage of the power tube follow the output voltage change of the power tube, and the output terminal of the power tube serves as the output terminal of the fast transient response LDO circuit without external capacitor;

[0010] The load tracking unit is connected to the power tube and the output side of the error amplification output unit, and is used to replicate the current of the power tube to compensate for the fast transient response LDO circuit without external capacitor.

[0011] A further technical solution is as follows: the fast response unit comprises a flip voltage follower circuit, a source follower circuit and a current source circuit, wherein:

[0012] The current source circuit is used to provide current for the flip voltage follower circuit and the source follower circuit;

[0013] The flip voltage follower circuit includes a follower response circuit and the power tube, the input end of the power tube is connected to the power supply VDD, the control end of the follower response circuit is connected to the output side of the error amplification output unit, the input end and the output end of the follower response circuit are respectively connected to the output end of the power tube and the input end of the source follower circuit, and the follower response circuit is also connected to the current source circuit;

[0014] The output end of the source follower circuit is connected to the control end of the power tube, so as to make the voltage of the control end of the power tube follow the output voltage change of the fast transient response LDO circuit without external capacitor.

[0015] Its further technical solution is: the follower response circuit includes a sixth PMOS tube, the source follower circuit includes a fourth PMOS tube, a second NMOS tube and a second resistor, the current source circuit includes a third NMOS tube and a third PMOS tube, the power tube is a PMOS tube, and its source, drain and gate are the input end, output end and control end of the power tube respectively; wherein,

[0016] The drain of the power tube is connected to the source of the sixth PMOS tube, the drain of the sixth PMOS tube is connected to the drain of the third NMOS tube and the gate of the fourth PMOS tube, the gate of the power tube is connected to the source of the fourth PMOS tube, the drain of the third PMOS tube and the drain of the second NMOS tube, the sources of the power tube and the third PMOS tube are connected to the power supply VDD, and the gates of the third PMOS tube, the third NMOS tube and the sixth PMOS tube are respectively connected to the external bias voltage VBIASP, the external bias voltage VBIASN and the output side of the error amplification output unit, the gate of the second NMOS tube is connected to the drain of the fourth PMOS tube and one end of the second resistor, and the sources of the second NMOS tube and the third NMOS tube and the other end of the second resistor are all grounded.

[0017] A further technical solution is: the current source circuit further includes a third resistor, and the third resistor is connected in parallel between the drain and the source of the third NMOS tube.

[0018] A further technical solution is: the fast response unit further includes a first capacitor, one end of the first capacitor is connected to a power supply VDD, and the other end is connected to the gate of the power tube.

[0019] Its further technical solution is: the fast transient response off-chip capacitor-free LDO circuit also includes a frequency compensation unit, and the frequency compensation unit includes a second capacitor and a fourth resistor, wherein one end of the second capacitor and the fourth resistor connected in series is connected to the drain of the power tube, and the other end is connected to the gate of the fourth PMOS tube.

[0020] Its further technical solution is: the load tracking unit includes a seventh PMOS tube, a fourth NMOS tube and a fourth capacitor, wherein the source of the seventh PMOS tube is connected to the power supply VDD, and the gate thereof is connected to the control end of the power tube, the drain of the seventh PMOS tube is connected to the drain of the fourth NMOS tube, the gate of the fourth NMOS tube is connected to the output side of the error amplification output unit through the fourth capacitor, and the source of the fourth NMOS tube is grounded.

[0021] Its further technical solution is: the voltage divider feedback unit includes a fifth resistor, an adjustable resistor and a sixth resistor, wherein one end of the adjustable resistor is connected to the output end of the fast transient response off-chip capacitor-free LDO circuit through the fifth resistor, the other end of the adjustable resistor is connected to the input side of the error amplification output unit and one end of the sixth resistor, and the other end of the sixth resistor is grounded.

[0022] A further technical solution is as follows: the error amplification output unit includes an operational amplifier and a buffer output circuit, and the buffer output circuit includes a first PMOS tube, a second PMOS tube, a first resistor and a first NMOS tube; wherein,

[0023] The inverting input terminal and the non-inverting input terminal of the operational amplifier are respectively connected to an external reference voltage and the output terminal of the voltage divider feedback unit, the output terminal of the operational amplifier is connected to the gate of the first PMOS tube and the load tracking unit, the source of the first PMOS tube is connected to the power supply VDD, and the drain thereof is connected to the source of the second PMOS tube, the gate and drain of the second PMOS tube are connected and connected to the fast response unit, the gate of the first NMOS tube is connected to the external bias voltage VBIASN, and the drain thereof is connected to the drain of the second PMOS tube and one end of the first resistor, and the source of the first NMOS tube and the other end of the first resistor are both grounded.

[0024] A further technical solution is: the fast transient response LDO circuit without external capacitors also includes a main pole determination unit, the main pole determination unit includes a third capacitor, one end of the third capacitor is connected to the output end of the operational amplifier, and the other end is grounded.

[0025] Compared with the prior art, the fast transient response and no external capacitor LDO circuit of the present invention is provided with a fast response unit and a load tracking unit. The output of the power tube in the fast response unit is the output of the fast transient response and no external capacitor LDO circuit. On the one hand, the control terminal voltage of the power tube can follow the output voltage change of the power tube through the fast response unit, thereby controlling the power tube current, so as to quickly adjust the output voltage when the load current jumps instantly, accelerate the transient response recovery speed, and also reduce the overshoot and dive voltage during the transient jump. On the other hand, the current of the power tube can be copied through the load tracking unit to generate a zero point that can track the load, that is, the position of the zero point is changed according to the change of the load current, the LDO circuit of the present invention is compensated, the stability under different load conditions is improved, and the transient performance of the circuit is improved to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying any creative work.

[0027] Figure 1 The diagram is a circuit structure diagram of a fast transient response LDO circuit without external capacitors provided in one embodiment of the present invention.

[0028] Figure 2 yes Figure 1 The transient response simulation diagram of the LDO circuit with fast transient response and no external capacitor is shown.

[0029] Figure 3 yes Figure 1 The stability simulation diagram of the LDO circuit with fast transient response and no external capacitor is shown.

[0030] Figure 4 yes Figure 1 The stability simulation diagram shown is a fast transient response capacitor-free LDO circuit after removing the load tracking unit and the frequency compensation unit. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] It should be understood that when used in this specification and the appended claims, the terms "include" and "comprises" indicate the presence of described features, integers, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, operations, elements, components and / or groups thereof.

[0033] It should also be understood that the terms used in this specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the specification of the present invention and the appended claims, the singular forms of "a", "an" and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should also be further understood that the term "and / or" used in the specification of the present invention and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0034] Reference Figure 1 , Figure 1The circuit structure diagram of a specific embodiment of a fast transient response LDO circuit without external capacitors of the present invention. In the embodiment shown in the accompanying drawings, the fast transient response LDO circuit without external capacitors includes a voltage division feedback unit 11, an error amplification output unit, a fast response unit 14 and a load tracking unit 15, wherein the input end of the voltage division feedback unit 11 is connected to the output end of the fast transient response LDO circuit without external capacitors, and is used to divide the output voltage VOUT of the fast transient response LDO circuit without external capacitors to obtain a feedback voltage VFB; the error amplification output unit is connected to an external reference voltage VREF and the output end of the voltage division feedback unit 11, and is used to compare the feedback voltage VFB with the external reference voltage VREF, and generate a control signal. The output of the power tube PM5 in the fast response unit 14; the fast response unit 14 is connected to the output side of the error amplification output unit, and is used to control the power tube PM5 according to the output from the error amplification output unit, and make the control end voltage of the power tube PM5 follow the output voltage VOUT of the power tube PM5, and the output end of the power tube PM5 serves as the output end of the fast transient response no-off-chip capacitor LDO circuit; the load tracking unit 15 is connected to the power tube PM5 and the output side of the error amplification output unit, and is used to copy the current of the power tube PM5 to compensate the fast transient response no-off-chip capacitor LDO circuit. Based on the above design, the fast response unit 14 works under the action of the output of the error amplification output unit, so that the control terminal voltage of the power tube PM5 can follow the output voltage VOUT of the power tube PM5, thereby controlling the current of the power tube PM5, so as to quickly adjust the output voltage VOUT when the load current jumps instantly, so that the transient response speed is faster, the dive and overshoot of the output voltage when the load jumps are smaller, and the transient performance of the LDO circuit without external capacitors is improved; at the same time, the current of the power tube PM5 can be copied through the load tracking unit 15, and the position of the zero point can be changed according to the change of the load current, that is, a zero point that can track the load is generated, the loop is compensated, and the stability under different load conditions is improved, which can further improve the transient performance of the circuit.

[0035] In some embodiments, the fast response unit 14 includes a flip voltage follower circuit 141, a source follower circuit and a current source circuit, wherein the current source circuit is used to provide current for the flip voltage follower circuit 141 and the source follower circuit; the flip voltage follower circuit 141 includes a follower response circuit and the power tube PM5, the input end of the power tube PM5 is connected to the power supply VDD, the control end of the follower response circuit is connected to the output side of the error amplification output unit, the input end and the output end of the follower response circuit are respectively connected to the output end of the power tube PM5 and the input end of the source follower circuit, and the follower response circuit is also connected to the current source circuit; the output end of the source follower circuit is connected to the control end of the power tube PM5, so as to make the control end voltage of the power tube PM5 follow the output voltage VOUT change of the fast transient response off-chip capacitor LDO circuit. Based on the above design, the follower response circuit and the source follower circuit cooperate with the power tube PM5 to form a loop that feeds back from the output end of the power tube PM5 to the control end of the power tube PM5. When the voltage at the control end of the follower response circuit changes, that is, when the output of the error amplifier output unit changes, the output voltage VOUT at the output end of the power tube PM5 can follow the change well, which is beneficial to the transient recovery of the LDO. The source follower circuit is used to transmit the output voltage of the follower response circuit to the control end of the power tube PM5, thereby controlling the current of the power tube PM5.

[0036] Specifically, in this embodiment, Figure 1As shown, the follower response circuit includes a sixth PMOS tube PM6, the source follower circuit includes a fourth PMOS tube PM4, a second NMOS tube NM2 and a second resistor R2, the current source circuit includes a third NMOS tube NM3 and a third PMOS tube PM3, the power tube PM5 is a PMOS tube, and its source, drain and gate are respectively the input end, output end and control end of the power tube PM5; wherein the drain of the power tube PM5 is connected to the source of the sixth PMOS tube PM6, the drain of the sixth PMOS tube PM6 is connected to the drain of the third NMOS tube NM3 and the gate of the fourth PMOS tube PM4, and the gate of the power tube PM5 is connected to the fourth PMOS tube PM4. The source of the OS transistor PM4, the drain of the third PMOS transistor PM3 and the drain of the second NMOS transistor NM2, the source of the power transistor PM5 and the third PMOS transistor PM3 are all connected to the power supply VDD, and the gates of the third PMOS transistor PM3, the third NMOS transistor NM3 and the sixth PMOS transistor PM6 are respectively connected to the external bias voltage VBIASP, the external bias voltage VBIASN and the output side of the error amplification output unit, the gate of the second NMOS transistor NM2 is connected to the drain of the fourth PMOS transistor PM4 and one end of the second resistor R2, and the sources of the second NMOS transistor NM2 and the third NMOS transistor NM3 and the other end of the second resistor R2 are all grounded. Based on the above design, the flip voltage follower circuit 141 operates in a local closed loop with a pole at an extremely high frequency, and can have a large bandwidth, thereby reducing the reaction time. That is, the fast response unit 14 provides a high-bandwidth loop from the output voltage VOUT to the gate control voltage of the power tube PM5, which can make the gate voltage of the power tube PM5 quickly follow the change of the output voltage VOUT. When the load current increases, the output voltage VOUT of the power tube PM5 decreases, and the gate voltage of the power tube PM5 decreases, thereby increasing the current provided by the power tube PM5 and restoring the output voltage.

[0037] Furthermore, the fast response unit 14 further includes a first capacitor C1, one end of which is connected to the power supply VDD, and the other end of which is connected to the gate of the power tube PM5; the current source circuit further includes a third resistor R3, and the third resistor R3 is connected in parallel between the drain and the source of the third NMOS tube NM3. Based on the above design, the third resistor R3 is connected in parallel with the third NMOS tube NM3, which can reduce the output resistance of the fast response unit 14, thereby reducing the loop gain and improving the loop stability.

[0038] In some embodiments, the load tracking unit 15 includes a seventh PMOS tube PM7, a fourth NMOS tube NM4 and a fourth capacitor C4, wherein the source of the seventh PMOS tube PM7 is connected to the power supply VDD, and the gate thereof is connected to the control end of the power tube PM5, the drain of the seventh PMOS tube PM7 is connected to the drain of the fourth NMOS tube NM4, the gate of the fourth NMOS tube NM4 is connected to the output side of the error amplification output unit through the fourth capacitor C4, and the source of the fourth NMOS tube NM4 is grounded. In the present invention, the seventh PMOS tube PM7 and the power tube PM5 in the load tracking unit 15 form a current mirror, which can copy the current flowing through the power tube PM5 and then flow into the fourth NMOS tube NM4. At this time, the equivalent resistance of the fourth NMOS tube NM4 is related to the current in the power tube PM5. The fourth NMOS tube NM4 and the fourth capacitor C4 can form a feedback loop to feed back the output current of the power tube PM5 to the output side of the error amplification output unit, forming a zero point that can track the load current, so that the loop stability is strongly correlated with the load current, and the loop stability is guaranteed within a large current change range.

[0039] Further, in some embodiments, the fast transient response LDO circuit without external capacitors further includes a frequency compensation unit 16, and the frequency compensation unit 16 includes a second capacitor C2 and a fourth resistor R4, wherein one end of the second capacitor C2 and the fourth resistor R4 connected in series is connected to the drain of the power tube PM5, and the other end is connected to the gate of the fourth PMOS tube PM4. Based on this design, the RC network of the frequency compensation unit 16 can generate a zero point, so that the loop gain drops to 1 more slowly, thereby increasing the bandwidth of the loop and further enhancing stability.

[0040] In this embodiment, the voltage-dividing feedback unit 11 includes a fifth resistor R5, an adjustable resistor Rt and a sixth resistor R6, wherein one end of the adjustable resistor Rt is connected to the output end of the fast transient response LDO circuit without external capacitor through the fifth resistor R5, the other end of the adjustable resistor Rt is connected to the input side of the error amplification output unit and one end of the sixth resistor R6, and the other end of the sixth resistor R6 is grounded. In this embodiment, the voltage VFB after voltage division is fed back to the input side of the error amplification output unit through the adjustable resistor Rt, so adjusting the resistance value of the adjustable resistor Rt can adjust the output voltage VOUT value of the fast transient response LDO circuit without external capacitor of the present invention.

[0041] Continue to refer to Figure 1Specifically, in the embodiment shown in the accompanying drawings, the error amplification output unit includes an operational amplifier U1 and a buffer output circuit, and the buffer output circuit includes a first PMOS transistor PM1, a second PMOS transistor PM2, a first resistor R1 and a first NMOS transistor NM1; wherein the inverting input terminal and the non-inverting input terminal of the operational amplifier U1 are respectively connected to the external reference voltage VREF and the adjustable resistor Rt, the output terminal of the operational amplifier U1 is connected to the gate of the first PMOS transistor PM1 and the fourth capacitor C4 in the load tracking unit 15, the source of the first PMOS transistor PM1 is connected to the power supply VDD, and the drain thereof is connected to the source of the second PMOS transistor PM2, the gate and drain of the second PMOS transistor PM2 are connected, and are connected to the gate of the sixth PMOS transistor PM6, the gate of the first NMOS transistor NM1 is connected to the external bias voltage VBIASN, and the drain thereof is connected to the drain of the second PMOS transistor PM2 and one end of the first resistor R1, and the source of the first NMOS transistor NM1 and the other end of the first resistor R1 are both grounded. Based on the above design, the function of the operational amplifier U1 is mainly to clamp the voltage. When the operational amplifier U1 is working normally, the voltages at both ends of the inverting input terminal and the non-inverting input terminal should be equal, then VREF is equal to VFB, and VFB and the output voltage VOUT are in a voltage-dividing relationship. Therefore, the rated value of the output voltage VOUT of the fast transient response and off-chip capacitor-free LDO circuit of the present invention can also be controlled by adjusting the value of VREF through the operational amplifier U1.

[0042] Preferably, in this embodiment, the fast transient response LDO circuit without external capacitors further includes a main pole determination unit 17, and the main pole determination unit 17 includes a third capacitor C3, one end of the third capacitor C3 is connected to the output end of the operational amplifier U1, and the other end is grounded. Based on this design, the third capacitor C3 to the ground is added to the output end of the operational amplifier U1, which can increase the equivalent capacitance of the output end of the operational amplifier U1 to the ground, so that the output end of the operational amplifier U1 becomes the main pole of the loop. Therefore, changing the value of the third capacitor C3 can well change the main pole of the loop, achieving the goal of ensuring stability while maximizing the bandwidth.

[0043] Continue to refer to Figure 1, the direction of the arrow in the figure is the flow direction of the electrical signal, the fast transient response no-chip capacitor LDO circuit of the present invention works, when the connected load current increases instantaneously, the power tube PM5 cannot provide a large current instantaneously, the current is provided by the parasitic capacitor, and a current from bottom to top is generated, and a voltage in a positive direction at the bottom and a negative direction at the top is generated through the parasitic resistance of the parasitic capacitor, which is superimposed on the output voltage VOUT of the power tube PM5 to reduce its output voltage VOUT. At this time, the gate voltage of the sixth PMOS tube PM6 remains unchanged, and since the current is proportional to VGS-VTH, the current on PM6 decreases. Since the current of the third NMOS tube NM3 and the third resistor R3 is equal to the current on PM6, NM The gate voltage on R3 remains unchanged, and the current on NM3 remains unchanged, so the current on R3 decreases, causing the voltage on the upper end of R3 to decrease. This change is transmitted to the gate of PM4, causing the current on PM4 to increase. Since the current on PM4 plus the current on NM2 equals the current on PM3, the current on PM4 increases at this time, and the current on NM2 decreases. Therefore, the gate voltage of NM2 decreases, causing the current on the second resistor R2 to decrease, that is, the current on PM4 decreases. At this time, the gate voltage of PM4 has not recovered and is still lower than before, so the source voltage of PM4 decreases, that is, the gate voltage of the power tube PM5 decreases, and the power tube PM5 provides a larger current, and the circuit gradually returns to a steady state. For example, as Figure 2 As shown, when the load current jumps from 5mA to 100mA after 100ns, the reaction time is only 3.72ns, and the LDO circuit with fast transient response and no external capacitor of the present invention can recover in only 101ns, and the dive voltage is only 149mv; when the load current jumps from 100mA back to 5mA after 100ns, the LDO can recover in only 130ns, and the overshoot voltage is only 120mv, that is, the LDO circuit with fast transient response and no external capacitor of the present invention can quickly realize transient response, and the dive and overshoot of the output voltage are small when the load jumps.

[0044] Furthermore, during the operation of the fast transient response off-chip capacitor-free LDO circuit of the present invention, stability can be enhanced by the frequency compensation unit 16 and the load tracking unit 15, that is, the RC network composed of the second capacitor C2 and the fourth resistor R4 in the frequency compensation unit 16 can generate a zero point, so that the loop gain drops to 1 more slowly, thereby increasing the bandwidth of the loop, and the seventh PMOS tube PM7 and the power tube PM5 in the load tracking unit 15 form a current mirror, which can copy the current flowing through the power tube PM5, and then feed back the output current of the power tube PM5 to the output end of the operational amplifier U1 through the fourth NMOS tube NM4 and the fourth capacitor C4, forming a zero point capable of tracking the load current, thereby ensuring loop stability within a large current variation range. For example, as Figure 3 As shown, Figure 3The stability simulation schematic diagram is obtained by simulating the stability of the fast transient response LDO circuit without external capacitors of the present invention. It can be seen from the figure that when the load current is 100mA, the bandwidth is 113.4Mhz and the phase margin is 45 degrees; and when the load tracking unit 15 and the frequency compensation unit 16 in the fast transient response LDO circuit without external capacitors are removed and the stability is simulated, it can be obtained Figure 4 From the stability simulation diagram shown, it can be seen that when the load current is 100mA, its bandwidth is 88Mhz and the phase margin is <0 degrees. Through the above comparison, it can be concluded that the fast transient response LDO circuit without external capacitor of the present invention can well ensure the stability of the loop, and to a certain extent improve the bandwidth and optimize the transient performance.

[0045] In summary, the present invention greatly improves the transient performance through the fast response unit 14, making the transient response speed faster, and the output voltage dive and overshoot smaller when the load jumps, thereby improving the problem of poor transient performance without external capacitors; and also generates load-related zero poles through the load tracking unit 15, thereby improving the stability problem that is very easy to occur when the light load and heavy load current of the LDO differ greatly. At the same time, a zero point is generated through the frequency compensation unit 16, thereby avoiding the stability problem caused by the lack of an external zero point of the LDO without external capacitors. Through these two compensation methods, not only the stability of the circuit is improved, but also the circuit bandwidth is increased, thereby improving the transient performance of the circuit to a certain extent.

[0046] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A fast transient response LDO circuit without external capacitor, characterized in that: The fast transient response LDO circuit without external capacitor includes a voltage division feedback unit, an error amplification output unit, a fast response unit and a load tracking unit; wherein, The input end of the voltage division feedback unit is connected to the output end of the fast transient response LDO circuit without external capacitor, and is used to divide the output voltage of the fast transient response LDO circuit without external capacitor to obtain a feedback voltage; The error amplification output unit is connected to the external reference voltage and the output end of the voltage-dividing feedback unit, and is used to compare the feedback voltage with the external reference voltage, and to generate an output to control the power tube in the fast response unit; The fast response unit is connected to the output side of the error amplification output unit, and is used to control the power tube according to the output from the error amplification output unit, and make the control terminal voltage of the power tube follow the output voltage change of the power tube, and the output terminal of the power tube serves as the output terminal of the fast transient response LDO circuit without external capacitor; The load tracking unit is connected to the power tube and the output side of the error amplification output unit, and is used to replicate the current of the power tube to compensate for the fast transient response LDO circuit without external capacitor.

2. The fast transient response LDO circuit without external capacitor as claimed in claim 1, characterized in that: The fast response unit includes a flip voltage follower circuit, a source follower circuit and a current source circuit, wherein: The current source circuit is used to provide current for the flip voltage follower circuit and the source follower circuit; The flip voltage follower circuit includes a follower response circuit and the power tube, the input end of the power tube is connected to the power supply VDD, the control end of the follower response circuit is connected to the output side of the error amplification output unit, the input end and the output end of the follower response circuit are respectively connected to the output end of the power tube and the input end of the source follower circuit, and the follower response circuit is also connected to the current source circuit; The output end of the source follower circuit is connected to the control end of the power tube, so as to make the voltage of the control end of the power tube follow the output voltage change of the fast transient response LDO circuit without external capacitor.

3. The fast transient response LDO circuit without external capacitor as claimed in claim 2, characterized in that: The follower response circuit includes a sixth PMOS tube, the source follower circuit includes a fourth PMOS tube, a second NMOS tube and a second resistor, the current source circuit includes a third NMOS tube and a third PMOS tube, the power tube is a PMOS tube, and its source, drain and gate are the input end, output end and control end of the power tube respectively; wherein, The drain of the power tube is connected to the source of the sixth PMOS tube, the drain of the sixth PMOS tube is connected to the drain of the third NMOS tube and the gate of the fourth PMOS tube, the gate of the power tube is connected to the source of the fourth PMOS tube, the drain of the third PMOS tube and the drain of the second NMOS tube, the sources of the power tube and the third PMOS tube are connected to the power supply VDD, and the gates of the third PMOS tube, the third NMOS tube and the sixth PMOS tube are respectively connected to the external bias voltage VBIASP, the external bias voltage VBIASN and the output side of the error amplification output unit, the gate of the second NMOS tube is connected to the drain of the fourth PMOS tube and one end of the second resistor, and the sources of the second NMOS tube and the third NMOS tube and the other end of the second resistor are all grounded.

4. The fast transient response LDO circuit without external capacitor as claimed in claim 3, characterized in that: The current source circuit further includes a third resistor, which is connected in parallel between the drain and the source of the third NMOS tube.

5. The fast transient response LDO circuit without external capacitor as claimed in claim 3, characterized in that: The fast response unit further includes a first capacitor, one end of which is connected to a power source VDD, and the other end of which is connected to the gate of the power tube.

6. The fast transient response LDO circuit without external capacitor as claimed in claim 3, characterized in that: The fast transient response and off-chip capacitor-free LDO circuit also includes a frequency compensation unit, which includes a second capacitor and a fourth resistor, wherein one end of the second capacitor and the fourth resistor connected in series is connected to the drain of the power tube, and the other end is connected to the gate of the fourth PMOS tube.

7. The fast transient response LDO circuit without external capacitor as claimed in claim 1, characterized in that: The load tracking unit includes a seventh PMOS tube, a fourth NMOS tube and a fourth capacitor, wherein the source of the seventh PMOS tube is connected to the power supply VDD, and the gate thereof is connected to the control end of the power tube, the drain of the seventh PMOS tube is connected to the drain of the fourth NMOS tube, the gate of the fourth NMOS tube is connected to the output side of the error amplification output unit through the fourth capacitor, and the source of the fourth NMOS tube is grounded.

8. The fast transient response LDO circuit without external capacitor as claimed in claim 1, characterized in that: The voltage divider feedback unit includes a fifth resistor, an adjustable resistor and a sixth resistor, wherein one end of the adjustable resistor is connected to the output end of the fast transient response off-chip capacitor-free LDO circuit through the fifth resistor, the other end of the adjustable resistor is connected to the input side of the error amplification output unit and one end of the sixth resistor, and the other end of the sixth resistor is grounded.

9. The fast transient response LDO circuit without external capacitor as claimed in claim 1, characterized in that: The error amplification output unit includes an operational amplifier and a buffer output circuit, and the buffer output circuit includes a first PMOS tube, a second PMOS tube, a first resistor and a first NMOS tube; wherein, The inverting input terminal and the non-inverting input terminal of the operational amplifier are respectively connected to an external reference voltage and the output terminal of the voltage divider feedback unit, the output terminal of the operational amplifier is connected to the gate of the first PMOS tube and the load tracking unit, the source of the first PMOS tube is connected to the power supply VDD, and the drain thereof is connected to the source of the second PMOS tube, the gate and drain of the second PMOS tube are connected and connected to the fast response unit, the gate of the first NMOS tube is connected to the external bias voltage VBIASN, and the drain thereof is connected to the drain of the second PMOS tube and one end of the first resistor, and the source of the first NMOS tube and the other end of the first resistor are both grounded.

10. The fast transient response LDO circuit without external capacitor as claimed in claim 9, characterized in that: The fast transient response LDO circuit without external capacitors also includes a main pole determination unit, and the main pole determination unit includes a third capacitor, one end of the third capacitor is connected to the output end of the operational amplifier, and the other end is grounded.

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