Symbol transfer multiplication unit circuit, multiply-accumulate calculation circuit and module

Abstract

The invention relates to the technical field of analog domain in-memory calculation, in particular to a symbol transfer multiplication unit circuit, a multiplication-accumulation calculation circuit and a module. The invention provides a symbol transfer multiplication unit circuit. The symbol transfer multiplication unit circuit comprises a symbol storage part, a weight storage part, a turn-off control part and a storage calculation part, a symbol transfer multiplication unit circuit is designed, weight symbols are equivalently transferred to input values, and the multiplication calculation process with sign bits is simplified; the analog domain calculation is realized by directly charging and sampling the analog voltage of the capacitor, so that the PVT influence is effectively reduced; the left capacitor and the right capacitor alternately work in an assembly line mode, the limitation of quantitative waiting is solved, the working efficiency is improved, and the throughput rate is increased.

Description

Technical Field

[0001] The present invention relates to the field of analog domain in-memory computing technology, and more specifically, to: 1. a sign transfer multiplication unit circuit; 2. a sign transfer multiplication module based on the layout of the sign transfer multiplication unit circuit; 3. a multiplication-accumulation calculation circuit constructed based on the sign transfer multiplication unit circuit; 4. a multiplication-accumulation calculation module based on the layout of the multiplication-accumulation calculation circuit. Background Art

[0002] The traditional von Neumann architecture is no longer suitable for the current AI applications’ demand for high computing power due to the memory wall problem. In-memory computing has become the mainstream choice for improving the computing efficiency of deep neural networks in AI. In-memory computing in the analog domain is subject to many influences and is unreliable. Although there are many analog domain memory computing architectures conducting research in related directions, this field still needs more reliable solutions.

[0003] At present, the in-memory calculation in the analog domain tends to use 8T-SRAM: 8T-SRAM is used as a multiplication calculation unit with a simple structure; only two MOS tubes and a calculation bit line are added to complete the multiplication and accumulation calculation, and it can be matched with more input methods. The input signal and the stored data represent the result of the multiplication calculation by controlling whether the two additional MOS tubes are turned on or off. If the multiplication calculation result is 1, the calculation bit line is discharged, and if the result is 0, it is not discharged. All rows in the same column discharge the charge stored in the parasitic capacitance of the calculation bit line at the same time, thereby realizing the multiplication and accumulation function.

[0004] Since the above design adopts charge discharge, the discharge accuracy requirement is very high. However, the actual discharge accuracy is greatly affected by PVT (process voltage temperature).

[0005] In addition, the above-mentioned design for realizing multiplication and multiplication-accumulation calculations cannot realize continuous calculations, because it needs to quantify the results in time after each calculation is completed, and quantization also takes time. This results in the calculation efficiency being limited by the quantization of the results. Summary of the invention

[0006] Based on this, in order to solve the problem that the existing analog domain in-memory multiplication calculation is greatly affected by PVT and the calculation efficiency is limited by the result quantization, the present invention provides a sign transfer multiplication unit circuit, a multiplication and accumulation calculation circuit and an in-memory calculation circuit.

[0007] The present invention is implemented by the following technical solutions:

[0008] In a first aspect, the present invention provides a sign transfer multiplication unit circuit for performing multiplication calculation of a 2-bit analog input Input and a 2-bit signed weight value Weight.

[0009] The sign transfer multiplication unit circuit includes: a sign storage unit, a weight storage unit, a shutdown control unit, and an in-memory calculation unit.

[0010] The symbol storage unit includes: a symbol storage subunit, a bit line BL sign , bit line BLB sign 、Inverter INV sign The symbol storage sub-unit includes: 1 column of N 6T-SRAM cells 1, N ≥ 1. Each 6T-SRAM cell 1 stores a 1-bit symbol of Weight. The symbol storage sub-unit shares BL sign ,BLB sign . INV sign The input terminal of BL sign .

[0011] The weight storage unit includes: a weight storage subunit, a bit line BL, and a bit line BLB. The weight storage subunit includes: a column of N 6T-SRAM cells 2. Each 6T-SRAM cell 2 stores a 1-bit weight value of Weight. The weight storage subunit shares BL and BLB.

[0012] The shutdown control unit is used to control the BL sign ,BLB sign , BL, and BLB are turned on and off to switch the entire circuit between read-write mode and multiplication mode.

[0013] The internal computing part of the memory includes: input sub-part, control sub-part, left capacitor part, right capacitor part, and a charging bit line Bottom. sign The output terminal, BL, and BLB are connected to each other, and are used to input Input and Weight in multiplication mode, and selectively charge Bottom according to Input and Weight. The left capacitor unit includes: 1 capacitor Cap_L, an output bit line DL, and the upper plate of Cap_L is connected to DL. The right capacitor unit includes: 1 capacitor Cap_R, an output bit line DR, and the upper plate of Cap_R is connected to DR. The control sub-unit is used to control the lower plates of Cap_L and Cap_R to be alternately connected to Bottom to realize continuous multiplication calculation and store the multiplication results in the lower plates of the corresponding capacitors.

[0014] The implementation of the sign transfer multiplication unit circuit is based on the method or process of the embodiment of the present disclosure.

[0015] In a second aspect, the present invention discloses a sign transfer multiplication unit module, which adopts the layout of the sign transfer multiplication unit circuit disclosed in the first aspect.

[0016] The implementation of this sign transfer multiplication unit module is based on the method or process of an embodiment of the present disclosure.

[0017] In a third aspect, the present invention discloses a multiplication-accumulation calculation circuit, which is used to perform multiplication-accumulation calculations on a 2-bit analog input Input and a 2-bit signed weight value Weight.

[0018] The multiplication-accumulation-addition calculation circuit includes: a multiplication-accumulation-addition calculation unit.

[0019] The multiplication and accumulation calculation unit comprises: a column of M sign transfer multiplication unit circuits as disclosed in the first aspect; the M sign transfer multiplication unit circuits share a BL sign ,BLB sign ,BL,BLB,DL,DR,S DL_1 , S DL_2 , S DR_1 , S DR_2 , SL, SR, WVCM.

[0020] Among them, S DL_1 , S DL_2 Located on both sides of the multiplication and accumulation calculation unit; S DR_1 , S DR_2 Located on both sides of the multiplication and accumulation calculation unit; S DL_1 , S DR_1 On the same side; S DL_2 , S DR_2 Located on the same side.

[0021] The implementation of the multiplication-accumulation-addition calculation circuit is based on the method or process of the embodiment of the present disclosure.

[0022] In a fourth aspect, the present invention discloses a multiplication-accumulation-addition calculation module, which adopts the layout of the multiplication-accumulation-addition calculation circuit disclosed in the first aspect.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] 1. The present invention designs a sign transfer multiplication unit circuit, which transfers the weight sign to the input value equivalently, simplifies the signed bit multiplication calculation process; uses capacitor analog voltage direct charging sampling to realize analog domain calculation, effectively reducing the PVT impact; adopts left and right capacitors to work alternately in a pipeline manner, solves the limitation of quantization waiting, increases work efficiency, and improves throughput.

[0025] 2. The present invention designs a multiplication-accumulation calculation circuit based on a sign transfer multiplication unit circuit, simplifies the accumulation calculation process of signed bit multiplication, reduces the PVT impact, and solves the limitation of quantization waiting by alternating the left and right paths in a pipeline manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0027] Figure 1 A circuit structure diagram of a sign transfer multiplication unit provided in Embodiment 1 of the present invention;

[0028] Figure 2 for Figure 1 Schematic diagram of the left and right pipelines working;

[0029] Figure 3 This is a structural diagram of the multiplication-accumulation calculation circuit provided in Example 2 of the present invention. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] It should be noted that when a component is referred to as being "mounted on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component at the same time. When a component is considered to be "fixed to" another component, it may be directly fixed on the other component or there may be a central component at the same time.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "or / and" used herein includes any and all combinations of one or more of the related listed items.

[0033] Example 1

[0034] See also Figure 1 , which shows a circuit diagram of a sign transfer multiplication unit circuit provided in this embodiment 1.

[0035] In general, the sign transfer multiplication unit circuit is designed to perform multiplication calculation of a 2-bit analog input Input and a 2-bit signed weight value Weight.

[0036] Among them, Input has four cases: "00", "01", "10", and "11"; Weight includes 1 bit of sign bit and 1 bit of weight bit, and it has four cases: "negative 1", "positive 1", "positive 0", and "negative 0".

[0037] Functionally, the sign transfer multiplication unit circuit includes: a sign storage unit, a weight storage unit, a shutdown control unit, and an in-memory calculation unit.

[0038] See also Figure 1 , the following is a detailed introduction to each part:

[0039] 1. The symbol storage unit includes: a symbol storage subunit, a bit line BL sign , bit line BLB sign 、Inverter INV sign .

[0040] The symbol storage sub-unit includes: 1 column of N 6T-SRAM cells, N≥1.

[0041] Among them, the 6T-SRAM cell 1 is a conventional 6T-SRAM cell, and its structure is well known in the art and will not be described here in detail.

[0042] Each 6T-SRAM cell stores a 1-bit sign bit of Weight: if a 6T-SRAM cell stores "0", it means that the 1-bit sign bit is positive; if a 6T-SRAM cell stores "1", it means that the 1-bit sign bit is negative.

[0043] Symbol storage sub-unit shared BL sign ,BLB sign ;INV sign The input terminal of BL sign .

[0044] 2. The weight storage unit includes: a weight storage sub-unit, a bit line BL, and a bit line BLB.

[0045] The weight storage sub-unit includes: 1 column of N 6T-SRAM cells 2.

[0046] Among them, the 6T-SRAM cell 2 is a conventional 6T-SRAM cell, and its structure is well known in the art and will not be described here in detail.

[0047] Each 6T-SRAM cell 2 stores a 1-bit weight value of Weight: if a 6T-SRAM cell 2 stores "0", it means that the 1-bit weight value is 0; if a 6T-SRAM cell 2 stores "1", it means that the 1-bit weight value is 1.

[0048] The weight storage subunits share BL and BLB.

[0049] 3. Shutdown control unit is used to control BL sign ,BLB sign , BL, and BLB are turned on and off to switch the entire circuit between read-write mode and multiplication mode.

[0050] like Figure 1 As shown, the shutdown control unit can be designed to include: 2 weight switches S 9 ~S 10 , 2 symbol switches S 13 ~S 14 .

[0051] Specifically, S. 9 Set on BL and located on one side of the weight storage subunit; S 10 Set on the BLB and located on one side of the weight storage subunit; S 13 Set up in BL sign On the side of the symbol storage sub-unit; S 14 Set up in BLB sign On the side of the symbol storage subsection. INV sign With BL sign The connection end is located at S 13 , weights are stored between sub-sections.

[0052] Among them, S 9 ~S 10 , S 13 ~S 14 The state always remains the same. 9 ~S 10 , S 13 ~S 14 Can be controlled independently or with a unified signal S 位 to control. Figure 1 As shown, it shows the use of S 位 For S 9 ~S 10 , S 13 ~S 14 Schematic diagram for control: S 位 When it is high, S 9 ~S 10 , S 13 ~S 14Conductivity; S 位 When it is low, S 9 ~S 10 , S 13 ~S 14 disconnect.

[0053] Thus, when S 9 ~S 10 , S 13 ~S 14 When off, BL sign ,BLB sign , BL, and BLB are all disconnected, and the entire circuit enters the multiplication mode.

[0054] When S 9 ~S 10 , S 13 ~S 14 When turned on, BL sign ,BLB sign , BL, and BLB are all turned on, and the entire circuit enters the read-write mode.

[0055] Among them, the read and write mode is to read and write the weight storage sub-section and the symbol storage sub-section. The process is similar to the read and write operation of the conventional 6T-SRAM and will not be repeated here.

[0056] The multiplication mode reflects the difference between the present invention and the existing design, which will be described in detail later.

[0057] 4. The in-memory computing section includes: an input subsection, a control subsection, a left capacitor section, a right capacitor section, and a charging bit line Bottom.

[0058] 401, Input subsection and INV sign The output terminals, BL and BLB are connected to input Input and Weight in the multiplication mode, and Bottom is selectively charged according to Input and Weight.

[0059] like Figure 1 As shown, the input sub-section can be designed to include: an input bit line Sign, an input bit line VINN, a reference bit line VCM, an input bit line VINP, two NMOS tubes N1-N2, and three PMOS tubes P1-P3.

[0060] Specifically, Sign and INV signThe output end of N1 is connected; the gate of N1 is connected to BL, and the drain is connected to VINP; the gate of N2 is connected to Sign, the drain is connected to the source of N1, and the source is connected to Bottom; the gate of P1 is connected to Sign, and the drain is connected to VINN; the gate of P2 is connected to BLB, the drain is connected to the source of P1, and the source is connected to Bottom; the gate of P3 is connected to BL, the drain is connected to VCM, and the source is connected to Bottom.

[0061] It should be noted that the connection between N1 and BL is located at S 9 , weight storage sub-unit; the connection end between P2 and BLB is located at S 10 , weights are stored between sub-sections.

[0062] The input sub-unit actually uses VINN, VCM, and VINP to input Input.

[0063] Among them, if Input is "00", VINP input is 3*VDD / 6, VINN input is 3*VDD / 6, and VCM input is 3*VDD / 6;

[0064] If Input is "01", VINP input is 2*VDD / 6, VINN input is 4*VDD / 6, and VCM input is 3*VDD / 6;

[0065] If Input is "10", VINP input is VDD / 6, VINN input is 5*VDD / 6, and VCM input is 3*VDD / 6;

[0066] If Input is "11", VINP inputs VSS, VINN inputs VDD, and VCM inputs 3*VDD / 6;

[0067] Among them, VSS=0*VDD / 6, which represents the minimum voltage; VDD represents the maximum voltage.

[0068] 402. The left capacitor unit includes: a capacitor Cap_L and an output bit line DL, wherein the upper plate of Cap_L is connected to DL.

[0069] 403. The right capacitor unit includes: a capacitor Cap_R and an output bit line DR, and the upper plate of Cap_R is connected to DR.

[0070] 404. The control sub-unit is used to control the lower plates of Cap_L and Cap_R to be alternately connected to Bottom to achieve continuous multiplication calculation and store the multiplication result in the lower plate of the corresponding capacitor.

[0071] like Figure 1 As shown, the control sub-unit can be designed to include: a left local bit line SL, a right local bit line SR, a global bit line WVCM, and four switches S 1~S 4 , 2 left switches S DL_1 ~S DL_2 , 2 right switches S DR_1 ~S DR_2 .

[0072] Specifically, the left end of Bottom passes through S 1 Connect the lower plate of Cap_L and the right end through S 2 Connect the lower plate of Cap_R; WVCM through S 3 Connected to Bottom; S 3 The connection with Bottom is located at S 1 , Cap_L; WVCM through S 4 Connected to Bottom; S 4 The connection with Bottom is located at S 2 , Cap_R; the upper plate of Cap_L passes through S DL_1 Connected to WVCM; the upper plate of Cap_L is connected to WVCM through S DL_2 Connected to the quantization circuit (not shown); the upper plate of Cap_R is connected to the quantization circuit (not shown); DR_1 Connected to WVCM; the upper plate of Cap_R is connected to WVCM through S DR_2 Connected to the quantization circuit (not shown).

[0073] Among them, S 1 , S 4 The state always remains the same; S 2 , S 3 The state always remains the same; S 1 , S 2 The state is always opposite. 1 ~S 4 It can be controlled independently or by using signals A and A_B. Figure 1 As shown, it shows the use of A to S 1 and S 4 Control, A_B to S 2 and S 3 Schematic diagram of control: A and A_B are opposite signals; when A is high level, S 1 , S 4 On, S 2 , S 3 Disconnect; when A is low, S 1 , S 4 Disconnect, S 2 , S 3 Conductivity.

[0074] S DL_1 , S DR_2The state always remains the same; S DR_1 , S DL_2 The state always remains the same; S DL_1 , S DL_2 The state is always opposite. DL_1 , S DR_2 , S DR_1 , S DL_2 It can be controlled independently or by using signals C and C_B. Figure 1 As shown, it shows the use of C to S DL_1 and S DR_2 Control, C_B to S DR_1 and S DL_2 Schematic diagram of control: C and C_B are opposite signals; when C is high level, S DL_1 , S DR_2 On, S DR_1 , S DL_2 Disconnect; when C is low, S DR_1 , S DL_2 Disconnect, S DR_1 , S DL_2 Conductivity.

[0075] Based on the above-designed sign transfer multiplication unit circuit, its operation mode in multiplication mode is as follows:

[0076] ①. If only one multiplication calculation is performed, then:

[0077] Open one of the 6T-SRAM units 1 in the symbol storage subunit and one of the 6T-SRAM units 2 in the weight storage subunit:

[0078] When the 1-bit sign bit is positive and the 1-bit weight value is 0, INV sign Output 1 to Sign, P1 is turned off, N2 is turned on; BL is 0, BLB is 1, N1 and P2 are turned off, P3 is turned on; VINN and VINP are disconnected from Bottom, VCM is connected to Bottom, and the voltage of VCM is charged to Bottom;

[0079] When the 1-bit sign bit is negative and the 1-bit weight value is 0, INV sign Output 0 to Sign, P1 is turned on, N2 is turned off; BL is 0, BLB is 1, N1 and P2 are turned off, P3 is turned on; VINN and VINP are disconnected from Bottom, VCM is connected to Bottom, and the voltage of VCM is charged to Bottom;

[0080] When the 1-bit sign bit is positive and the 1-bit weight value is 1, INV signOutput 1 to Sign, P1 is turned off, N2 is turned on; BL is 1, BLB is 0, N1 and P2 are turned on, P3 is turned off; VINN, VCM and Bottom are disconnected, VINP is connected to Bottom, and the voltage of VINP is charged to Bottom;

[0081] When the 1-bit sign bit is negative and the 1-bit weight value is 1, INV sign Output 0 to Sign, P1 is turned on, N2 is turned off; BL is 1, BLB is 0, N1 and P2 are turned on, P3 is turned off; VINP, VCM and Bottom are disconnected, VINN is connected to Bottom, and the voltage of VINN is charged to Bottom.

[0082] Although the above four situations all charge the Bottom, due to the different voltages of VCM, VINP, and VINN, the final voltage value of the Bottom is also different, which reflects the multiplication result.

[0083] Then, select the left capacitor or the right capacitor to store the voltage of the Bottom:

[0084] If the left capacitor is used, the S 1 , S 4 , turn off S 2 , S 3 , store the charging result of Bottom into Cap_L (at this time Cap_R and Bottom are disconnected);

[0085] If the right capacitor is used, the S 2 , S 3 , turn off S 1 , S 4 , store the charging result of Bottom into Cap_R (at this time Cap_L and Bottom are disconnected).

[0086] ② If continuous multiplication is performed, control S DL_1 ~S DL_2 , S DR_1 ~S DR_2 The two paths are switched on and off to realize quantization in one of the left and right paths and multiplication in the other path, and the result of each multiplication is reflected in DL or DR.

[0087] Specifically, before each multiplication calculation, WVCM inputs 3*VDD / 6; first turns on the shutdown control unit; then turns on BL sign ,BLB sign , BL, BLB are pre-charged to VDD, and then the shutdown control unit is turned off;

[0088] For a single multiplication calculation, refer to ① and select one of the left and right paths for multiplication:

[0089] If the left path is selected, conduct S DL_1 , S DL_2 , turn off S DR_1 , S DL_2 , DL is charged to 3*VDD / 6 by WVCM; the sign transfer multiplication unit circuit performs a multiplication calculation and stores the multiplication result in the lower plate of Cap_L; turns off S DL_1 , S DL_2 , turn on S DR_1 , S DL_2 , DL is disconnected from WVCM; S is turned on 3 , the lower plate of Cap_L is charged by WVCM through SL; the multiplication calculation value is transferred to the upper plate of Cap_L (i.e., DL); DL is connected to the quantization circuit and quantization can be performed.

[0090] If the right path is selected, conduct S DR_1 , S DL_2 , turn off S DL_1 , S DL_2 , DR is charged to 3*VDD / 6 by WVCM; the sign transfer multiplication unit circuit performs a multiplication calculation and stores the multiplication result in the lower plate of Cap_R; turns off S DR_1 , S DL_2 , turn on S DL_1 , S DL_2 , DR is disconnected from WVCM; S is turned on 4 , Cap_R is charged by WVCM through SR; the multiplication calculation value is transferred to the upper plate of Cap_L (i.e., DR); DR is connected to the quantization circuit and quantization can be performed.

[0091] The continuous multiplication rule requires that the two multiplication calculations use different paths: in the Xth calculation, the charging result of Bottom is stored in Cap_L, and DR is quantized at the same time; in the X+1th calculation, the charging result of Bottom is stored in Cap_R, and DL is quantized at the same time; X represents a positive integer.

[0092] So, see Figure 2 , the left and right paths form a pipeline work: time 1 ~time N It represents the time of N multiplication calculations. When the left path is being calculated, the right path is being quantized. When the right path is being calculated, the left path is being quantized. This saves the time of waiting for quantization and improves work efficiency.

[0093] This embodiment 1 also discloses a sign transfer multiplication unit module, which adopts the layout of the sign transfer multiplication unit circuit and is packaged into a module, which makes it easier to promote and apply the circuit.

[0094] Example 2

[0095] See also Figure 3 , which shows a circuit diagram of a multiplication-accumulation calculation circuit provided in this embodiment 2.

[0096] In general, the multiplication-accumulation calculation circuit is designed to perform multiplication-accumulation calculations on a 2-bit analog input Input and a 2-bit signed weight value Weight.

[0097] Functionally, the multiplication-accumulation-addition calculation circuit includes: a multiplication-accumulation-addition calculation unit.

[0098] See also Figure 3 The multiplication and accumulation calculation unit can be designed to include: 1 column of M sign transfer multiplication unit circuits as disclosed in Example 1.

[0099] M symbol transfer multiplication unit circuits share BL sign ,BLB sign ,BL,BLB,DL,DR,S DL_1 , S DL_2 , S DR_1 , S DR_2 , SL, SR, WVCM.

[0100] Among them, S DL_1 , S DL_2 Located on both sides of the multiplication and accumulation calculation unit; S DR_1 , S DR_2 Located on both sides of the multiplication and accumulation calculation unit; S DL_1 , S DR_1 On the same side; S DL_2 , S DR_2 Located on the same side.

[0101] See also Figure 3 , showing that WVCM is located on the upper side of the multiplication and accumulation calculation unit, S DL_1 ~S DR_1 Located above the multiplication and accumulation calculation unit, S DL_2 ~S DR_2 The case where it is located below the multiplication and accumulation calculation unit.

[0102] For ease of understanding, the M distributed sign transfer multiplication unit circuit in one column is divided into two small columns and M rows: the M units in the first small column correspond to 1 bit sign bit, respectively, with W 0 [1]~W M [1] indicates that the M units in the second column correspond to 1-bit weights, respectively represented by W 0 [0]~W M [0] indicates that the M units in the second column correspond to M 2-bit analog inputs, respectively, IN0 [0:1]~IN M [0:1] represents.

[0103] It should be noted that a single symbol transfer multiplication unit circuit has one control sub-unit (SL has S 3 , there is S on SR 4 ), then, when M symbol transfer multiplication unit circuits share SL and SR, it is recommended to use the S 3 , S 4 Placed on the same side, M control sub-units S 3 , S 4 Also placed on the same side (such as Figure 2 As shown, it is located on the upper side of Bottom), then WVCM reaches W M [0] The Cap_L lower plate needs to go through M S 3 , from WVCM to W M [0] The Cap_R lower plate needs to undergo M S 4 .

[0104] The multiplication-accumulation calculation circuit based on the above structure can perform M times of accumulation of multiplications and continuous calculation of multiplication-accumulation:

[0105] ① If one round of multiplication and accumulation is performed (i.e., accumulation of M multiplications), then:

[0106] Before performing the multiplication and accumulation calculation, WVCM inputs 3*VDD / 6; first turn on all the shutdown control parts of the multiplication and accumulation calculation part; then turn on BL sign ,BLB sign After BL, BLB are pre-charged to VDD, all shutdown control parts of the multiplication and accumulation calculation part are shut down.

[0107] Among them, BL sign ,BLB sign Precharging BL, BLB to VDD can be achieved using a precharging circuit (not shown).

[0108] When performing multiplication and accumulation calculations, one of the left and right paths is selected for multiplication and accumulation;

[0109] If the left path is selected, conduct S DL_1 , S DL_2 , turn off S DR_1 , S DL_2 , DL is charged to 3*VDD / 6 by WVCM; each sign transfer multiplication unit circuit performs a multiplication calculation and stores the multiplication results in the lower plate of the left capacitor; turn off S DL_1 , S DL_2 , turn on S DR_1 , S DL_2, DL is disconnected from WVCM; M S on SL are turned on 3 , the lower plates of the M Cap_L on the left share charge and are charged by WVCM through SL; the upper plates of the M Cap_L on the left also share charge and transfer the accumulated calculation value of M multiplications to DL; DL is connected to the quantization circuit and quantization can be performed.

[0110] If the right path is selected, conduct S DR_1 , S DL_2 , turn off S DL_1 , S DL_2 , DR is charged to 3*VDD / 6 by WVCM; each sign transfer multiplication unit circuit performs a multiplication calculation and stores the multiplication results in the lower plate of the right capacitor; turn off S DR_1 , S DL_2 , turn on S DL_1 , S DL_2 DR is disconnected from WVCM; M S on SR are turned on 4 The lower plates of the M Cap_R on the right share charge and are charged by WVCM through SR; the upper plates of the M Cap_R on the left also share charge and transfer the accumulated calculation value of M multiplications to DR; DR is connected to the quantization circuit and quantization can be performed.

[0111] ② If continuous multiplication and accumulation calculations are performed, by controlling S DL_1 ~S DL_2 , S DR_1 ~S DR_2 The two paths are switched on and off to realize quantization in one of the left and right paths and multiplication and accumulation calculation in the other path, and the result of each round of multiplication and accumulation calculation is reflected to DL or DR.

[0112] Specifically, refer to ① to perform cumulative calculations of M multiplications in each round; continuous multiplication-accumulation calculations require that different paths be used for the two previous and subsequent multiplication-accumulation calculations: in the Yth round of calculations, the left path is selected for calculation, and DR quantization is performed on ; in the Y+1th round of calculations, the right path is selected for calculation, and DL quantization is performed on ; Y represents a positive integer.

[0113] In this way, similar to a single symbol transfer multiplication unit circuit, the left and right paths of the multiplication and accumulation calculation circuit also form a pipeline operation: when the left path is calculating, the right path is quantizing; when the right path is calculating, the left path is quantizing; this saves the time waiting for quantization and improves work efficiency.

[0114] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0115] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A sign transfer multiplication unit circuit, characterized in that: Used to perform multiplication calculation of 2-bit analog input Input and 2-bit signed weight value Weight; It includes: The symbol storage unit includes: a symbol storage subunit, a bit line BL sign , bit line BLB sign 、Inverter INV sign ; The symbol storage sub-unit includes: 1 column of N 6T-SRAM cells, N ≥ 1; each 6T-SRAM cell stores a 1-bit sign bit of Weight; the symbol storage sub-unit shares BL sign ,BLB sign ;INV sign The input terminal of BL sign ; The weight storage unit includes: a weight storage subunit, a bit line BL, and a bit line BLB; the weight storage subunit includes: a column of N 6T-SRAM cells 2; each 6T-SRAM cell 2 stores a 1-bit weight value of Weight; the weight storage subunit shares BL and BLB; Shutdown control unit, which is used to control BL sign ,BLB sign , BL, BLB are turned on and off to switch the entire circuit between read-write mode and multiplication mode; The in-memory computing unit includes: an input subunit, a control subunit, a left capacitor unit, a right capacitor unit, and a charging bit line Bottom; the input subunit and INV sign The output terminals, BL and BLB are connected to each other, and are used to input Input and Weight in the multiplication mode, and selectively charge Bottom according to Input and Weight; the left capacitor unit includes: 1 capacitor Cap_L and an output bit line DL, and the upper plate of Cap_L is connected to DL; the right capacitor unit includes: 1 capacitor Cap_R and an output bit line DR, and the upper plate of Cap_R is connected to DR; the control sub-unit is used to control the lower plates of Cap_L and Cap_R to be alternately connected to Bottom, so as to realize continuous multiplication calculation, and store the multiplication results in the lower plates of the corresponding capacitors.

2. A sign transfer multiplication unit circuit according to claim 1, characterized in that: The input sub-section includes: input bit line Sign, input bit line VINN, reference bit line VCM, input bit line VINP, 2 NMOS tubes N1-N2, and 3 PMOS tubes P1-P3; Sign and INV sign The output terminal connection of The gate of N1 is connected to BL, and the drain is connected to VINP; The gate of N2 is connected to Sign, the drain is connected to the source of N1, and the source is connected to Bottom; The gate of P1 is connected to Sign, and the drain is connected to VINN; The gate of P2 is connected to BLB, the drain is connected to the source of P1, and the source is connected to Bottom; The gate of P3 is connected to BL, the drain is connected to VCM, and the source is connected to Bottom.

3. A sign transfer multiplication unit circuit according to claim 2, characterized in that: If Input is "00", VINP input is 3*VDD / 6, VINN input is 3*VDD / 6, and VCM input is 3*VDD / 6; If Input is "01", VINP input is 2*VDD / 6, VINN input is 4*VDD / 6, and VCM input is 3*VDD / 6; If Input is "10", VINP input is VDD / 6, VINN input is 5*VDD / 6, and VCM input is 3*VDD / 6; If Input is "11", VINP inputs VSS, VINN inputs VDD, and VCM inputs 3*VDD / 6; Among them, VSS=0*VDD / 6, which represents the minimum voltage; VDD represents the maximum voltage.

4. A sign transfer multiplication unit circuit according to claim 2, characterized in that: The shutdown control unit includes: 2 weight switches S9~S 10 , 2 symbol switches S 13 ~S 14 ; S9 is arranged on BL and is located on one side of the weight storage sub-unit; S 10 It is set on the BLB and located on one side of the weight storage subunit; S 13 Set up in BL sign On the side of the symbol storage sub-section; S 14 Set up in BLB sign On the side of the symbol storage sub-section; INV sign With BL sign The connection end is located at S 13 , between weight storage sub-sections; The connection end of N1 and BL is located between S9 and the weight storage subsection; The connection between P2 and BLB is located at S 10 , between weight storage sub-sections; Among them, S9~S 10 , S 13 ~S 14 The state always remains the same; When S9~S 10 , S 13 ~S 14 When off, BL sign ,BLB sign , BL, and BLB are all disconnected, and the entire circuit enters the multiplication mode; When S9~S 10 , S 13 ~S 14 When turned on, BL sign ,BLB sign , BL, and BLB are all turned on, and the entire circuit enters the read-write mode.

5. A sign transfer multiplication unit circuit according to claim 4, characterized in that: In the multiplication mode, when performing a multiplication calculation, a certain 6T-SRAM unit 1 of the symbol storage sub-unit and a certain 6T-SRAM unit 2 of the weight storage sub-unit are opened; If the 6T-SRAM cell stores "0", it means that the 1-bit sign bit is positive; if the 6T-SRAM cell stores "1", it means that the 1-bit sign bit is negative; If the 6T-SRAM cell 2 stores "0", it means that the 1-bit weight value is 0; if the 6T-SRAM cell 2 stores "1", it means that the 1-bit weight value is 1; When the 1-bit sign bit is positive and the 1-bit weight value is 0, INV sign Output 1 to Sign, P1 is turned off, N2 is turned on; BL is 0, BLB is 1, N1 and P2 are turned off, P3 is turned on; VINN and VINP are disconnected from Bottom, VCM is connected to Bottom, and the voltage of VCM is charged to Bottom; When the 1-bit sign bit is negative and the 1-bit weight value is 0, INV sign Output 0 to Sign, P1 is turned on, N2 is turned off; BL is 0, BLB is 1, N1 and P2 are turned off, P3 is turned on; VINN and VINP are disconnected from Bottom, VCM is connected to Bottom, and the voltage of VCM is charged to Bottom; When the 1-bit sign bit is positive and the 1-bit weight value is 1, INV sign Output 1 to Sign, P1 is turned off, N2 is turned on; BL is 1, BLB is 0, N1 and P2 are turned on, P3 is turned off; VINN, VCM and Bottom are disconnected, VINP is connected to Bottom, and the voltage of VINP is charged to Bottom; When the 1-bit sign bit is negative and the 1-bit weight value is 1, INV sign Output 0 to Sign, P1 is turned on, N2 is turned off; BL is 1, BLB is 0, N1 and P2 are turned on, P3 is turned off; VINP, VCM and Bottom are disconnected, VINN is connected to Bottom, and the voltage of VINN is charged to Bottom.

6. A sign transfer multiplication unit circuit according to claim 4, characterized in that: The control sub-unit includes: left local bit line SL, right local bit line SR, global bit line WVCM, 4 switches S1~S4, 2 left switches S DL_1 ~S DL_2 , 2 right switches S DR_1 ~S DR_2 ; The left end of Bottom is connected to the lower plate of Cap_L through S1, and the right end is connected to the lower plate of Cap_R through S2; WVCM is connected to Bottom through S3; the connection end between S3 and Bottom is located between S1 and Cap_L; WVCM is connected to Bottom through S4; the connection end between S4 and Bottom is located between S2 and Cap_R; The upper plate of Cap_L is connected through S DL_1 Connected to WVCM; the upper plate of Cap_L is connected to WVCM through S DL_2 Connecting with quantization circuit; The upper plate of Cap_R is connected through S DR_1 Connected to WVCM; the upper plate of Cap_R is connected to WVCM through S DR_2 Connecting with quantization circuit; Among them, the states of S1 and S4 always remain the same; the states of S2 and S3 always remain the same; the states of S1 and S2 are always opposite; DL_1 , S DR_2 The state always remains the same; S DR_1 , S DL_2 The state always remains the same; S DL_1 , S DL_2 The state is always opposite; In multiplication mode, if continuous multiplication calculation is performed, control S DL_1 ~S DL_2 , S DR_1 ~S DR_2 The two paths are switched on and off to realize quantization in one of the left and right paths and multiplication in the other path, and the result of each multiplication is reflected in DL or DR.

7. A symbol transfer multiplication unit module, characterized in that: It adopts the layout of the sign transfer multiplication unit circuit as described in any one of claims 1-6.

8. A multiplication-accumulation calculation circuit, characterized in that: It is used to perform multiplication and accumulation calculations on the 2-bit analog input Input and the 2-bit signed weight value Weight; It includes: The multiplication and accumulation calculation unit comprises: a column of M sign transfer multiplication unit circuits as claimed in claim 6; the M sign transfer multiplication unit circuits share BL sign ,BLB sign ,BL,BLB,DL,DR,S DL_1 , S DL_2 , S DR_1 , S DR_2 , SL, SR, WVCM; Among them, S DL_1 , S DL_2 Located on both sides of the multiplication and accumulation calculation unit; S DR_1 , S DR_2 Located on both sides of the multiplication and accumulation calculation unit; S DL_1 , S DR_1 Located on the same side; S DL_2 , S DR_2 Located on the same side.

9. The multiplication-accumulation calculation circuit according to claim 8, characterized in that: If continuous multiplication and accumulation calculations are performed, control S DL_1 ~S DL_2 , S DR_1 ~S DR_2 The two paths are switched on and off to realize quantization in one of the left and right paths and multiplication and accumulation calculation in the other path, and the result of each round of multiplication and accumulation calculation is reflected to DL or DR.

10. A multiplication and accumulation calculation module, characterized in that: It adopts the layout of the multiplication and accumulation calculation circuit as claimed in claim 9.

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