Double BIOS switching system for mainboard

Abstract

The invention discloses a double BIOS switching system for a mainboard, which comprises a first BIOS module, a second BIOS module, a control module, a switch module, a CPU module and a BMC management module, and is characterized in that the CPU module sends a signal for data interaction with the first BIOS module or the second BIOS module to the control module, the BMC management module sends a GPIO signal to the control module, and the control module sends the GPIO signal to the switch module; the BMC management module performs data interaction with the first BIOS module or the second BIOS module to update BIOS firmware online, and the control module controls the switch module to switch to an access channel and access data of the first BIOS module or the second BIOS module so as to realize data interaction between the CPU module and the first BIOS module or the second BIOS module. According to the invention, the switching of the double BIOS modules can be realized, so that the CPU module is matched with different functions of the double BIOS modules, and the CPU module can be upgraded on the original mainboard.

Description

Technical Field

[0001] The present invention relates to the technical field of mainboard BIOS, and in particular to a dual BIOS switching system for a mainboard. Background Art

[0002] BIOS, or "Basic Input Output System", is a set of programs fixed on a ROM chip on the computer motherboard. It stores the most important basic input and output programs of the computer, the self-test program after power-on, and the system self-starting program. It can read and write specific information of system settings from CMOS. Its main function is to provide the most basic and direct hardware settings and control for the computer motherboard. There are two independent BIOS modules on the existing motherboard. One is the main BIOS, which is responsible for normal system startup and configuration; the other is the backup BIOS, which can automatically take over control when there is a problem with the main BIOS to ensure that the motherboard can continue to work normally, but it has shortcomings.

[0003] The existing motherboards equipped with dual BIOS modules need to be specially customized for the single-channel or multi-channel CPU modules that control the dual BIOS modules during design, which not only limits the effective use of R&D resources, but also causes inconvenience during upgrades. Whenever a technology upgrade is required, the motherboard must be redesigned and developed, and users often have to replace the motherboard as a whole, which increases the cost of use. In addition, the switching mechanism of the dual BIOS modules of the existing motherboards equipped with dual BIOS modules is relatively cumbersome, which affects the user's operation. Summary of the invention

[0004] The purpose of the present invention is to provide a dual BIOS switching system for a mainboard, wherein the switching mechanism of the dual BIOS module is more flexible and convenient, and the CPU module controlling the dual BIOS module can be updated on the basis of the original mainboard.

[0005] To achieve the above object, the solution of the present invention is: a dual BIOS switching system for a motherboard, the system comprising: The first BIOS module is used to run the first BIOS system after the mainboard is powered on; The second BIOS module is used to run the second BIOS system after the mainboard is powered on; A control module connected to the switch module, the switch module connected to the first BIOS module and the second BIOS module, the control module is used to control the switch module to switch the access channel and access data of the first BIOS module and the second BIOS module; A CPU module, connected to the control module and the switch module, and used for data exchange with the first BIOS module or the second BIOS module through the control module; A BMC management module, connected to the control module, for updating the BIOS firmware of the first BIOS module or the second BIOS module online, or for cooperating with the CPU module to perform data exchange with the first BIOS module or the second BIOS module; The CPU module sends a signal for data interaction with the first BIOS module or the second BIOS module to the control module, the BMC management module sends a GPIO signal to the control module, the BMC management module interacts with the first BIOS module or the second BIOS module to update the BIOS firmware online, and the control module controls the switch module to switch to the access channel and access data of the first BIOS module or the second BIOS module to realize data interaction between the CPU module and the first BIOS module or between the CPU module and the second BIOS module.

[0006] In a preferred embodiment, the switch module includes a primary switch and a secondary switch, the two primary switches are respectively connected to the first BIOS module and the second BIOS module, the two primary switches are respectively connected to the control module, and the control module switches the access channel of the first BIOS module and the second BIOS module through the primary switch; the two secondary switches are respectively connected to the two primary switches, the two secondary switches are respectively connected to the control module and the CPU module, and the CPU module switches the access data of the first BIOS module and the second BIOS module through the control module and the secondary switch.

[0007] In a preferred embodiment, the control module is an FPGA chip, the first-level switch is provided with a first-level control pin S0 and a pin S1, a first-level switching pin COM, a pin NC, a pin N0 and a pin N1, the pin COM of the two first-level switches are respectively connected to the first BIOS module and the second BIOS module, the pin COM of the two first-level switches are respectively connected to the pin NC, the pin N0 and the pin N1, the pin S0 and the pin S1 of the two second-level switches are respectively connected to the FPGA chip, and the FPGA chip controls the pin COM connected to the first BIOS module and the second BIOS module through the pin S0 and the pin S1 to select the turning on pin NC, the pin N0 or the pin N1.

[0008] In a preferred embodiment, the secondary switch is provided with a secondary control pin IN, a secondary switching pin A, a pin B and a pin Y, the pin NC of the two primary switches is connected to the pin A of the two secondary switches to form an access channel A, the pin N0 of the two primary switches is connected to the pin B of the two secondary switches to form an access channel B, the pin N1 of the two primary switches is connected to the FPGA chip to form a feedback channel, the pin Y of the two secondary switches is respectively connected to the CPU module, the pin IN of the two secondary switches is respectively connected to the FPGA chip, and the FPGA chip controls the pin Y through the pin IN to select to turn on the access channel A or the access channel B.

[0009] In a preferred embodiment, the CPU module is provided with data control pins P0, P1 and P2 respectively connected to the FPGA chip. The CPU module sends levels of different states to the FPCA chip through pins P0, P1 and P2 to select data access to the first BIOS module or the second BIOS module.

[0010] In a preferred embodiment, when the pins P0, P1 and P2 are all at high levels, the CPU module accesses data to the first BIOS module; and when the pins P0, P1 and P2 are all at low levels, the CPU module accesses data to the second BIOS module.

[0011] In a preferred embodiment, when the FPGA chip sends a low level to pin IN of the secondary switch, access channel A is turned on, access channel B is turned off, and the CPU module accesses data to the first BIOS module; when the FPGA chip sends a high level to pin IN of the secondary switch, access channel A is turned off, access channel B is turned on, and the CPU module accesses data to the second BIOS module. At this time, the system is in dual BIOS cross-switching mode.

[0012] In a preferred embodiment, when the FPGA chip always sends a low level to the pin IN of the secondary switch, the access channel A is turned on, the access channel B is turned off, and the CPU module accesses data to the first BIOS module. At this time, the system is in the dual BIOS normalization mode.

[0013] In a preferred solution, the BMC management module updates the BIOS firmware of the first BIOS module and the second BIOS module or cooperates with the CPU module to perform data exchange between the first BIOS module and the second BIOS module by sending high and low levels of different states to the control module.

[0014] The preferred solution also includes a security verification module, which is connected to the control module and is provided with a PCIE slot interface for an external PCIE card to measure and verify whether the BIOS firmware information of the first BIOS module and the second BIOS module is consistent with the previously bound device information content when the mainboard is powered on.

[0015] After adopting the above scheme, the beneficial effect of the present invention is that the control module of the present invention controls the switch module to switch the access channel and access data of the first BIOS module and the second BIOS module by detecting the signal sent by the CPU module for data interaction with the first BIOS module or the second BIOS module, thereby realizing the switching of the dual BIOS modules, so as to achieve the purpose of matching the CPU module with the different functional applications of the dual BIOS modules. The operation is convenient, the CPU module can be updated on the basis of the original motherboard, the use is flexible, and it is beneficial to improve the performance of the motherboard and save development costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a system flow chart of an embodiment of the present invention; Figure 2 is a system flow chart of a dual BIOS cross switching mode in an embodiment of the present invention; Figure 3 It is a system flow chart of the dual BIOS normalization mode in an embodiment of the present invention.

[0017] Description of labels: 1. First BIOS module; 2. Second BIOS module; 3. Control module; 31. FPGA chip; 4. Switch module; 41. Primary switch; 42. Secondary switch; 5. CPU module; 6. BMC management module; 7. Security verification module. DETAILED DESCRIPTION

[0018] The present invention will now be further described with reference to the accompanying drawings and specific implementation methods.

[0019] This embodiment provides a dual BIOS switching system for a motherboard. Figure 1 As shown, the system includes: a first BIOS module 1, which is used to run a first BIOS system after the mainboard is powered on; The second BIOS module 2 is used to run the second BIOS system after the mainboard is powered on; the control module 3 is connected to the switch module 4, and the switch module 4 is connected to the first BIOS module 1 and the second BIOS module 2. The control module 3 is used to control the switch module 4 to switch the access channel and access data between the first BIOS module 1 and the second BIOS module 2; A CPU module 5, connected to the control module 3 and the switch module 4, and configured to perform data exchange with the first BIOS module 1 or the second BIOS module 2 through the control module 3; A BMC management module 6, connected to the control module 3, for updating the BIOS firmware of the first BIOS module 1 or the second BIOS module 2 online, or for cooperating with the CPU module 5 to perform data exchange with the first BIOS module 1 or the second BIOS module 2; The CPU module 5 sends a signal for data interaction with the first BIOS module 1 or the second BIOS module 2 to the control module 3, the BMC management module 6 sends a GPIO signal to the control module 3, the BMC management module 6 interacts with the first BIOS module 1 or the second BIOS module 2 to update the BIOS firmware online, and the control module 3 controls the switch module 4 to switch to the access channel and access data of the first BIOS module 1 or the second BIOS module 2 to realize data interaction between the CPU module 5 and the first BIOS module 1 or between the CPU module 5 and the second BIOS module 2.

[0020] The motherboard equipped with this system can be used in the fields of servers, industrial control equipment or embedded devices. In this embodiment, the control module 3 on the motherboard is used to manage the basic functions of the CPU module 5 such as power on and off, reset, signal conversion, etc., and the BMC management module 6 manages the control module 3 on the motherboard. When this system is applied on a server, the BMC management module 6 is also used to manage the entire motherboard, such as the display output of the server motherboard, monitoring the voltage of the server motherboard, detecting the temperature and controlling the fan, detecting the total system power consumption of the total power supply PSU module, remote management of the server, etc. The BMC management module 6 of this embodiment includes components such as the BMC main control IC, FLASH firmware, video memory, EEPROM, CPLD chip, I / O interface, etc. This is a prior art and will not be described in detail.

[0021] In this embodiment, the user can adjust the number of CPUs of the CPU module 5 according to actual needs. In this example, two CPUs are set, but the present invention is not limited thereto. By setting two CPUs, the performance of the motherboard can be effectively improved to meet different usage requirements.

[0022] When the CPU module 5 needs to interact with the first BIOS module 1 or the second BIOS module 2 for data, the CPU module 5 will send a control signal to the control module 3, and the control module 3 will control the switch module 4 to switch to the access channel of the first BIOS module 1 or the second BIOS module 2 for the CPU module 5 to interact with data and the access data of the first BIOS module 1 or the second BIOS module 2 for the CPU module 5 to interact with data, thereby realizing the switching of the dual BIOS modules, so as to achieve the purpose of matching the CPU module 5 with different functional applications of the dual BIOS modules, and the operation is convenient.

[0023] Since the first BIOS module 1, the second BIOS module 2, the control module 3 and the switch module 4 for controlling the switching of the BIOS modules in this embodiment are designed in a supporting manner, when the CPU module 5 needs to be updated, the CPU module 5 can be adjusted based on the original motherboard. For example, a single-channel CPU module 5 only needs to be set with one CPU, while a multi-channel CPU module 5 needs to be set with multiple CPUs. The switch module 4 and the control module 3 can be adaptively adjusted in terms of interface. This is flexible to use and helps save development costs.

[0024] like Figure 1 As shown, the switch module 4 includes a primary switch 41 and a secondary switch 42. The two primary switches 41 are respectively connected to the first BIOS module 1 and the second BIOS module 2, and the two primary switches 41 are respectively connected to the control module 3. The control module 3 switches the access channels of the first BIOS module 1 and the second BIOS module 2 through the primary switch 41; the two secondary switches 42 are respectively connected to the two primary switches 41, and the two secondary switches 42 are respectively connected to the control module 3 and the CPU module 5. The CPU module 5 switches the access data of the first BIOS module 1 and the second BIOS module 2 through the control module 3 and the secondary switch 42.

[0025] The switch module 4 of this embodiment is provided with a primary switch 41 and a secondary switch 42. Specifically, the primary switch 41 is used to control the data of the first BIOS module 1 and the second BIOS module 2 to be accessed by the CPU module 5 or the control module 3, and the secondary switch 42 is used to control the CPU module 5 to access the data of the first BIOS module 1 or the second BIOS module 2. Both the primary switch 41 and the secondary switch 42 are dispatched by the control module 3, and the operation is convenient.

[0026] like Figure 1 As shown, the control module 3 is an FPGA chip 31, and the first-level switch 41 is provided with a first-level control pin S0, a pin S1, a first-level switching pin COM, a pin NC, a pin N0 and a pin N1. The pin COM of the two first-level switches 41 is respectively connected to the first BIOS module 1 and the second BIOS module 2, the pin COM of the two first-level switches 41 is respectively connected to the pin NC, the pin N0 and the pin N1, the pin S0 and the pin S1 of the two second-level switches 42 are respectively connected to the FPGA chip 31, and the FPGA chip 31 controls the pin COM connected to the first BIOS module 1 and the second BIOS module 2 through the pin S0 and the pin S1 to select the turning on pin NC, the pin N0 or the pin N1.

[0027] The control module 3 of this embodiment adopts FPGA chip 31, but is not limited thereto, and has high flexibility and reconfigurability, and can provide efficient processing performance. The specific control of the primary switch 41 by the FPGA chip 31 is shown in Table 1.

[0028] Table 1. First-level switch channel switching truth table

[0029] When the FPGA chip 31 sends a low-level signal to pin S0 and pin S1 of the primary switch 41, pin COM selects to turn on pin NC; when the FPGA chip 31 sends a high-level signal to pin S0 of the primary switch 41 and a low-level signal to pin S1, pin COM selects to turn on pin N0; when the FPGA chip 31 sends a low-level signal to pin S0 of the primary switch 41 and a high-level signal to pin S1, pin COM selects to turn on pin N1, which is convenient to operate.

[0030] like Figure 1 As shown, the secondary switch 42 is provided with a secondary control pin IN, a secondary switching pin A, a pin B and a pin Y, the pin NC of the two primary switches 41 is connected to the pin A of the two secondary switches 42 to form an access channel A, the pin N0 of the two primary switches 41 is connected to the pin B of the two secondary switches 42 to form an access channel B, the pin N1 of the two primary switches 41 is connected to the FPGA chip 31 to form a feedback channel, the pin Y of the two secondary switches 42 is respectively connected to the CPU module 5, the pin IN of the two secondary switches 42 is respectively connected to the FPGA chip 31, and the FPGA chip 31 controls the pin Y through the pin IN to select to turn on the access channel A or the access channel B.

[0031] In this embodiment, the specific control of the secondary switch 42 by the FPGA chip 31 is shown in Table 2.

[0032] Table 2 Secondary switch channel switching truth table

[0033] When the FPGA chip 31 sends a low-level signal to the pin of the secondary switch 42, pin Y is connected to pin A, thereby opening the access channel A between the primary switch 41 and the secondary switch 42; when the FPGA chip 31 sends a high-level signal to the pin of the secondary switch 42, pin Y is connected to pin B, thereby opening the access channel B between the primary switch 41 and the secondary switch 42. This embodiment controls the switching of the primary switch 41 and the secondary switch 42 through the levels of different states, and the operation is simple. In other embodiments, the control level can also be adjusted.

[0034] like Figure 1As shown, the CPU module 5 of this embodiment is provided with data control pins P0, P1 and P2 respectively connected to the FPGA chip 31. The CPU module 5 sends levels of different states to the FPCA chip through pins P0, P1 and P2 to select data access to the first BIOS module 1 or the second BIOS module 2. The operation is simple and the use is flexible.

[0035] Table 3 CPU module detects BIOS status truth table through FPGA chip

[0036] Specifically, as shown in Table 3, when the pin P0, the pin P1 and the pin P2 are all at high levels, the CPU module 5 accesses data to the first BIOS module 1, and when the pin P0, the pin P1 and the pin P2 are all at low levels, the CPU module 5 accesses data to the second BIOS module 2. The user can adjust the level status to meet different usage requirements, and the operation is convenient.

[0037] Table 4 Truth table of CPU module reading BIOS firmware in dual BIOS cross switching mode

[0038] like Figure 2 As shown in Table 4, when the FPGA chip 31 sends a low level to pin IN of the secondary switch 42, access channel A is turned on, access channel B is turned off, and the CPU module 5 accesses data to the first BIOS module 1; when the FPGA chip 31 sends a high level to pin IN of the secondary switch 42, access channel A is turned off, access channel B is turned on, and the CPU module 5 accesses data to the second BIOS module 2. At this time, the system is in dual BIOS cross-switching mode.

[0039] When the present embodiment is in the dual BIOS cross switching mode, Figure 1 , Figure 2 As shown in Table 4, through the primary switch 41 being matched with the secondary switch 42, when the CPU module 5 needs to access the data of the first BIOS module 1, the FPGA chip 31 sends a low-level signal to both the pin S0 and the pin S1 of the primary switch 41, and at this time, the pin COM selects to turn on the pin NC, thereby turning on the access channel A of the first BIOS module 1 and the second BIOS module 2. The FPGA chip 31 sends a low-level signal to the pin IN of the secondary switch 42, and at this time, the pin Y is turned on with the pin A, thereby turning on the access channel A of the first BIOS module 1 and closing the access channel B of the second BIOS module 2, thereby enabling the CPU module 5 to access the data of the first BIOS module 1.

[0040] Similarly, when the CPU module 5 needs to access the data of the second BIOS module 2, the FPGA chip 31 sends a high-level signal to the pin S0 of the primary switch 41, and sends a low-level signal to the pin S1. At this time, the pin COM selects to turn on the pin N0, thereby turning on the access channel B of the first BIOS module 1 and the second BIOS module 2. At the same time, the FPGA chip 31 sends a high-level signal to the pin IN of the secondary switch 42. At this time, the pin Y is connected to the pin B, thereby turning on the access channel B of the second BIOS module 2, and closing the access channel A of the first BIOS module 1, so that the CPU module 5 can access the data of the second BIOS module 2.

[0041] like Figure 3 As shown in Table 5, when the FPGA chip 31 always sends a low level to the pin IN of the secondary switch 42, the access channel A is turned on, the access channel B is turned off, and the CPU module 5 accesses data to the first BIOS module 1. At this time, the system is in the dual BIOS normalization mode.

[0042] Table 5 Truth table of CPU module reading BIOS firmware in dual BIOS normalization mode

[0043] When the present embodiment is in the dual BIOS normalization mode, Figure 1 , Figure 3 As shown in Table 5, pins P0, P1 and P2 of the CPU module 5 send a high level to the FPGA chip 31 by default, and the FPGA chip 31 always sends a low level signal to pin IN of the secondary switch 42. The access channel A of the first BIOS module 1 is turned on, and the access channel B is closed at the same time, so that the CPU module 5 accesses the data of the first BIOS module 1 by default, and the second BIOS module 2 is in an inoperative state. Only one BIOS is required to realize the normal operation of the motherboard, which is beneficial to saving power consumption.

[0044] Furthermore, in this embodiment, the BMC management module 6 updates the BIOS firmware of the first BIOS module 1 and the second BIOS module 2 or cooperates with the CPU module 5 to perform data exchange between the first BIOS module 1 and the second BIOS module 2 by sending high and low levels of different states to the control module 3.

[0045] Table 6 Truth table of BMC management module used to switch and update BIOS firmware or CPU module to read and write BIOS firmware normally

[0046] Specifically, as shown in Table 6, the BMC management module 6 is provided with a pin BIOS0_SELT and a pin BIOS1_SELT, and the pin BIOS0_SELT and the pin BIOS1_SELT are respectively connected to the corresponding pins of the FPGA chip 31. When the pin BIOS0_SELT is at a low level and the pin BIOS1_SELT is at a high level, the BIOS firmware of the first BIOS module 1 is updated; when the pin BIOS0_SELT is at a high level and the pin BIOS1_SELT is at a low level, the BIOS firmware of the second BIOS module 2 is updated; when the pin BIOS0_SELT and the pin BIOS1_SELT are both at a high level, the CPU module 5 exchanges data with the first BIOS module 1 and the second BIOS module 2.

[0047] like Figure 1 As shown, this embodiment also includes a security verification module 7, which is connected to the control module 3. The security verification module 7 is provided with a PCIE slot interface for an external PCIE card, so as to measure and verify whether the BIOS firmware information of the first BIOS module 1 and the second BIOS module 2 is consistent with the previously bound device information content when the mainboard is powered on, so as to further ensure the safety during use.

[0048] In this embodiment, the data transmission between the first BIOS module 1 and the second BIOS module 2 and the primary switch 41 adopts the QSPI protocol, and the data transmission between the secondary switch 42 and the CPU module 5 adopts the QSPI protocol, which has a higher data transmission rate and improves the communication efficiency. The feedback channel between the primary switch 41 and the FPGA chip 31 adopts the SPI protocol, and the BMC management module 6 and the security verification module 7 and the FPGA chip 31 adopt the SPI protocol, which has the characteristics of simplicity and flexibility. The transmission protocol can also be adjusted in other embodiments.

[0049] The working principle of the present invention is as follows: When the CPU module 5 needs to upgrade the BIOS firmware of the first BIOS module 1 and the second BIOS module 2 or exchange data between the first BIOS module 1 and the second BIOS module 2, the pins BIOS0_SELT and BIOS1_SELT of the BMC management module 6 send levels of different states to the FPGA chip 31 respectively.

[0050] When the pin BIOS0_SELT is at a low level and the pin BIOS1_SELT is at a high level, the BIOS firmware of the first BIOS module 1 is updated; when the pin BIOS0_SELT is at a high level and the pin BIOS1_SELT is at a low level, the BIOS firmware of the second BIOS module 2 is updated; when the pin BIOS0_SELT and the pin BIOS1_SELT are both at high levels, the CPU module 5 exchanges data with the first BIOS module 1 and the second BIOS module 2.

[0051] When the CPU module 5 needs to access the data of the first BIOS module 1, the FPGA chip 31 sends a low-level signal to both pin S0 and pin S1 of the primary switch 41. At this time, pin COM selects to turn on pin NC, thereby turning on access channel A of the first BIOS module 1 and the second BIOS module 2. At the same time, the FPGA chip 31 sends a low-level signal to pin IN of the secondary switch 42. At this time, pin Y is connected to pin A, thereby turning on access channel A of the first BIOS module 1 and closing access channel B of the second BIOS module 2, thereby enabling the CPU module 5 to access the data of the first BIOS module 1. At this time, the system is in dual BIOS cross-switching mode.

[0052] When the CPU module 5 needs to access the data of the second BIOS module 2, the FPGA chip 31 sends a high-level signal to the pin S0 of the first-level switch 41, and sends a low-level signal to the pin S1. At this time, the pin COM selects to turn on the pin N0, thereby turning on the access channel B of the first BIOS module 1 and the second BIOS module 2. At the same time, the FPGA chip 31 sends a high-level signal to the pin IN of the second-level switch 42. At this time, the pin Y is connected to the pin B, thereby turning on the access channel B of the second BIOS module 2, and closing the access channel A of the first BIOS module 1, so that the CPU module 5 can access the data of the second BIOS module 2. At this time, the system is in the dual BIOS normalization mode.

[0053] The above description is only a preferred embodiment of the present invention and is not a limitation on the design of this case. Any equivalent changes made based on the design key of this case shall fall within the protection scope of this case.

Claims

1. A dual BIOS switching system for a motherboard, characterized in that: The system comprises: The first BIOS module is used to run the first BIOS system after the mainboard is powered on; The second BIOS module is used to run the second BIOS system after the mainboard is powered on; A control module connected to the switch module, the switch module connected to the first BIOS module and the second BIOS module, the control module is used to control the switch module to switch the access channel and access data of the first BIOS module and the second BIOS module; A CPU module, connected to the control module and the switch module, and used for data exchange with the first BIOS module or the second BIOS module through the control module; A BMC management module, connected to the control module, for updating the BIOS firmware of the first BIOS module or the second BIOS module online, or for cooperating with the CPU module to perform data exchange with the first BIOS module or the second BIOS module; The CPU module sends a signal for data interaction with the first BIOS module or the second BIOS module to the control module, the BMC management module sends a GPIO signal to the control module, the BMC management module interacts with the first BIOS module or the second BIOS module to update the BIOS firmware online, and the control module controls the switch module to switch to the access channel and access data of the first BIOS module or the second BIOS module to realize data interaction between the CPU module and the first BIOS module or between the CPU module and the second BIOS module.

2. A dual BIOS switching system for a motherboard as claimed in claim 1, characterized in that: The switch module includes a primary switch and a secondary switch, the two primary switches are respectively connected to the first BIOS module and the second BIOS module, the two primary switches are respectively connected to the control module, and the control module switches the access channel of the first BIOS module and the second BIOS module through the primary switch; the two secondary switches are respectively connected to the two primary switches, the two secondary switches are respectively connected to the control module and the CPU module, and the CPU module switches the access data of the first BIOS module and the second BIOS module through the control module and the secondary switch.

3. A dual BIOS switching system for a motherboard as claimed in claim 2, characterized in that: The control module is an FPGA chip, and the first-level switch is provided with a first-level control pin S0 and a pin S1, a first-level switching pin COM, a pin NC, a pin N0 and a pin N1, the pin COM of the two first-level switches are respectively connected to the first BIOS module and the second BIOS module, the pin COM of the two first-level switches are respectively connected to the pin NC, the pin N0 and the pin N1, the pin S0 and the pin S1 of the two second-level switches are respectively connected to the FPGA chip, and the FPGA chip controls the pin COM connected to the first BIOS module and the second BIOS module through the pin S0 and the pin S1 to select the turning on pin NC, the pin N0 or the pin N1.

4. A dual BIOS switching system for a motherboard as claimed in claim 3, characterized in that: The secondary switch is provided with a secondary control pin IN, a secondary switching pin A, a pin B and a pin Y. The pin NC of the two primary switches is connected to the pin A of the two secondary switches to form an access channel A. The pin N0 of the two primary switches is connected to the pin B of the two secondary switches to form an access channel B. The pin N1 of the two primary switches is connected to the FPGA chip to form a feedback channel. The pin Y of the two secondary switches is respectively connected to the CPU module. The pin IN of the two secondary switches is respectively connected to the FPGA chip. The FPGA chip controls the pin Y through the pin IN to select to turn on the access channel A or the access channel B.

5. A dual BIOS switching system for a motherboard as claimed in claim 4, characterized in that: The CPU module is provided with data control pins P0, P1 and P2 respectively connected to the FPGA chip. The CPU module sends different state levels to the FPCA chip through pins P0, P1 and P2 to select data access to the first BIOS module or the second BIOS module.

6. A dual BIOS switching system for a motherboard as claimed in claim 5, characterized in that: When the pin P0, the pin P1 and the pin P2 are all at high levels, the CPU module accesses data to the first BIOS module; when the pin P0, the pin P1 and the pin P2 are all at low levels, the CPU module accesses data to the second BIOS module.

7. A dual BIOS switching system for a motherboard as claimed in claim 6, characterized in that: When the FPGA chip sends a low level to pin IN of the secondary switch, access channel A is turned on, access channel B is turned off, and the CPU module accesses data to the first BIOS module; when the FPGA chip sends a high level to pin IN of the secondary switch, access channel A is turned off, access channel B is turned on, and the CPU module accesses data to the second BIOS module. At this time, the system is in dual BIOS cross-switching mode.

8. A dual BIOS switching system for a motherboard as claimed in claim 6, characterized in that: When the FPGA chip always sends a low level to the pin IN of the secondary switch, access channel A is turned on, access channel B is turned off, and the CPU module accesses data to the first BIOS module. At this time, the system is in dual BIOS normalization mode.

9. A dual BIOS switching system for a motherboard as claimed in claim 1, characterized in that: The BMC management module updates the BIOS firmware of the first BIOS module and the second BIOS module or cooperates with the CPU module to perform data exchange between the first BIOS module and the second BIOS module by sending high and low levels of different states to the control module.

10. A dual BIOS switching system for a motherboard as claimed in claim 1, characterized in that: It also includes a security verification module, which is connected to the control module. The security verification module is provided with a PCIE slot interface for an external PCIE card to measure and verify whether the BIOS firmware information of the first BIOS module and the second BIOS module is consistent with the previously bound device information content when the mainboard is powered on.

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