Module-level verification method, system, device, medium and program product
Through the modular verification environment integrating the register model, host monitor and other components, the high cost and inefficiency problems caused by over-design of the existing module-level verification environment are solved, and easy to adjust and efficient module-level verification is achieved.
Patent Information
- Application Number
- CN202411694105.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-25
- Publication Date
- 2025-05-23
AI Technical Summary
The existing module-level verification environment has over-design problems, which increases development costs and maintenance difficulties, and is less validated.
By integrating register models, host monitors, slave monitors, reference model components and input/output scoring boards, a scalable and reusable modular verification environment is built to achieve comprehensive verification of the modules to be tested.
It realizes comprehensive verification of the module to be tested, is easy to adjust, is low in cost and has high verification efficiency, reducing the difficulty of development and maintenance.
Smart Images
Figure CN120029831A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of module-level verification technology, and in particular to a module-level verification method, system, device, medium and program product. Background Art
[0002] System-on-Chip (SOC) module-level verification refers to the process of individually verifying each functional module inside the chip during the SOC design process. This is a key step to ensure that each module can correctly implement its intended function before being integrated into the SOC. It mainly focuses on each individual module in the SOC and verifies it before the module is integrated into the SOC. For example, in a SOC that contains a central processing unit (CPU), a graphics processing unit (GPU), and various communication modules, module-level verification will independently verify the CPU module, GPU module, and communication modules (such as USB interface module, Ethernet interface module, etc.).
[0003] At present, the module-level verification environment required for the development of verification environment templates is mainly established through Universal Verification Methodology (UVM) to shorten the verification iteration time. However, the module-level verification environment built using UVM may have the problem of over-design, which increases unnecessary development costs and maintenance difficulties. Summary of the invention
[0004] In order to solve the above technical problems or at least partially solve the above technical problems, the present application provides a module-level verification method, system, equipment, medium and program product, which can build an extensible and reusable module-level verification environment to achieve comprehensive verification of the module to be tested, which is easy to adjust, low cost and high verification efficiency.
[0005] In order to achieve the above purpose, the technical solutions provided by the embodiments of the present application are as follows:
[0006] In a first aspect, the present application provides a module-level verification method, which is applied to a module-level verification system. The method includes:
[0007] Control the register model to drive the operation of the module under test according to the register configuration file; obtain the actual state information of the module under test through the host monitor, and obtain the actual interaction information between the module under test and the slave through the slave monitor; simulate the operation of the module under test through the reference model component to obtain the simulated state information of the module under test and the simulated interaction information between the module under test and the slave; compare the simulated state information with the actual state information through the output scoreboard, and compare the simulated interaction information with the actual interaction information through the input scoreboard; if the simulated state information is consistent with the actual state information and the simulated interaction information is consistent with the actual interaction information, it is determined that the module under test has passed the verification.
[0008] As an optional implementation provided in an embodiment of the present application, before controlling the register model to drive the module to be tested according to the register configuration file, the method also includes: controlling the interrupt service stimulus module to manipulate the register model to configure the module to be tested according to the test case configuration information to drive the module to be tested.
[0009] As an optional implementation provided in an embodiment of the present application, after obtaining the actual status information of the module to be tested through the host monitor, and obtaining the actual interaction information between the module to be tested and the slave through the slave monitor, the method also includes: performing coverage analysis based on the actual status information and the actual interaction information through a coverage component.
[0010] As an optional implementation provided in an embodiment of the present application, the method also includes: obtaining timing information of the module to be tested through an assertion component; determining whether the timing information is correct; and if so, determining that the design of the module to be tested is correct.
[0011] In a second aspect, the present application provides a module-level verification system, the system comprising:
[0012] The top-level module is used to start and manage the test case module and establish the connection between the test case module and the module to be tested;
[0013] Test case module, used to build the verification environment. The test case module includes: register model, interrupt service stimulus module, test case configuration information and environment components;
[0014] Among them, the register model is used to simulate the register behavior of the module under test; the interrupt service stimulus module is used to control the register model to configure the module under test; the environment components include: reference model components, host agent, slave agent, input scoreboard and output scoreboard;
[0015] The reference model component is used to simulate the operation of the module under test, obtain the simulated state information of the module under test, and the simulated interaction information between the module under test and the slave; the host agent is used to obtain the actual state information of the module under test through the host monitor; the slave agent is used to obtain the actual interaction information of the module under test and the slave through the slave monitor; the input scoreboard is used to compare whether the simulated state information is consistent with the actual state information; the output scoreboard is used to compare whether the simulated interaction information is consistent with the actual interaction information.
[0016] As an optional implementation provided in an embodiment of the present application, the environment component also includes a coverage component; wherein the coverage component is used to perform coverage analysis based on actual state information and actual interaction information.
[0017] As an optional implementation provided in an embodiment of the present application, the top-level module is also used to establish a connection between the assertion component and the module to be tested; wherein the assertion component is used to: obtain the timing information of the module to be tested; determine whether the timing information is correct; if so, determine that the design of the module to be tested is correct.
[0018] In a third aspect, the present application provides an electronic device comprising: a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein when the computer program is executed by the processor, the module-level verification method as described in the first aspect or any one of its optional embodiments is implemented.
[0019] In a fourth aspect, the present application provides a computer-readable storage medium, comprising: a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, it implements the module-level verification method as described in the first aspect or any optional embodiment thereof.
[0020] In a fifth aspect, the present application provides a computer program product, including: the computer program product includes a computer program, and when the computer program runs on a computer, the computer implements the module-level verification method as described in the first aspect or any optional embodiment thereof.
[0021] Compared with the prior art, the technical solution provided by the embodiments of the present application has the following advantages:
[0022] The disclosed embodiments provide a module-level verification method, system, device, medium and program product, wherein the method first controls the register model to drive the operation of the module to be tested according to the register configuration file, obtains the actual state information of the module to be tested through the host monitor, and obtains the actual interaction information between the module to be tested and the slave through the slave monitor; simulates the operation of the module to be tested through the reference model component to obtain the simulation state information of the module to be tested and the simulation interaction information between the module to be tested and the slave; then compares the simulation state information and the actual state information through the output-type scoring board to see if they are consistent, and compares the simulation interaction information and the actual interaction information through the input-type scoring board to see if they are consistent; if they are consistent, it is determined that the module to be tested has passed the verification. In this way, the present application integrates the register model, the host monitor, the slave monitor, the reference model component and the input / output scoring board to build an expandable and reusable modular verification environment, so as to realize comprehensive verification of the module to be tested, which is easy to adjust, low in cost and high in verification efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.
[0024] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.
[0025] Figure 1 A schematic diagram of the architecture of a module-level verification system provided in an embodiment of the present application;
[0026] Figure 2 A schematic diagram of a module-level verification method according to an embodiment of the present application;
[0027] Figure 3 A schematic diagram of the structure of an electronic device described in an embodiment of the present application. DETAILED DESCRIPTION
[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the technical terms required to be used in the embodiments or the description of the prior art are briefly introduced below.
[0029] The device under test (DUT) refers to a specific functional module or complete device unit that is specially selected as a test target during the test of electronic circuits, chips, systems, etc. It is the core object of the test system, and testers use various test methods and tools to test and verify its performance, function, reliability and other aspects.
[0030] A directed association, also called an association relationship, is a way to describe the structural relationship between classes. It indicates that there is a connection between one class object and another class object. In a Unified Modeling Language class diagram, an association relationship is usually represented by a solid arrow. If the association is directed, that is, there is a clear owner and owned relationship, then the arrow points from the owner to the owned.
[0031] Unified Modeling Language Class Diagram (UML) is a visualization tool used to describe classes, class attributes, relationships between classes, and class behaviors in a system. It is the most commonly used diagram in UML.
[0032] In order to more clearly understand the above-mentioned purposes, features and advantages of the present application, the scheme of the present application will be further described below. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.
[0033] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only part of the embodiments of the present application, rather than all of the embodiments.
[0034] In order to solve some or all of the technical problems existing in the related art, the embodiment of the present application provides a module-level verification method, system, device, medium and program product, wherein the method first controls the register model to drive the operation of the module to be tested according to the register configuration file, obtains the actual state information of the module to be tested through the host monitor, and obtains the actual interaction information between the module to be tested and the slave through the slave monitor; simulates the operation of the module to be tested through the reference model component to obtain the simulation state information of the module to be tested and the simulation interaction information between the module to be tested and the slave; then compares the simulation state information and the actual state information through the output scoring board to see if they are consistent, and compares the simulation interaction information and the actual interaction information through the input scoring board to see if they are consistent; if they are consistent, it is determined that the module to be tested has passed the verification. In this way, the present application integrates the register model, the host monitor, the slave monitor, the reference model component and the input / output scoring board to build an expandable and reusable modular verification environment, so as to realize comprehensive verification of the module to be tested, which is easy to adjust, low in cost and high in verification efficiency.
[0035] A module-level verification method provided in the embodiment of the present application can be implemented by an electronic device, and the electronic device includes but is not limited to a personal computer, a laptop computer, a tablet computer, a smart phone, etc. The operating system of the electronic device may include Android (Android), a mobile operating system (iOS) developed by Apple, an operating system (Windows) developed by Microsoft Corporation of the United States, etc., and the embodiment of the present application is not limited to this. The electronic device can be run alone to implement the present application, or it can be connected to the network and implement the present application through interactive operations with other computer devices in the network. Among them, the network in which the electronic device is located includes but is not limited to the Internet, a wide area network, a metropolitan area network, a local area network, a virtual private network (Virtual Private Network, VPN) network, etc.
[0036] It should be noted that the protection scope of the module-level verification method described in the embodiment of the present application is not limited to the execution order of the steps listed in this embodiment. All solutions implemented by adding, reducing or replacing steps in the prior art based on the principles of the present application are included in the protection scope of the present application.
[0037] like Figure 1 As shown, Figure 1 This is a schematic diagram of the architecture of a module-level verification system provided in an embodiment of the present application, and the system is used to implement the module-level verification method provided in an embodiment of the present application. The system includes:
[0038] The top-level module (tb_top) is used to start and manage the test case module (case) and establish the connection between the test case module and the module under test DUT;
[0039] The test case module case is used to build a verification environment. The test case module includes: register model (regmodel), interrupt service stimulus module (ISR_sequence), test case configuration information (case_cfg) and environment component (env); the test case module builds a verification environment by instantiating register model, interrupt service stimulus module, test case configuration information and environment components.
[0040] Among them, the register model regmodel is used to simulate the register behavior of the module under test DUT; the register model is generated based on the register configuration file (reg.xlsx).
[0041] The interrupt service stimulus module ISR_sequence is used to control the register model to configure the module to be tested; specifically, the register model is controlled to configure the module to be tested according to the test case configuration information.
[0042] The test case configuration information case_cfg is parsed based on the test case configuration file (case.xlsx) and contains the configuration information required by the test case; the test case configuration file provides the necessary input and parameters for the constructed verification environment.
[0043] The environment component env includes: reference model component (refer_model), host agent (master agent), slave agent (slave agent), input scoreboard (scoreboard ingress) and output scoreboard (scoreboardegress); the environment component is the core of the verification environment built. By integrating the reference model component, host agent, slave agent, input scoreboard and output scoreboard, it controls the collaboration of various modules to achieve functional verification of the module to be tested.
[0044] The reference model component refer_model is used to simulate the operation of the module to be tested, obtain the simulated state information of the module to be tested, and the simulated interaction information between the module to be tested and the slave.
[0045] The host agent is used to obtain the actual status information of the module under test through the host monitor; optionally, the host agent controls the behavior of the module under test by instantiating the scheduling sequencer, host transaction, host interface, transaction driver (apb / axi lite / axi driver) and host monitor to send test stimuli.
[0046] The slave agent is used to obtain the actual interaction information between the module under test and the slave through the slave monitor; optionally, the slave agent simulates the slave connected to the module under test DUT by instantiating the slave monitor (device monitor), slave interface (deviceinterface), slave transaction (device transaction) and receive / transmit driver (tx / rx_driver) modules to receive the test stimulus from the SOC DUT and generate a response.
[0047] The input scoreboard scoreboard ingress is used to compare the simulated status information with the actual status information. If they are inconsistent, an error is recorded.
[0048] The output scoreboard scoreboard egress is used to compare the simulated interaction information with the actual interaction information. If they are inconsistent, an error is recorded.
[0049] The above-mentioned module-level verification system builds a verification environment by integrating various verification components, which can realize intelligent module-level verification, which is conducive to shortening the verification cycle and thus improving verification efficiency. In addition, the modular design facilitates the expansion and maintenance of the system, thereby adapting to diversified verification needs; the test configuration file and register configuration file are user-configurable, making the constructed verification environment easy to adjust and reusable, thereby reducing the verification cost.
[0050] In some embodiments, the environment component env also includes a coverage component (coverage); wherein the coverage component is used to perform coverage analysis based on actual state information and actual interaction information.
[0051] Specifically, the coverage component collects the actual status information monitored by the host monitor and the actual interaction information monitored by the device monitor according to the test case configuration information case_cfg to perform coverage analysis, thereby ensuring the comprehensiveness and completeness of module-level verification.
[0052] In some embodiments, the top-level module tb_top is also used to establish a connection between an assertion component and a module under test DUT; wherein the assertion component is used to: obtain timing information of the module under test; determine whether the timing information is correct; if so, determine that the design of the module under test is correct. The module under test is connected in the top-level module through the assertion component to determine the correctness of the port of the module under test, thereby determining that the design of the module under test is correct.
[0053] Each module in the above module-level verification system can be implemented in whole or in part by software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module.
[0054] A module-level verification method according to an embodiment of the present application is applied to the above system. Figure 2 As shown, Figure 2 This is a flow chart of a module-level verification method according to an embodiment of the present application. The method can be executed by an electronic device, and a module-level verification system is run on the electronic device. The method mainly includes the following steps S201 to S205:
[0055] S201. According to the register configuration file, control the register model to drive the module to be tested to run.
[0056] The register configuration file reg.xlsx is obtained by parsing the Python file. The register configuration file supports user configuration.
[0057] Specifically, when executing step S201, the register configuration file reg.xlsx is obtained to generate a register model regmodel, which is used to simulate the register behavior of the module under test; the register model transmits stimulus to the transaction driver apb / axi lite / axi driver through the scheduling sequencer sequencer of the host agent masteragent to drive the module under test to run.
[0058] In some embodiments, before executing step S201, it also includes: controlling the interrupt service stimulus module ISR_sequence to manipulate the register model regmodel to configure the module to be tested according to the test case configuration information case_cfg. Specifically, the interrupt service stimulus module manipulates the register model based on the test case configuration information to transmit the register configuration transaction to the transaction driver (apb / axilite / axi driver), so that the transaction driver sends a configuration signal to the module to be tested, so that the module to be tested is configured in response to the configuration signal.
[0059] S202: Acquire actual status information of the module under test through the host monitor, and acquire actual interaction information between the module under test and the slave through the slave monitor.
[0060] The slave device is a slave device connected to the module under test (DUT).
[0061] When executing step S202, the module under test DUT is being driven to run, and the actual state information of the module under test is monitored by the host monitor of the master agent; the actual interaction information between the module under test and the slave is monitored by the device monitor of the slave agent.
[0062] Specifically, the host monitor obtains actual status information from the bus interface (apb / axi lite / axi) of the module under test DUT via the host interface host interface. The slave monitor device monitor obtains actual interaction information from the bus interface (apb / axi lite / axi) of the module under test DUT via the slave interface device interface.
[0063] S203 , simulating the operation of the module to be tested by using the reference model component to obtain simulation state information of the module to be tested and simulation interaction information between the module to be tested and the slave.
[0064] One end of the reference model component refer_model is directional associated with the host transaction of the master agent, and the other end is directional associated with the test case configuration information case_cfg. The reference model component is also directional associated with the slave transaction device transaction of the slave agent.
[0065] Specifically, a host transaction is generated by the reference model component refer_model according to the test case configuration information case_cfg and transmitted to the input scoreboard scoreboard ingress; a slave transaction is generated by the reference model component according to the test case configuration information and transmitted to the output scoreboard scoreboard egress, so as to simulate the operation of the module under test DUT, obtain the simulation state information of the module under test corresponding to the host transaction, and the simulation interaction information between the module under test and the slave corresponding to the slave transaction.
[0066] In some embodiments, after executing step S203, the method further includes: performing coverage analysis according to actual state information and actual interaction information through a coverage component. This can evaluate the integrity of module-level verification, help discover test gaps, and ensure a more comprehensive and complete verification of the module to be tested; it can measure the quality of module-level verification, thereby optimizing the verification process and improving the verification quality; during coverage analysis, redundant test cases and insufficient test areas may be identified, thereby optimizing and improving the test cases, which is conducive to improving the efficiency and effectiveness of verification.
[0067] S204: comparing the simulated state information with the actual state information through the output scoreboard to see if they are consistent, and comparing the simulated interaction information with the actual interaction information through the input scoreboard to see if they are consistent.
[0068] Specifically, the output-type scoreboard is used to compare whether the simulated state information is consistent with the actual state information, so as to compare whether the expected output behavior of the module under test DUT is consistent with the actual output behavior; the input-type scoreboard is used to compare whether the simulated interaction information is consistent with the actual interaction information, so as to compare whether the expected input behavior of the module under test DUT is consistent with the actual input behavior.
[0069] S205: If the simulated state information is consistent with the actual state information and the simulated interaction information is consistent with the actual interaction information, it is determined that the module to be tested passes the verification.
[0070] Specifically, if the simulation state information is consistent with the actual state information and the simulation interaction information is consistent with the actual interaction information, it means that the expected output / input behavior of the module under test DUT is consistent with the actual output / input behavior, and it can be determined that the module under test DUT has passed the verification.
[0071] In some embodiments, the method further includes: obtaining the timing information of the module to be tested through the assertion component; determining whether the timing information is correct; if so, determining that the design of the module to be tested is correct. This ensures that data can be transmitted accurately in the SOC and ensures that the system can operate stably and reliably. In summary, the present application provides a module-level verification method, which first controls the register model to drive the module to be tested to run according to the register configuration file, obtains the actual state information of the module to be tested through the host monitor, and obtains the actual interaction information between the module to be tested and the slave through the slave monitor; simulates the operation of the module to be tested through the reference model component to obtain the simulation state information of the module to be tested, and the simulation interaction information between the module to be tested and the slave; and then compares the simulation state information and the actual state information through the output scoring board, and compares the simulation interaction information and the actual interaction information through the input scoring board; if they are consistent, it is determined that the module to be tested has passed the verification. In this way, the present application integrates register models, host monitors, slave monitors, reference model components and input / output scoreboards to build an extensible and reusable modular verification environment, which can achieve comprehensive verification of the modules under test, is easy to adjust, low cost and has high verification efficiency.
[0072] In one embodiment, the present application provides an electronic device, which may be a terminal, and its internal structure diagram may be as follows: Figure 3 As shown. The electronic device includes a processor, a memory, a communication interface, a display screen and an input device connected through a system bus. Among them, the processor of the electronic device is used to provide computing and control capabilities. The memory of the electronic device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The communication interface of the electronic device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be implemented through WIFI, an operator network, near field communication (NFC) or other technologies. When the computer program is executed by the processor, a module-level verification method is implemented. The display screen of the electronic device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the electronic device can be a touch layer covered on the display screen, or a button, trackball or touchpad set on the housing of the electronic device, or an external keyboard, touchpad or mouse, etc.
[0073] Those skilled in the art will understand that Figure 3The structure shown in the figure is merely a block diagram of a partial structure related to the scheme of the present application, and does not constitute a limitation on the electronic device to which the scheme of the present application is applied. The specific electronic device may include more or fewer components than shown in the figure, or combine certain components, or have a different arrangement of components.
[0074] In one embodiment, the present application provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:
[0075] Control the register model to drive the operation of the module under test according to the register configuration file; obtain the actual state information of the module under test through the host monitor, and obtain the actual interaction information between the module under test and the slave through the slave monitor; simulate the operation of the module under test through the reference model component to obtain the simulated state information of the module under test and the simulated interaction information between the module under test and the slave; compare the simulated state information with the actual state information through the output scoreboard, and compare the simulated interaction information with the actual interaction information through the input scoreboard; if the simulated state information is consistent with the actual state information and the simulated interaction information is consistent with the actual interaction information, it is determined that the module under test has passed the verification.
[0076] In one embodiment, the processor also implements the following steps when executing the computer program: before controlling the register model to drive the module to be tested according to the register configuration file, the method also includes: controlling the interrupt service stimulus module to manipulate the register model to configure the module to be tested according to the test case configuration information to drive the module to be tested.
[0077] In one embodiment, the processor further implements the following steps when executing the computer program: after obtaining the actual status information of the module to be tested through the host monitor, and obtaining the actual interaction information between the module to be tested and the slave through the slave monitor, the method further includes: performing coverage analysis based on the actual status information and the actual interaction information through the coverage component.
[0078] In one embodiment, the processor further implements the following steps when executing the computer program: The method also includes: obtaining the timing information of the module to be tested through the assertion component; judging whether the timing information is correct; if so, determining that the design of the module to be tested is correct.
[0079] When the processor in the electronic device provided by the present application executes a computer program, it first controls the register model to drive the module to be tested to run according to the register configuration file, obtains the actual state information of the module to be tested through the host monitor, and obtains the actual interaction information between the module to be tested and the slave through the slave monitor; simulates the operation of the module to be tested through the reference model component to obtain the simulated state information of the module to be tested and the simulated interaction information between the module to be tested and the slave; then compares the simulated state information and the actual state information through the output scoring board to see if they are consistent, and compares the simulated interaction information and the actual interaction information through the input scoring board to see if they are consistent; if they are all consistent, it is determined that the module to be tested has passed the verification. In this way, the present application integrates the register model, the host monitor, the slave monitor, the reference model component and the input / output scoring board to build an expandable and reusable modular verification environment, so as to realize comprehensive verification of the module to be tested, which is easy to adjust, low in cost and high in verification efficiency.
[0080] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by the computer program, the following steps are implemented:
[0081] Control the register model to drive the operation of the module under test according to the register configuration file; obtain the actual state information of the module under test through the host monitor, and obtain the actual interaction information between the module under test and the slave through the slave monitor; simulate the operation of the module under test through the reference model component to obtain the simulated state information of the module under test and the simulated interaction information between the module under test and the slave; compare the simulated state information with the actual state information through the output scoreboard, and compare the simulated interaction information with the actual interaction information through the input scoreboard; if the simulated state information is consistent with the actual state information and the simulated interaction information is consistent with the actual interaction information, it is determined that the module under test has passed the verification.
[0082] In one embodiment, the computer program further implements the following steps when executing the computer program: before controlling the register model to drive the module to be tested according to the register configuration file, the method also includes: controlling the interrupt service stimulus module to manipulate the register model to configure the module to be tested according to the test case configuration information to drive the module to be tested.
[0083] In one embodiment, the computer program further implements the following steps when executing the computer program: after obtaining the actual state information of the module to be tested through the host monitor, and obtaining the actual interaction information between the module to be tested and the slave through the slave monitor, the method further includes: performing coverage analysis based on the actual state information and the actual interaction information through the coverage component.
[0084] In one embodiment, the computer program further implements the following steps when executing the computer program: The method also includes: obtaining the timing information of the module to be tested through the assertion component; judging whether the timing information is correct; if so, determining that the design of the module to be tested is correct.
[0085] When the computer program in the computer-readable storage medium provided by the present application executes the computer program, the register model is first controlled according to the register configuration file to drive the module to be tested to run, the actual state information of the module to be tested is obtained through the host monitor, and the actual interaction information between the module to be tested and the slave is obtained through the slave monitor; the operation of the module to be tested is simulated through the reference model component to obtain the simulated state information of the module to be tested and the simulated interaction information between the module to be tested and the slave; and then the simulated state information and the actual state information are compared through the output scoring board to see if they are consistent, and the simulated interaction information and the actual interaction information are compared through the input scoring board to see if they are consistent; if they are all consistent, it is determined that the module to be tested has passed the verification. In this way, the present application integrates the register model, the host monitor, the slave monitor, the reference model component and the input / output scoring board to build an expandable and reusable modular verification environment, so as to realize comprehensive verification of the module to be tested, which is easy to adjust, low in cost and high in verification efficiency.
[0086] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media that include computer-usable program code.
[0087] In several embodiments provided by the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.
[0088] In the present application, the processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.
[0089] In this application, memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.
[0090] In this application, computer-readable media includes permanent and non-permanent, removable and non-removable storage media. Storage media can be implemented by any method or technology to store information, and the information can be computer-readable instructions, data structures, modules of programs or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. According to the definition in this article, computer-readable media does not include temporary computer-readable media (transitory media), such as modulated data signals and carrier waves.
[0091] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.
[0092] The above is only a specific implementation of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to these embodiments herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A module-level verification method, characterized in that: Applied to module-level verification systems, including: According to the register configuration file, the control register model drives the module under test to run; Acquire actual status information of the module under test through a host monitor, and acquire actual interaction information between the module under test and a slave through a slave monitor; Simulating the operation of the module to be tested by using a reference model component to obtain simulation state information of the module to be tested and simulation interaction information between the module to be tested and the slave; Comparing the simulated state information with the actual state information through an output-type scoreboard to see whether they are consistent, and comparing the simulated interaction information with the actual interaction information through an input-type scoreboard to see whether they are consistent; If the simulation state information is consistent with the actual state information and the simulation interaction information is consistent with the actual interaction information, it is determined that the module to be tested passes the verification.
2. The method according to claim 1, characterized in that Before controlling the register model to drive the module to be tested according to the register configuration file, the method further includes: According to the test case configuration information, the control interrupt service stimulus module manipulates the register model to configure the module to be tested so as to drive the module to be tested.
3. The method according to claim 1, characterized in that After obtaining the actual state information of the module to be tested through the host monitor, and obtaining the actual interaction information between the module to be tested and the slave through the slave monitor, the method further includes: A coverage component is used to perform coverage analysis according to the actual state information and the actual interaction information.
4. The method according to claim 1, characterized in that: The method further comprises: Acquire the timing information of the module under test through the assertion component; Determining whether the timing information is correct; If so, it is determined that the module to be tested is designed correctly.
5. A module-level verification system, characterized in that: include: The top-level module is used to start and manage the test case module and establish a connection between the test case module and the module to be tested; The test case module is used to build a verification environment, and the test case module includes: a register model, an interrupt service stimulus module, test case configuration information and an environment component; The register model is used to simulate the register behavior of the module under test; the interrupt service stimulus module is used to control the register model to configure the module under test; the environment components include: a reference model component, a host agent, a slave agent, an input scoreboard and an output scoreboard; The reference model component is used to simulate the operation of the module to be tested, and obtain the simulation state information of the module to be tested, and the simulation interaction information between the module to be tested and the slave; the host agent is used to obtain the actual state information of the module to be tested through the host monitor; the slave agent is used to obtain the actual interaction information between the module to be tested and the slave through the slave monitor; the input scoreboard is used to compare whether the simulation state information is consistent with the actual state information; the output scoreboard is used to compare whether the simulation interaction information is consistent with the actual interaction information.
6. The verification system according to claim 5, characterized in that: The environment component also includes a coverage component; The coverage component is used to perform coverage analysis according to the actual state information and the actual interaction information.
7. The verification system according to claim 5, characterized in that: The top-level module is also used to establish a connection between the assertion component and the module to be tested; Wherein, the assertion component is used to: Acquiring timing information of the module to be tested; Determining whether the timing information is correct; If so, it is determined that the module to be tested is designed correctly.
8. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program implements the module-level verification method according to any one of claims 1 to 4 when executed by the processor.
9. A computer-readable storage medium, characterized in that: include: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the module-level verification method according to any one of claims 1 to 4 is implemented.
10. A computer program product, characterized in that include: The computer program product comprises a computer program, and when the computer program is run on a computer, the computer is enabled to implement the module-level verification method according to any one of claims 1 to 4.