Data access method of system on chip, system on chip and electronic device

Abstract

The application discloses a data access method of a system on chip, a system on chip and electronic equipment, and belongs to the chip field. In the method, for any AHB master device in the system on chip, there are at least two access links between the AHB master device and any APB slave device. Based on this, when the AHB master device sends an access request to the APB slave device through one of the access links, the data bridge connected to the APB slave device can temporarily store the data of the access request to release the APB bus in advance, so that the AHB master device can access the APB slave device through other access links or access other APB slave devices, thereby improving the use efficiency and utilization of the bus in the system on chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chips, in particular to a data access method of a system on chip, a system on chip and an electronic device. BACKGROUND

[0002] Advanced High-performance Bus (AHB) and Advanced Peripheral Bus (APB) are commonly used bus protocols in chip design. At present, in a system on chip (SoC) using AHB and APB, only one AHB master device can access one APB slave device at the same time.

[0003] In the related art, for some APB slave devices (also referred to as low-speed devices or low-speed modules, etc.) with low working frequency and low data transmission rate, when the AHB master device performs a write operation on the low-speed devices through the APB, the AHB master device can only release the APB bus after the low-speed devices complete the operation due to the slow processing speed of the low-speed devices, which causes the APB bus to be occupied by the low-speed devices for a long time, affecting the use efficiency and utilization rate of the APB bus. SUMMARY

[0004] Embodiments of the present application provide a data access method of a system on chip, a system on chip and an electronic device, which can improve the use efficiency and utilization rate of the bus in the system on chip. The technical solution is as follows.

[0005] In a first aspect, a data access method of a system on chip is provided, applied to a system on chip, the system on chip comprising a first bus system using an Advanced High-performance Bus (AHB) and a second bus system using an Advanced Peripheral Bus (APB), the first bus system and the second bus system being connected through a plurality of AHB-APB bridges, there being at least two access links between each AHB master device in the first bus system and each APB slave device in the second bus system, each APB slave device being connected with a data bridge, and the method comprising:

[0006] a first AHB master device in the first bus system sends a first access request to a first APB slave device in the second bus system through a first access link;

[0007] The first APB slave device receives the first access request from the first data bridge, and if the first access request is a write request and the first APB slave device is in a busy state, stores data of the first access request to the first data bridge, and then sends an APB release signal to the first AHB master device, or if the first access request is a read request, reads data of the first access request from the first APB slave device, stores the read data to the first data bridge, and then sends an APB release signal to the first AHB master device;

[0008] After receiving the APB release signal, the first AHB master device sends a second access request to the first APB slave device through a second access link, or sends a third access request to a second APB slave device in the second bus system through a third access link.

[0009] The access link between the first AHB master device and the first APB slave device includes the first access link and the second access link, and the AHB-APB bridges on the first access link and the second access link are the same or different.

[0010] In some embodiments, the method further comprises:

[0011] If the first access request is a write request, the first data bridge writes the data of the first access request to the first APB slave device after storing the data of the first access request to the first data bridge, and in the case that the first APB slave device is in an idle state.

[0012] If the first access request is a read request, the first data bridge transmits the data of the first access request to the first AHB master device after sending an APB release signal to the first AHB master device.

[0013] In some embodiments, if the first access request is a write request and the first APB slave device is in a busy state, the first data bridge stores the data of the first access request to the first data bridge, and then sends an APB release signal to the first AHB master device, comprising:

[0014] The first data bridge determines a storage level of the data of the first access request based on the type of the data, different storage levels correspond to different storage areas in the first data bridge, and different storage areas correspond to different access performances.

[0015] The first data bridge stores the data to the storage area corresponding to the storage level of the data in the first data bridge based on the storage level of the data.

[0016] In some embodiments, the first data bridge stores the data to a storage area corresponding to a storage level of the data in the first data bridge based on the storage level of the data, including:

[0017] The first data bridge stores the data to a first storage area in the first data bridge based on a storage level of the data.

[0018] The method further includes:

[0019] The first data bridge predicts a state of the first APB slave device, and if a prediction result indicates that the first APB slave device will change from the busy state to an idle state within a preset time period, the data is transferred from the first storage area to a second storage area in the first data bridge, the second storage area having a higher access performance than the first storage area.

[0020] In some embodiments, the method further includes:

[0021] The first AHB master device records execution information of the access request sent to the first APB slave device through different access links, the execution information including at least one of an execution duration and an execution success rate of the access request.

[0022] After receiving the APB release signal, the first AHB master device sends a second access request to the first APB slave device through a second access link, including:

[0023] After receiving the APB release signal, the first AHB master device determines the second access link from a plurality of access links based on the execution information, and sends the second access request to the first APB slave device through the second access link, the plurality of access links excluding the first access link.

[0024] In some embodiments, the first access link includes a first arbiter, a first AHB-APB bridge, and a second arbiter; the first AHB master device sends a first access request to the first APB slave device in the second bus system through the first access link, including:

[0025] The first AHB master device sends the first access request to the first arbiter;

[0026] After arbitrating the received first access request and a fourth access request sent by a second AHB master device, the first arbiter sends the first access request to the second arbiter through the first AHB-APB bridge;

[0027] The second arbiter sends the first access request to the first data bridge after arbitrating the received first access request and a fifth access request sent by a third AHB master device.

[0028] In some embodiments, the first arbiter, the first AHB-APB bridge and the second arbiter are all provided with a fault detection function, and the method further comprises:

[0029] In the process that the first AHB master device sends the first access request to the first APB slave device through the first access link, if any one of the first arbiter, the first AHB-APB bridge and the second arbiter detects a fault of the first access link, the node switches the first access request to a fourth access link to send the first access request to the first APB slave device through the fourth access link, and the access link between the first AHB master device and the first APB slave device includes the fourth access link.

[0030] In a second aspect, a system-on-chip is provided, which includes a first bus system using an advanced high-performance bus (AHB) and a second bus system using an advanced peripheral bus (APB), the first bus system and the second bus system are connected through a plurality of AHB-APB bridges, there are at least two access links between each AHB master device in the first bus system and each APB slave device in the second bus system, and each APB slave device is connected with a data bridge.

[0031] A first AHB master device in the first bus system is configured to send a first access request to a first APB slave device in the second bus system through a first access link.

[0032] A first data bridge connected with the first APB slave device is configured to receive the first access request, if the first access request is a write request and the first APB slave device is in a busy state, store data of the first access request to the first data bridge, and then send an APB release signal to the first AHB master device, or if the first access request is a read request, read data of the first access request from the first APB slave device and store the read data to the first data bridge, and then send an APB release signal to the first AHB master device.

[0033] The first AHB master device is further configured to, after receiving the APB release signal, send a second access request to the first APB slave device through a second access link, or send a third access request to a second APB slave device in the second bus system through a third access link.

[0034] The access link between the first AHB master device and the first APB slave device includes the first access link and the second access link, and the AHB-APB bridges on the first access link and the second access link are the same or different.

[0035] In some embodiments, if the first access request is a write request, the first data bridge is further configured to store the data of the first access request to the first data bridge, and then write the data of the first access request to the first APB slave device when the first APB slave device is in an idle state; if the first access request is a read request, the first data bridge is further configured to transmit the data of the first access request to the first AHB master device after sending an APB release signal to the first AHB master device.

[0036] In some embodiments, if the first access request is a write request and the first APB slave device is in a busy state, the first data bridge is configured to determine a storage level of the data of the first access request based on a type of the data, different storage levels correspond to different storage areas in the first data bridge, and different storage areas correspond to different access performances; and store the data in a storage area corresponding to the storage level of the data in the first data bridge.

[0037] In some embodiments, the first data bridge is configured to store the data in a first storage area in the first data bridge based on the storage level of the data; predict a state of the first APB slave device, and if a prediction result indicates that the first APB slave device will change from the busy state to an idle state within a preset time period, transfer the data from the first storage area to a second storage area in the first data bridge, the access performance of the second storage area being higher than that of the first storage area.

[0038] In some embodiments, the first AHB master device is further configured to record execution information of access requests sent to the first APB slave device through different access links, the execution information including at least one of an execution duration and an execution success rate of an access request; and after receiving the APB release signal, determine the second access link from a plurality of access links based on the execution information, and send the second access request to the first APB slave device through the second access link, the plurality of access links excluding the first access link.

[0039] In some embodiments, the first access link comprises a first arbiter, a first AHB-APB bridge and a second arbiter; the first AHB master is configured to send the first access request to the first arbiter; the first arbiter is configured to arbitrate the received first access request and a fourth access request sent by a second AHB master, and send the first access request to the second arbiter through the first AHB-APB bridge; and the second arbiter is configured to arbitrate the received first access request and a fifth access request sent by a third AHB master, and send the first access request to the first data bridge.

[0040] In some embodiments, the first arbiter, the first AHB-APB bridge and the second arbiter all have a fault detection function. During the process that the first AHB master sends the first access request to the first APB slave through the first access link, if any one of the first arbiter, the first AHB-APB bridge and the second arbiter detects a fault of the first access link, the node is configured to switch the first access request to a fourth access link to send the first access request to the first APB slave through the fourth access link, and the access link between the first AHB master and the first APB slave comprises the fourth access link.

[0041] In a third aspect, an electronic device is provided, which comprises a memory and a processor, and the memory stores at least one computer program, and the at least one computer program is loaded and executed by the processor to implement the data access method of the system on chip provided in the first aspect.

[0042] In a fourth aspect, a computer readable storage medium is provided, which stores at least one computer program, and the at least one computer program is loaded and executed by a processor to implement the data access method of the system on chip provided in the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0044] Figure 1 is a schematic diagram of an implementation environment provided by an embodiment of the present application;

[0045] Figure 2is a flowchart of a data access method of a system on chip provided by an embodiment of the present application;

[0046] Figure 3 is a structural schematic diagram of a data bridge provided by an embodiment of the present application;

[0047] Figure 4 is a schematic diagram of a data access device of a system on chip provided by an embodiment of the present application;

[0048] Figure 5 is a structural schematic diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0049] To make the purpose, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0050] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data for analysis, stored data, displayed data, etc.) and signals involved in the present application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data need to comply with relevant laws, regulations and standards of relevant countries and regions. For example, the access request, device priority and the like involved in the present application are obtained under sufficient authorization.

[0051] Figure 1 is a schematic diagram of an implementation environment provided by an embodiment of the present application. As shown in Figure 1 The implementation environment includes a system on chip 100, the system on chip 100 includes a first bus system 110 adopting an advanced high-performance bus AHB and a second bus system 120 adopting an advanced peripheral bus APB, and the first bus system 110 and the second bus system 120 are connected through a plurality of AHB-APB bridges. There are at least two access links between each AHB master in the first bus system 110 and each APB slave in the second bus system 120, and each APB slave is connected with a data bridge.

[0052] Taking any one of the access links between any one AHB master and any one APB slave as an example, the access link includes: the AHB master, a multiplexer, an arbiter, an AHB-APB bridge, an arbiter, an APB interface, a data bridge and the APB slave.

[0053] AHB master device is, for example, a central processing unit (CPU), a direct memory access (DMA) controller, or other auxiliary operators, and the type of AHB master device is not limited in the present application. The multiplexer is also called an address selector, which is used to select any one of the multiple data transmission paths as needed during the process of multiple data transmission, also known as a multiplexer or a multi-way switch. The input end of the multiplexer is connected with the AHB master device, and the multiple output ends of the multiplexer are respectively connected with multiple arbitrators. The output end of each arbitrator is respectively connected with an AHB-APB bridge. For any AHB-APB bridge, the multiple output ends of the AHB-APB bridge are respectively connected with multiple arbitrators, and the output end of each arbitrator is respectively connected with an APB interface. The multiple output ends of each APB interface are respectively connected with multiple data bridges, and each data bridge is respectively connected with an APB slave device. The APB slave device refers to a peripheral device, such as a universal asynchronous receiver-transmitter, a serial peripheral interface, a timer, etc. It should be understood that, since the data transmission speed of these peripheral devices is relatively slow compared with the APB, when these peripheral devices interact with the AHB master device in the system through the APB, due to their own slow speed, the APB will wait for the peripheral device to complete the operation before releasing the bus, which will further affect the use efficiency and utilization rate of the bus. These peripheral devices can also be referred to as a kind of low-speed intellectual property (IP) module. It should be understood that IP in the field of chip design refers to a circuit module design with specific functions and reusability, and low speed means that the data transmission speed of the peripheral device is slower than the data transmission speed of the APB.

[0054] As shown above, in the system on chip 100, through the multiplexer, one AHB master device can be interconnected and accessed with multiple different AHB-APB bridges (in this process, the AHB-APB bridge can be understood as an AHB slave device relative to the AHB master device). Further, each AHB-APB bridge is connected with an arbitrator, which ensures that a single AHB-APB bridge is accessed by only one AHB master device at the same time, and the arbitrator also ensures that the connected APB interface can be accessed by only one AHB-APB bridge at the same time, that is, one AHB-APB bridge can be interconnected and accessed with multiple different APB slave devices (in this process, the AHB-APB bridge can be understood as an APB master device relative to the APB slave device), but at the same time, a single APB slave device can be accessed by only one AHB-APB bridge.

[0055] Furthermore, in the System-on-Chip 100, there are at least two non-interfering access links between any AHB master device and any APB slave device. This allows the AHB master device to simultaneously access the APB slave device using at least two non-interfering access links, thereby improving system processing performance. It should be noted that... Figure 1 The examples shown are merely illustrative and do not constitute a limitation of this application. As the number of AHB master devices, AHB-APB bridges, and APB interfaces increases, the number of non-interfering master-slave access links can be further increased, and the system processing speed can be further improved.

[0056] The System-on-Chip 100 described above can be deployed in electronic devices. These electronic devices include, but are not limited to, in-vehicle terminals, smartphones, tablets, laptops, desktop computers, and smartwatches. For example, an in-vehicle terminal integrated into a vehicle itself can be used. In some embodiments, the vehicle is a new energy vehicle, such as a pure electric vehicle, a plug-in hybrid electric vehicle, or a fuel cell electric vehicle; this application does not limit this. When the System-on-Chip 100 is deployed in an in-vehicle terminal, the AHB master device is, for example, a CPU, responsible for running the operating system, various in-vehicle applications, and processing data received from different sensors and devices. The AHB master device can also be, for example, a DMA controller. A large amount of data in the in-vehicle terminal needs to be rapidly transferred between different storage areas or devices, such as reading map data from flash memory into memory. As an AHB master device, the DMA controller can directly perform high-speed data transfer between memory and other devices without occupying CPU resources, controlling the data flow through the AHB to achieve efficient data transfer. The APB slave device is, for example, a Universal Asynchronous Receiver / Transmitter (UAR), used for serial communication between the in-vehicle terminal and external devices. Other examples include timers, Serial Peripheral Interfaces (SPI), and Integrated Circuit Bus (I2C) interfaces. The SPI and I2C interfaces are used to connect various low-speed peripheral devices, such as sensors (temperature sensors, tire pressure sensors, etc.) and some simple actuators. These interfaces act as APB slave devices, reading sensor data or sending control signals to actuators according to the instructions of the APB master device, enabling interaction between the vehicle system and external devices. For example, data from the tire pressure sensor can be read via the SPI interface and transmitted to the vehicle terminal for tire pressure monitoring and alarm functions.

[0057] Figure 2 This is a flowchart of a data access method for an on-chip system provided in an embodiment of this application. For example... Figure 2 As shown, this method is applied to Figure 1 The system-on-a-chip shown is used as an example to introduce the data access method of the system-on-a-chip, taking the interaction between various components in the system-on-a-chip as an example. The method includes the following steps 201 to 204.

[0058] 201、The first AHB master in the first bus system sends a first access request to the first APB slave in the second bus system through the first access link.

[0059] In the embodiments of the present application, the system on chip includes a first bus system using AHB and a second bus system using APB. The first AHB master is any one of the AHB masters in the first bus system, and the first APB slave is any one of the APB slaves accessible by the first AHB master in the second bus system. The first access request is a write request or a read request, which is not limited in the present application.

[0060] Illustratively, the first access link includes the first AHB master, a multiplexer, a first arbiter, a first AHB-APB bridge, a second arbiter, an APB interface, a first data bridge, and the first APB slave. The first arbiter and the second arbiter can simultaneously receive multiple access requests, and arbitrate the received multiple access requests to determine the priority of each access request, or in other words, the sending order of each access request.

[0061] In some embodiments, in the process of the first AHB master sending the first access request to the first APB slave through the first access link, the first AHB master sends the first access request to the first arbiter through the multiplexer. The first arbiter arbitrates the received first access request and a fourth access request sent by a second AHB master, and then sends the first access request to the second arbiter through the first AHB-APB bridge. The second arbiter arbitrates the received first access request and a fifth access request sent by a third AHB master, and then sends the first access request to the first data bridge connected to the first APB slave. That is, in the case that the first arbiter and the second arbiter simultaneously receive multiple access requests, the first access request is determined to be sent preferentially through arbitration. The second AHB master is any one of the AHB masters in the first bus system except the first AHB master, and the third AHB master is any one of the AHB masters in the first bus system except the first AHB master. The second AHB master and the third AHB master are the same or different.

[0062] In some embodiments, the first arbiter arbitrates the received first access request and fourth access request based on a priority of the first AHB master and a priority of the second AHB master, and sends the first access request to the second arbiter through the first AHB-APB bridge in a case that the priority of the first AHB master is higher than the priority of the second AHB master. The priority of the first AHB master and the priority of the second AHB master can be pre-set, or can be determined by the first arbiter based on access requests received in a historical time period. For example, the first arbiter records access requests of each AHB master in the historical time period, such as recording historical information of request frequency, data transmission amount, and transmission delay requirement, and determines a priority weight of each AHB master based on the historical information. When multiple access requests arrive at the first arbiter at the same time, the weights are used to determine which request is processed preferentially. For example, an AHB master that often needs to transmit a large amount of real-time data and is sensitive to delay is given a higher priority, so that the transmission requirements of different types of data in the system can be better met, and the overall performance is improved. It should be noted that the second arbiter can use the same arbitration method as the first arbiter, which will not be described here.

[0063] 202. The first APB slave receives the first access request from the first data bridge.

[0064] In the embodiments of the present application, the first APB slave is connected with the first data bridge, the first data bridge is connected with the APB interface, and when the first access request of the first AHB master reaches the APB interface through the AHB on the first access link, the first AHB-APB bridge, and the APB interface receives the first access request, analyzes the first access request to obtain an access type, and transmits a corresponding signal to the first data bridge based on the access type to make the first data bridge write data or read data to the first APB slave. For example, the APB interface analyzes the first access request based on a pre-defined control signal coding format, determines that the access type is a write request when a specific write operation identification bit is set, and determines that the access type is a read request when a specific read operation identification bit is set.

[0065] Generally, the APB interface parses the first access request, and if it is determined that the access type is a write request, the write request, the access address and the write data signal are transmitted to the first data bridge, the first data bridge synchronizes the write data signal to the interface timing of the first APB slave device, and if the completion signal of the first APB slave device is high, the write data is written into the first APB slave device. It should be understood that the data is written when the first APB slave device is ready (the completion signal is high), so as to ensure data integrity and avoid errors caused by forced writing when the first APB slave device is not ready. In the above process, the first data bridge returns the write data completion signal after receiving the write request, the access address and the write data signal, and the PREADY signal in the APB is pulled high through the signal, the APB bus is released, and the first AHB master device is allowed to access the APB slave device through the above APB interface again.

[0066] Alternatively, the APB interface parses the first access request, and if it is determined that the access type is a read request, the read request, the access address and the read data signal are transmitted to the first data bridge, the first data bridge synchronizes the read data signal to the interface timing of the first APB slave device, and if the first APB slave device is in an idle state, the data is read and transmitted to the APB interface through the first data bridge, and the data is returned to the first AHB master device by the APB interface.

[0067] In the present application, there are at least two access links between the first AHB master device and the first APB slave device, which do not interfere with each other. Based on this, in the case that the first access request is a write request and the first APB slave device is in a busy state, the first data bridge can store the data of the first access request to the first data bridge, and then send the APB release signal to the first AHB master device in advance. Alternatively, in the case that the first access request is a read request, the first data bridge reads the data of the first access request from the first APB slave device and stores the read data to the first data bridge, and then sends the APB release signal to the first AHB master device. The two cases will be introduced respectively through steps 203A and 203B.

[0068] 203A, the first access request is a write request and the first APB slave device is in a busy state, the first data bridge stores the data of the first access request to the first data bridge, and then sends the APB release signal to the first AHB master device.

[0069] Among them, the first data bridge stores the data of the first access request to the first data bridge, and then sends the APB release signal to the first AHB master device, and in the case that the first APB slave device is in an idle state, the data of the first access request is written into the first APB slave device.

[0070] In some embodiments, the first data bridge is configured with a plurality of storage areas, different storage areas correspond to different access performance, and different storage areas correspond to different storage levels. Illustratively, the first data bridge determines the storage level of the data based on the type of the data of the first access request; the first data bridge stores the data in the storage area corresponding to the storage level in the first data bridge based on the storage level of the data. For example, the type of data includes real-time data, control data and batch data, and accordingly, the storage level of the data from high to low is level one, level two and level three, that is, for frequently accessed real-time data, the storage level is determined to be level one, and the data is stored in a storage area with high access performance, which can improve the speed of subsequent writing data to the first APB slave device. Illustratively, taking the deployment of a system on chip in a vehicle terminal as an example, real-time obstacle detection data from a laser radar belongs to real-time data, and its storage level is level one; the control instruction data of the vehicle power system belongs to control data, and its storage level is level two; the vehicle driving history data collected periodically for background analysis belongs to batch data, and its storage level is level three.

[0071] In addition, the capacity of each storage area in the first data bridge can be dynamically configured according to the average flow and peak demand of the corresponding type of data in the system. Taking the storage area corresponding to real-time data as an example, 1KB of space is initially allocated, and when the usage rate of this area exceeds 80%, a replacement mechanism based on the Least Recently Used (LRU) algorithm is started to ensure that there is enough space to store frequently accessed real-time data.

[0072] In other embodiments, after the first data bridge stores the data in the storage area with low access performance, when the first data bridge judges that the first APB slave device is about to be idle, the data can be prefetched from the storage area with low access performance to the storage area with high access performance in advance, so that when the first APB slave device is idle, the data can be quickly obtained, and the delay of data transmission is reduced. Illustratively, the first data bridge stores the data in the storage area corresponding to the storage level in the first data bridge based on the storage level of the data, comprising: the first data bridge stores the data in the first storage area in the first data bridge based on the storage level of the data; the first data bridge predicts the state of the first APB slave device, and if the prediction result indicates that the first APB slave device will change from a busy state to an idle state within a preset time period, the data is transferred from the first storage area to a second storage area in the first data bridge, and the access performance of the second storage area is higher than that of the first storage area.

[0073] 203B, the first access request is a read request, the first data bridge reads the data of the first access request from the first APB slave device and stores the read data to the first data bridge, and sends an APB release signal to the first AHB master device.

[0074] The first data bridge stores the data of the first access request to the first data bridge, sends an APB release signal to the first AHB master, and transmits the data of the first access request to the first AHB master. It should be understood that the APB adopts a signal control-based operation mode. In the read operation, the APB slave device occupies the bus to transmit data. When the data bridge returns the APB release signal, it indicates that the data bridge determines that the APB slave device has completed the main operation of the data read stage, that is, the data is sent to the bus to be transmitted to the master device. In the process of transmitting the data from the APB slave device to the AHB master device through the APB bus, the transmission of the data is relatively independent of the bus resource allocation. Once the data has been sent to the bus, it is transmitted to the destination according to the transmission mechanism of the bus (such as clock driving). At this time, the APB slave device no longer needs to occupy the bus to ensure the transmission of the data, so that the bus can be released.

[0075] 204、The first AHB master receives the APB release signal, sends a second access request to the first APB slave device through a second access link, or sends a third access request to a second APB slave device in a second bus system through a third access link.

[0076] In the embodiment of the application, after the first AHB master receives the APB release signal, the first AHB master can continue to access the first APB slave device through the second access link, or access a second APB slave device in the second bus system through the third access link. The access link between the first AHB master and the first APB slave device includes the first access link and the second access link, and the AHB-APB bridges on the first access link and the second access link are the same or different. In addition, the second APB slave device is connected with a second data bridge, and the second data bridge has the same function as the first data bridge, which will not be described again.

[0077] In some embodiments, the first AHB master records execution information of the access request sent to the first APB slave through different access links, the execution information including at least one of execution duration and execution success rate of the access request; after receiving the APB release signal, the first AHB master sends a second access request to the first APB slave through a second access link, including: after receiving the APB release signal, the first AHB master determines the second access link from a plurality of access links based on the execution information, and sends the second access request to the first APB slave through the second access link, the plurality of access links excluding the first access link. For example, by setting a monitoring point on each AHB-APB bridge, the data flow, transmission delay and other parameters of each access link are counted in real time, so that the first AHB master can record the execution information of the access request sent to the first APB slave through different access links based on these parameters. When a new access link needs to be selected, the first AHB master selects an access link with more successful data transmission times and lower error rate in a period of time based on the recorded execution information, which can improve the efficiency and reliability of data transmission.

[0078] In some embodiments, the first arbiter, the first AHB-APB bridge and the second arbiter on the first access link are provided with fault detection functions. Based on this, in the process that the first AHB master sends a first access request to the first APB slave through the first access link, if any one of the first arbiter, the first AHB-APB bridge and the second arbiter detects that the first access link fails, the node switches the first access request to the fourth access link to send the first access request to the first APB slave through the fourth access link, and the access link between the first AHB master and the first APB slave includes the fourth access link. Illustratively, the first arbiter, the first AHB-APB bridge and the second arbiter are configured with an increased fault detection circuit for detecting data transmission errors, signal integrity problems, etc. When any one of the nodes detects a fault, a recovery mechanism is started in time to switch the link and improve the reliability and stability of the system. Moreover, the node can feed back fault information to the first AHB master for further fault diagnosis and processing. For example, the first arbiter, the first AHB-APB bridge and the second arbiter take 100 ns as a detection period, check the transmitted data through a built-in parity check circuit, and trigger a fault detection process once the number of error bits exceeds a threshold (such as 2 bits). After the link is switched to the fourth access link, a handshake signal is used for data synchronization to ensure the continuity of data before and after switching, and the last period of data is retransmitted for verification to ensure stable operation of the system. Illustratively, taking a system on chip deployed in a vehicle terminal as an example, due to factors such as vibration and electromagnetic interference of the vehicle, the data transmission link may fail. For example, when the data transmission link of the vehicle communication module fails, the system can quickly switch to a backup link to ensure the continuity of communication, avoid data loss, and improve the reliability and stability of the entire vehicle terminal in a complex environment.

[0079] The data bridge shown in Figure 3 The data access method of the system on chip is exemplified. Figure 3 is a structural schematic diagram of a data bridge provided by an embodiment of the present application. As Figure 3As shown, the data bridge, as a link between the APB and the APB slave (i.e. IP module) for data transmission, includes the following modules: data synchronization module, control signal buffer module, address buffer module, write data buffer module and IP interface conversion module. These modules can cooperatively realize the following functions: data transmission and reception buffer, data clock domain synchronization and generation of release bus control signal. In the figure, PWRITE is a write enable signal, PSEL is a chip select signal, PENABLE is an enable signal, PADDR is an address signal, PWDATA is a write data signal, PSLVERR is a slave error signal, PREADY is a ready signal, REG_EN is a register enable signal, IP_IDLE is an IP module idle signal, IP_RDATA is an IP module read data signal, IP_WDATA is an IP module write data signal, DATA_ERR is a data error signal, read_en is a read enable signal, and write_en is a write enable signal.

[0080] Taking the write request received by the data bridge as an example, if the write data control signals PWRITE, PSEL, PENABLE are valid and the storage area in the data bridge is not full (REG_EN = 1), the data bridge returns the PREADY signal to the AHB master to inform it that the current write operation is ready, and the AHB master can decide whether to continue to send subsequent data or perform other related operations according to the signal. If the storage area in the data bridge is full, the APB needs to wait and cannot release the APB bus until the storage area can be written. During this period, the AHB master can normally operate other APB slaves. When the APB slave can write data, the PSEL, PENABLE, PWRITE signals and WDATA are synchronized to the clock domain of the APB slave. Then PWDATA is stored to the buffer module of the data bridge and converted to the interface timing of the APB slave and transmitted to the APB slave.

[0081] Taking the write request received by the data bridge as an example, if the write data control signals PWRITE, PSEL, PENABLE are valid and the storage area in the data bridge is not full (REG_EN = 1), the data bridge returns the PREADY signal to the AHB master to inform it that the current write operation is ready, and the AHB master can decide whether to continue to send subsequent data or perform other related operations according to the signal. If the storage area in the data bridge is full, the APB needs to wait and cannot release the APB bus until the storage area can be written. During this period, the AHB master can normally operate other APB slaves. When the APB slave can write data, the PSEL, PENABLE, PWRITE signals and WDATA are synchronized to the clock domain of the APB slave. Then PWDATA is stored to the buffer module of the data bridge and converted to the interface timing of the APB slave and transmitted to the APB slave.

[0082] In addition, the address cache module is configured to control address delay. Illustratively, if the current access request has not been completed (i.e., IP_IDLE≠1), the address cache module waits until the APB slave device read-write data operation is completed (i.e., IP_IDLE=1); otherwise, the address cache module transmits the address to the IP interface conversion module to execute the access request.

[0083] The write data cache module is configured to control write data delay. Illustratively, if the current access request has not been completed (i.e., IP_IDLE≠1), the write data cache module waits until the APB slave device read-write data operation is completed (i.e., IP_IDLE=1); otherwise, the write data cache module transmits the write data to the IP interface conversion module to execute the access request.

[0084] The read-write control signal cache module is configured to control read-write control signal delay. Illustratively, if the current access request has not been completed (i.e., IP_IDLE≠1), the read-write control signal cache module waits until the APB slave device is completed (i.e., IP_IDLE=1); otherwise, the read-write control signal cache module transmits the read-write control signal to the IP interface conversion module to execute the access request.

[0085] The data synchronization module is configured to synchronize the PSEL, PENABLE, PWRITE, etc. of the APB to the clock domain of the APB slave device during execution of the write request, and synchronize the IP_RDATA and DATA_ERR, etc. of the APB to the clock domain of the APB slave device during execution of the read request, and then transmit the data to the APB, and finally return the data signal to the AHB master device.

[0086] In summary, in the data access method of the system-on-chip provided in the embodiments of the present application, for any AHB master device in the system-on-chip, there are at least two access links between the AHB master device and any APB slave device. Based on this, when the AHB master device sends an access request to the APB slave device through one of the access links, the data bridge connected to the APB slave device can temporarily store the data of the access request to release the APB bus in advance, so that the AHB master device can access the APB slave device through other access links, or access other APB slave devices, thereby improving the use efficiency and utilization rate of the bus in the system-on-chip.

[0087] In addition, in the case of deploying the above-mentioned system on chip in a vehicle terminal, since in the vehicle terminal, there are various data that need to be processed at the same time, such as navigation data, multimedia data, vehicle sensor data, etc. With the above-mentioned system on chip, there are at least two access links between the first AHB master and the first APB slave, which do not interfere with each other, which makes different types of data can be transmitted through different links, avoiding the bottleneck of data transmission. For example, when the navigation system needs to frequently update the map data (through the write request), at the same time, the vehicle state monitoring system can read the sensor data through another link, which improves the concurrent processing capability of the system and effectively improves the data access efficiency.

[0088] Referring to Figure 4 The embodiment of the present application provides a data access device of a system on chip, which can be configured in the system on chip. Illustratively, the device comprises a first sending module 401, a receiving module 402 and a second sending module 403.

[0089] The first sending module 401 is configured in a first AHB master in a first bus system, and is used for sending a first access request to a first APB slave in a second bus system through a first access link;

[0090] The receiving module 402 is configured in a first data bridge connected with the first APB slave, and is used for receiving the first access request. If the first access request is a write request and the first APB slave is in a busy state, the data of the first access request is stored to the first data bridge, and then an APB release signal is sent to the first AHB master, or if the first access request is a read request, the data of the first access request is read from the first APB slave and stored to the first data bridge, and then an APB release signal is sent to the first AHB master;

[0091] The second sending module 403 is configured in the first AHB master, and is used for sending a second access request to the first APB slave through a second access link after receiving the APB release signal, or sending a third access request to a second APB slave in the second bus system through a third access link;

[0092] The access link between the first AHB master and the first APB slave comprises the first access link and the second access link, and the AHB-APB bridges on the first access link and the second access link are the same or different.

[0093] In some embodiments, the device further comprises:

[0094] The writing module is configured in the first data bridge, and is used for, if the first access request is a write request, storing data of the first access request to the first data bridge, and then, if the first APB slave device is in an idle state, writing the data of the first access request to the first APB slave device.

[0095] The transmission module is configured in the first data bridge, and is used for, if the first access request is a read request, after sending an APB release signal to the first AHB master device, transmitting data of the first access request to the first AHB master device.

[0096] In some embodiments, if the first access request is a write request and the first APB slave device is in a busy state, the writing module is used for: determining a storage level of the data of the first access request based on a type of the data, different storage levels corresponding to different storage areas in the first data bridge, and different storage areas corresponding to different access performances; and storing the data to a storage area corresponding to the storage level of the data in the first data bridge.

[0097] In some embodiments, the writing module is used for: storing the data to a first storage area in the first data bridge based on the storage level of the data.

[0098] The device further includes a transfer module configured in the first data bridge, and used for predicting a state of the first APB slave device, and if a prediction result indicates that the first APB slave device will change from a busy state to an idle state within a preset time period, transferring the data from the first storage area to a second storage area in the first data bridge, the second storage area having a higher access performance than the first storage area.

[0099] In some embodiments, the device further includes a recording module configured in the first AHB master device, and used for recording execution information of an access request sent to the first APB slave device through different access links, the execution information including at least one of an execution duration and an execution success rate of the access request.

[0100] The second sending module 403 is configured to, after receiving the APB release signal, determine a second access link from a plurality of access links based on the execution information, and send a second access request to the first APB slave device through the second access link, the plurality of access links excluding the first access link.

[0101] In some embodiments, the first access link comprises the first arbiter, the first AHB-APB bridge and the second arbiter; sending the first access request to the first APB slave device in the second bus system through the first access link comprises: the first AHB master device sending the first access request to the first arbiter; the first arbiter arbitrating the received first access request and the fourth access request sent by the second AHB master device, and then sending the first access request to the second arbiter through the first AHB-APB bridge; and the second arbiter arbitrating the received first access request and the fifth access request sent by the third AHB master device, and then sending the first access request to the first data bridge.

[0102] In some embodiments, the first arbiter, the first AHB-APB bridge and the second arbiter all have a fault detection function, and the device further comprises a link switching module configured to, during the process of the first AHB master device sending the first access request to the first APB slave device through the first access link, if any one of the first arbiter, the first AHB-APB bridge and the second arbiter detects a fault in the first access link, switching the first access request to the fourth access link to send the first access request to the first APB slave device through the fourth access link, and the access link between the first AHB master device and the first APB slave device comprises the fourth access link.

[0103] In summary, in the data access device of the system on chip provided in the embodiments of the present application, for any one AHB master device in the system on chip, there are at least two access links between the AHB master device and any one APB slave device, and based on this, when the AHB master device sends an access request to the APB slave device through one of the access links, the data bridge connected to the APB slave device can temporarily store the data of the access request to release the APB bus in advance, so that the AHB master device can access the APB slave device through other access links, or access other APB slave devices, thereby improving the use efficiency and utilization rate of the bus in the system on chip.

[0104] It should be noted that the data access device of the system on chip provided in the above embodiments is used to perform data access of the system on chip, and only the division of the above functional modules is used as an example for illustration, and in actual application, the above functions can be completed by different functional modules according to needs, that is, the internal structure is divided into different functional modules to complete all or part of the functions described above. In addition, the data access device of the system on chip and the data access method of the system on chip provided in the above embodiments belong to the same concept, and the specific implementation process is described in detail in the method embodiments, which will not be described here.

[0105] Reference Figure 5 The embodiments of the present application also provide an electronic device, Figure 5is a structural schematic diagram of an electronic device provided by an embodiment of the present application. The electronic device 500 can have great differences due to different configurations or performances, and can include one or more processors (Central Processing Units, CPUs) 601 and one or more memories 502, where the memory 502 stores at least one piece of computer program, which is loaded and executed by the processor 501 to implement the data access method of the system on a chip provided by the above-mentioned method embodiments. Of course, the electronic device can also have a wired or wireless network interface, a keyboard, an input and output interface, and other components for realizing the functions of the device, and will not be described here.

[0106] An embodiment of the present application further provides a computer readable storage medium, which stores at least one piece of computer program, which is loaded and executed by a processor of an electronic device to implement the data access method of the system on a chip of the above-mentioned embodiments. For example, the computer readable storage medium can be a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a compact disc read-only memory (Compact Disc Read-Only Memory, CD-ROM), a magnetic tape, a floppy disk and an optical data storage device, etc.

[0107] An embodiment of the present application further provides a computer program product, which includes a computer program, and the computer program is loaded and executed by a processor to implement the data access method of the system on a chip as in the above-mentioned embodiments.

[0108] Those skilled in the art can understand that all or part of the steps of the above-mentioned embodiments can be completed by hardware, or by a program instructing related hardware to complete, and the program can be stored in a computer readable storage medium, and the above-mentioned storage medium can be a read-only memory, a magnetic disk or an optical disk, etc.

[0109] The above-mentioned is only an optional embodiment of the present application, and is not used to limit the present application, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method of data access for a system-on-chip, characterized by, The application is applied to a system on chip, which comprises a first bus system using an advanced high-performance bus (AHB) and a second bus system using an advanced peripheral bus (APB), the first bus system and the second bus system are connected through a plurality of AHB-APB bridges, there are at least two access links between each AHB master in the first bus system and each APB slave in the second bus system, each APB slave is connected with a data bridge, and the method comprises the following steps: A first AHB master in the first bus system sends a first access request to a first APB slave in the second bus system through a first access link; A first data bridge connected with the first APB slave receives the first access request, if the first access request is a write request and the first APB slave is in a busy state, stores data of the first access request to the first data bridge, and then sends an APB release signal to the first AHB master, or if the first access request is a read request, reads data of the first access request from the first APB slave and stores the read data to the first data bridge, and then sends an APB release signal to the first AHB master; After the first AHB master receives the APB release signal, the first AHB master sends a second access request to the first APB slave through a second access link, or sends a third access request to a second APB slave in the second bus system through a third access link; The access link between the first AHB master and the first APB slave comprises the first access link and the second access link, and the AHB-APB bridges on the first access link and the second access link are the same or different.

2. The method of claim 1, wherein, The method further comprises: If the first access request is a write request, after the first data bridge stores data of the first access request to the first data bridge, the first data bridge writes the data of the first access request to the first APB slave in the case that the first APB slave is in an idle state; If the first access request is a read request, after the first data bridge sends an APB release signal to the first AHB master, the first data bridge transmits data of the first access request to the first AHB master.

3. The method of claim 1, wherein, If the first access request is a write request and the first APB slave is in a busy state, after the first data bridge stores data of the first access request to the first data bridge, the first data bridge sends an APB release signal to the first AHB master, which comprises: The first data bridge determines a storage level of the data of the first access request based on the type of the data, different storage levels correspond to different storage areas in the first data bridge, and different storage areas correspond to different access performances; The first data bridge stores the data to the storage area corresponding to the storage level of the data in the first data bridge based on the storage level of the data.

4. The method of claim 3, wherein, The first data bridge stores the data to a storage area corresponding to the storage level of the data in the first data bridge based on the storage level of the data, including: The first data bridge stores the data to a first storage area in the first data bridge based on the storage level of the data. The method further includes: The first data bridge predicts the state of the first APB slave device, and if the prediction result indicates that the first APB slave device will change from the busy state to the idle state within a preset time period, the data is transferred from the first storage area to a second storage area in the first data bridge, and the access performance of the second storage area is higher than that of the first storage area.

5. The method of claim 1, wherein, The method further includes: The first AHB master device records execution information of the access request sent to the first APB slave device through different access links, and the execution information includes at least one of execution duration and execution success rate of the access request; After receiving the APB release signal, the first AHB master device sends a second access request to the first APB slave device through a second access link, including: After receiving the APB release signal, the first AHB master device determines the second access link from a plurality of access links based on the execution information, and sends the second access request to the first APB slave device through the second access link, and the plurality of access links do not include the first access link.

6. The method of claim 1, wherein, The first access link includes a first arbiter, a first AHB-APB bridge, and a second arbiter; the first AHB master device sends a first access request to the first APB slave device in the second bus system through the first access link, including: The first AHB master device sends the first access request to the first arbiter; After arbitrating the received first access request and a fourth access request sent by a second AHB master device, the first arbiter sends the first access request to the second arbiter through the first AHB-APB bridge; After arbitrating the received first access request and a fifth access request sent by a third AHB master device, the second arbiter sends the first access request to the first data bridge.

7. The method of claim 6, wherein, The first arbiter, the first AHB-APB bridge, and the second arbiter all have fault detection functions, and the method further includes: During the process that the first AHB master device sends the first access request to the first APB slave device through the first access link, if any one of the first arbiter, the first AHB-APB bridge, and the second arbiter detects a fault of the first access link, the node switches the first access request to a fourth access link to send the first access request to the first APB slave device through the fourth access link, and the access link between the first AHB master device and the first APB slave device includes the fourth access link.

8. A system on chip, characterized by The system on chip includes a first bus system adopting an advanced high-performance bus (AHB) and a second bus system adopting an advanced peripheral bus (APB), the first bus system and the second bus system are connected through a plurality of AHB-APB bridges, there are at least two access links between each AHB master in the first bus system and each APB slave in the second bus system, and each APB slave is connected with a data bridge; The first AHB master in the first bus system is configured to send a first access request to the first APB slave in the second bus system through a first access link; The first data bridge connected with the first APB slave is configured to receive the first access request, if the first access request is a write request and the first APB slave is in a busy state, store data of the first access request to the first data bridge, and then send an APB release signal to the first AHB master, or if the first access request is a read request, read data of the first access request from the first APB slave and store the read data to the first data bridge, and then send an APB release signal to the first AHB master; The first AHB master is further configured to send a second access request to the first APB slave through a second access link after receiving the APB release signal, or send a third access request to a second APB slave in the second bus system through a third access link; The access link between the first AHB master and the first APB slave includes the first access link and the second access link, and the AHB-APB bridges on the first access link and the second access link are the same or different.

9. An electronic device, comprising: The electronic device includes a memory and a processor, the memory stores at least one computer program, the at least one computer program is loaded and executed by the processor to implement the data access method of the system on chip as claimed in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores at least one computer program, the at least one computer program is loaded and executed by the processor to implement the data access method of the system on chip as claimed in any one of claims 1-7.

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