Airborne data processing unit architecture based on CPU and SOPC

Abstract

The invention provides an airborne data processing unit architecture based on a CPU (Central Processing Unit) and an SOPC (System On Programmable Chip), relates to the technical field of airborne bus interfaces, and solves the problem of limitation caused by purely increasing the number of CPUs in order to improve the data processing capability of an existing airborne embedded system. The architecture comprises a CPU (Central Processing Unit) processing unit group and an SOPC (System On Programmable Chip) processing unit group which are both connected to an external system Ethernet network; the CPU processing unit group and the SOPC processing unit group jointly form a data processing channel, and the data processing channel is used for data processing and data management of data chain type functions in the airborne platform; each CPU processing unit is connected to the SOPC processing unit group; each SOPC processing unit is connected to the SRIO exchange unit, and the SRIO exchange unit is used for providing data exchange capability and node expansion capability under the SRIO network for the SOPC processing unit group. According to the invention, the data processing and data management requirements of the airborne link function are smoothly met.

Description

Technical Field

[0001] The present invention relates to the technical field of airborne bus interfaces, and in particular to an airborne data processing unit architecture based on a CPU and SOPC. Background Art

[0002] In the modern information-based joint combat environment, the network-centric combat concept has led to the application of data link functions showing characteristics such as multi-channel, multi-network, multi-link and large data volume. These characteristics have put forward more stringent requirements on the data processing capabilities of airborne embedded systems. In order to meet this demand, the data processing tasks of avionics equipment are usually undertaken by specially designed data processing modules, which are responsible for processing the data of internal network, bus and point-to-point links, and realizing data management and forwarding functions.

[0003] Although traditional high-performance central processing units (CPUs) have powerful data processing capabilities, the types and number of interfaces they can directly support are limited. Simply increasing the number of CPUs will not only increase costs, but also lead to waste of resources. In addition, traditional CPUs often need to work in conjunction with field-programmable logic devices (FPGAs) to make up for the lack of interface scalability. In contrast, although system-on-chip (SOPC)-based devices are not as good as high-performance CPUs in processing performance, they can achieve flexible expansion of high-speed and low-speed interfaces through logic programming while ensuring a certain level of data processing capabilities, and have significant advantages in size and power consumption.

[0004] In view of the above situation, it is necessary to develop a new data processing unit architecture. This architecture aims to improve the reliability of hardware operation, enhance the flexibility of software deployment, and realize the functional expansion of the system while ensuring the hardware processing capability. It will provide good comprehensive operating characteristics, so as to better meet the complex requirements for data processing in information-based joint operations. Such a design will not only help optimize the performance of existing avionics systems, but also leave room for possible technological advances in the future, ensuring the long-term applicability and upgrade potential of the system. Summary of the invention

[0005] The purpose of the present invention is to solve the limitation problem caused by the simple increase of the number of CPUs in the existing airborne embedded systems to improve the data processing capability, and therefore proposes an airborne data processing unit architecture based on CPU and SOPC. The present invention has abundant high-speed interface resources, can support the communication of network-type and point-to-point business data at the same time, and can meet the data processing and data management requirements of airborne link functions; on the one hand, the architecture realizes the localization of software and hardware design; on the other hand, the architecture achieves a balance between the functional performance and power consumption volume of the data processing unit through the combination of CPU+SOPC. In addition, the architecture also expands the storage function, further improving its performance and advantages.

[0006] The present invention adopts the following technical solutions to achieve the purpose:

[0007] An airborne data processing unit architecture based on CPU and SOPC, the architecture comprises a CPU processing unit group and a SOPC processing unit group, both of which are connected to an external system Ethernet network through a connector; the CPU processing unit group and the SOPC processing unit group together constitute a data processing channel of the architecture, the data processing channel is used for data processing and data management of data link functions inside the airborne platform; each CPU processing unit in the CPU processing unit group is connected to the SOPC processing unit group; each SOPC processing unit in the SOPC processing unit group is connected to an SRIO switching unit, the SRIO switching unit is used to provide the SOPC processing unit group with data exchange capability and node expansion capability under the SRIO network.

[0008] The above architecture supports flexible deployment or dynamic reconstruction of the functional software of the airborne platform (such as multi-link management, take-off and landing chain, omnidirectional chain, embedded training chain, health management chain, etc.), provides comprehensive data processing resources for data link functions of avionics equipment, and realizes the processing, forwarding and management functions of different business data.

[0009] Furthermore, the CPU processing unit group includes 2 CPU processing units, each CPU processing unit includes a CPU processor, DDR, FLASH and RS232 interface; the CPU processor is used for processing SRIO network service data, DDR is used to provide a cache for software operation, FLASH is used to provide storage for embedded software (including BOOT, OS and APP here), and the RS232 interface is used as a debugging port.

[0010] Preferably, the main frequency and DDR capacity of the CPU processing unit group are higher than those of the SOPC processing unit group, so that it has stronger processing capabilities and can realize the processing of large-bandwidth data in the SRIO network. The two CPU processing units have a symmetrical circuit structure, and the power supply and clock of the two CPU processing units are independent of each other, so that they have higher reliability and security, and can run different functional software independently. Both CPU processing units are connected to the external system Ethernet network through a connector, which is used to process SRIO network-type business data at the same time, or for hot backup of core link functions, that is, when one of the CPU processing units fails, the function of the failed CPU processing unit is dynamically reconstructed by the other CPU processing unit.

[0011] Furthermore, the SOPC processing unit group is used to simultaneously complete the reception, sending and processing of SRIO network-type business data and GTX point-to-point business data. The SOPC processing unit group includes 2 SOPC processing units, each of which includes a SOPC chip, DDR, FLASH, EMMC and RS232 interface; DDR is used to provide cache for software operation, FLASH is used to provide storage for BOOT and OS in embedded software, EMMC is used to provide storage and capacity expansion for APP in embedded software, and the RS232 interface is used as a debugging port.

[0012] The processing capabilities of these two SOPC processing units are weaker than those of the CPU processing unit, but they can support the interaction of SRIO network data and GTX point-to-point data at the same time, and can expand LVCMOS, RS485 and other low-speed interfaces for discrete control and communication.

[0013] Preferably, the SOPC chip has a PS end and a PL end, and the DDR, FLASH, EMMC and RS232 interfaces are all mounted on the PS end, which together provide the data processing capability of the SOPC processing unit; in two SOPC processing units, the PS end of one of the SOPC processing units is also connected to the SRIO switching unit through an I2C interface, which can be used for the initialization configuration of the SRIO switching unit. The PL end of the SOPC chip in each SOPC processing unit implements the expansion of the SRIO, GTX, LVCMOS and RS485 interfaces through logic programming expansion, and exchanges data with other units in the architecture through these expansion interfaces.

[0014] Preferably, two SOPC processing units are interconnected via a GTX interconnect port, which is used to provide support for backup of business functions or direct data interaction in the SOPC processing units, so that the SOPC processing unit group can process more data types simultaneously and has stronger comprehensive capabilities.

[0015] Furthermore, both the CPU processing unit group and the SOPC processing unit group have corresponding SGMII Ethernet connections, and the implementation methods are all software implementations; wherein, each CPU processing unit in the CPU processing unit group is connected to one of the SOPC processing units in the SOPC processing unit group through the corresponding RGMII interface, and the SOPC processing unit implements the Ethernet protocol conversion from RGMII to SGMII through the PL end of its SOPC chip; each SOPC processing unit in the SOPC processing unit group implements the corresponding SGMII interface through the PL end of its own SOPC chip, and is connected to the external system Ethernet network through the SGMII interface, so that it can be used for debugging and online upgrades, and can also be used as an expansion of Ethernet services. This design architecture reduces the use of PHY, transformers, and Ethernet switching chips, and reduces hardware costs.

[0016] Furthermore, the SRIO switching unit has multiple SRIO ports. For each SOPC processing unit in the SOPC processing unit group, there is a corresponding SRIO port to establish a connection between it and the SRIO switching unit, and the remaining SRIO ports are connected to the external system Ethernet network; under the joint action of multiple SRIO ports, the SRIO switching unit realizes the port expansion, data transmission and reception and interaction functions of the SRIO network.

[0017] Furthermore, the architecture also includes a storage unit, which is connected to the connector via SRIO, GTX, RS232 and CAN interfaces, and is used for real-time data storage of input digital signals from the external system Ethernet network and key data of each unit in the architecture; the storage unit is also used to provide offline download and unloading support for stored data through the Gigabit Ethernet port.

[0018] The storage unit can be embedded in the architecture in the form of a subcard and can be flexibly selected. After assembly, the storage unit can record the SRIO business data, GTX business data, CAN bus maintenance data and RS232 debugging information in the avionics equipment in real time, and add a time stamp when recording. It can also download offline data after the mission is completed, and form a data spectrum based on the mission profile, which is convenient for analyzing the equipment function, equipment operation status and possible faults.

[0019] Furthermore, the architecture also includes a health management unit, which is connected to the storage unit, the CPU processing unit group and the SOPC processing unit group through the UART serial port at the same time. The health management unit is used to monitor the status of the remaining units in the architecture, collect the corresponding temperature and voltage data, and collect discrete states through the GPIO interface, and collect BIT information of the remaining units through the UART serial port; the health management unit is also connected to the connector through the CAN bus to realize communication and data interaction with the Ethernet network of the external system.

[0020] The health management unit can include an MCU chip, a temperature sensor, and an AD sampling circuit, etc., to achieve module-level unit health management. It collects the temperature, voltage, and discrete state of each unit, and connects to two SOPC processing units, two CPU processing units, and a storage unit through a UART serial port to obtain the detailed working status of each part of the unit, and frames all the data, and reports it to an external management and maintenance node through a CAN maintenance bus. It also supports BIT query, electronic tag query, and online upgrade instructions issued by the external management and maintenance node.

[0021] In summary, due to the adoption of this technical solution, the beneficial effects of the present invention are as follows:

[0022] The architecture of the present invention adopts two CPU processing units and two SOPC processing units to jointly constitute a general data processing resource, and uses the SRIO high-speed bus to form the backbone network of the processing architecture, which can realize interconnection and port expansion with other SRIO network nodes inside the device. The functional software can run independently and can also be dynamically reconstructed, so that the present invention has strong versatility and flexibility.

[0023] The architecture of the present invention organically combines the CPU processing unit and the SOPC processing unit together, and provides the processing capability for GTX point-to-point high-speed data, LVCMOS, and RS485 low-speed signals on the basis of ensuring high-speed data processing of the SRIO network, and can adapt to the data processing requirements of various data link functions, so it has strong comprehensive processing capabilities.

[0024] The architecture of the present invention also has a high degree of integration. The architecture integrates the CPU processing unit, SOPC processing unit, SRIO switching unit, health management unit and storage unit into one module, and realizes the expansion of the CPU processing unit SGMII network port and SRIO, GTX and other interfaces by programming the SOPC processing unit, reducing the use of PHY chips and programmable logic devices, thereby further compressing the physical volume and avoiding the waste of resources to a certain extent.

[0025] The architecture of the present invention realizes the node expansion of the system SRIO network through the SRIO switching unit and the expansion of the system data recording function through the storage unit on the basis of ensuring the data processing capability, which provides convenience for the design of the system architecture; moreover, the storage unit is embedded in the architecture in the form of a sub-card, which can be flexibly selected, and a dedicated data processing sub-card can be developed based on the existing sub-card interface definition in the future, so as to further expand the data processing capability and related system functions of the architecture. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a schematic diagram of the architecture of the airborne data processing unit of the present invention;

[0027] Figure 2 A schematic diagram of the application architecture of the airborne data processing unit in an embodiment of the present invention;

[0028] Figure 3 A typical application diagram of a data processing module using the airborne data processing unit of the present invention in a system;

[0029] Figure 4 Reason Figure 3 Schematic diagram of the data processing resource pool-level architecture composed of the data processing modules in . DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0031] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] Example

[0033] like Figure 1 As shown, this embodiment provides an airborne data processing unit architecture based on CPU and SOPC, which is targeted at airborne avionics equipment and provides data processing resources for its data link functions.

[0034] Figure 1In the invention, the architecture includes a CPU processing unit group and a SOPC processing unit group, both of which are connected to an external system Ethernet network through a connector; the CPU processing unit group and the SOPC processing unit group together constitute a data processing channel of the architecture, and the data processing channel is used for data processing and data management of data link functions within the airborne platform; each CPU processing unit in the CPU processing unit group is connected to the SOPC processing unit group; each SOPC processing unit in the SOPC processing unit group is connected to the SRIO switching unit, and the SRIO switching unit is used to provide the SOPC processing unit group with data exchange capability and node expansion capability under the SRIO network.

[0035] As a preferred embodiment of this embodiment, the CPU processing unit group includes 2 CPU processing units, each CPU processing unit includes a CPU processor, DDR, FLASH and RS232 interface; the CPU processor is used for processing SRIO network service data, DDR is used to provide a cache for software operation, FLASH is used to provide storage for embedded software, and the RS232 interface is used as a debugging port.

[0036] Correspondingly, the SOPC processing unit group is used to simultaneously complete the sending, receiving and processing of SRIO network business data and GTX point-to-point business data. The SOPC processing unit group includes 2 SOPC processing units, each of which includes a SOPC chip, DDR, FLASH, EMMC and RS232 interface; DDR is used to provide cache for software operation, FLASH is used to provide storage for BOOT and OS in embedded software, EMMC is used to provide storage and capacity expansion for APP in embedded software, and the RS232 interface is used as a debugging port.

[0037] This embodiment will take the specific unit model used as an example to introduce the above-mentioned architecture composition and connection relationship in detail, that is, Figure 1 The architecture shown corresponds to Figure 2 The application architecture diagram is shown in FIG. Among them, each CPU processing unit in the CPU processing unit group is Figure 2 The FT processing unit is in the middle; and each SOPC processing unit in the SOPC processing unit group is in Figure 2 The FMQL processing unit is in the middle.

[0038] like Figure 2 As shown, it is an airborne data processing unit architecture based on CPU and SOPC, mainly composed of 2 FT processing units, 2 FMQL processing units, SRIO switching units, storage units and health management units.

[0039] In this embodiment, the two FT processing units adopt a symmetrical design, and their power supplies and clocks are completely independent. Each FT processing unit is composed of an FT-2000 / 4 processor, DDR, FLASH, RS232, and a PCIE to SRIO bridge chip. Among them, FT-2000 / 4 is a quad-core CPU processor with a main frequency of 2.2GHz; DDR is configured as 2GB with ECC check, which is used for program running cache; FLASH capacity is 1Gbit, which is used to store software programs (BOOT, OS and APP); RS232 interface is used as a debugging port; PCIE to SRIO bridge chip is used to realize the PCIE interface of the FT-2000 / 4 processor to SRIO interface, so that the FT processing unit can access the SRIO network. SRIO adopts 1X mode, the rate is configurable, and the maximum support is 5Gbps, which can complete the data link function processing of the SRIO network.

[0040] In this embodiment, the two FMQL processing units also basically adopt a symmetrical design, and each FMQL processing unit is composed of a FMQL45T900 chip, DDR, FLASH, RS232 and EMMC. Among them, the PS end performance of the FMQL45T900 chip is equivalent to a 4-core CPU processor with a main frequency of 766MHz; the DDR is configured to 1GB, which is used for program running cache; the FLASH capacity is 256Mb, which is used to store the bottom layer of embedded software (BOOT and OS); the EMMC has a capacity of 32GB, which is used to store the application program (APP) of the embedded software, and can also be used to expand the business data generated in the storage system; the RS232 interface is used as a debugging port on the PS end.

[0041] The PL side of the FMQL45T900 chip is equivalent to a programmable logic device. Through logic software programming, the chip can output SRIO, GTX high-speed interfaces and RS422, LVCMOS low-speed interfaces. It can simultaneously realize the interaction, processing and management of SRIO network data, GTX point-to-point data, and low-speed interface data. Among them, SRIO adopts 1X mode, the rate is configurable, and the maximum support is 5Gbps; GTX adopts 1X mode, and the rate is configured to 1Gbps. RS422 and LVCMOS can be used for low-speed UART serial communication and discrete line control, which can be flexibly configured.

[0042] The SGMII Ethernet ports of the two FMQL45T900 chips are also implemented through logic software programming. At the same time, the RGMII interfaces of the FT-2000 / 4 processors in the two FT processing units are connected to the FMQL-1 processing unit, thereby realizing the protocol conversion from RGMII to SGMII; finally, four SGMII network ports are connected to the external system Ethernet network through high-speed connectors, which can be used for online upgrades and debugging of program software; if necessary in actual applications, they can also be expanded into a business network to exchange data through the Ethernet network.

[0043] In this embodiment, the FMQL-1 processing unit is also connected to the chip of the SRIO switching unit through the I2C interface, and can be used for initialization configuration of the SRIO switching network.

[0044] The SRIO switching unit is composed of the SRIO switching chip, which is internally connected to two FMQL processing units and can be expanded to form multiple SRIO ports externally, thus realizing both the interaction of SRIO network data and the expansion of SRIO ports.

[0045] In this embodiment, the storage unit is composed of a storage daughter card with a storage capacity of 1TB. It can record the data on the SRIO interface, GTX interface, CAN bus and RS232 debugging interface during the operation of the equipment in real time. After the task is completed, it can be connected to a PC through the Gigabit Ethernet port for data download and unloading, which is used to analyze the key indicators and possible problems of the equipment during the task.

[0046] In this embodiment, the health management unit is composed of an MCU chip, FLASH and a temperature sensor, etc., which are used to collect the voltage, temperature and discrete state corresponding to each unit. It is also connected to two FT processing units, two FMQL processing units and a storage unit through the UART serial port. The health management unit obtains the status information of each unit through serial port communication. A health management program runs on its MCU chip, which is responsible for framing the collected information and reporting it to the control management unit of the external system through the CAN bus. It also supports online upgrades, electronic tag queries, maintenance log issuance and other instructions issued by the control management unit.

[0047] Example 2

[0048] On the basis of Example 1, Figure 3 As shown, this embodiment introduces the interconnection architecture used in avionics equipment after applying the airborne data processing unit architecture. Figure 3In the figure, the main control module is the management and control core of the entire SRIO network. The two FT processing units and the storage unit in the data processing module are directly connected to the SRIO switching unit of the main control module. The two FMQL processing units are cascaded to the SRIO switching unit of the main control module through the SRIO switching unit inside the data processing module. This achieves the expansion of the number of nodes in the entire SRIO network and can support more SRIO node networking.

[0049] In this embodiment, two FT processing units are used to run the link management function, which uniformly processes, interacts, and distributes all data link function data in the device, ensuring that all data link operations will not conflict, become disordered, or fail. The entire link has a large amount of data, high test requirements, and high requirements for hardware processing capabilities, and has the highest operating priority and importance.

[0050] During normal operation, this function is deployed on the FT-1 processing unit, which has higher reliability in principle due to its independent power supply. The FT-2 processing unit implements keep-alive monitoring on the working status of the FT-1 processing unit and runs non-core link functions at the same time; when the FT-1 processing unit is found to be abnormal, the network processing unit of the main control module will control the FT-2 processing unit to deconstruct the non-core functions that were originally running, and reconstruct the link management function to the FT-2 processing unit to ensure that the system continues to operate normally.

[0051] In this embodiment, see Figure 3 ,Functional module 1 is connected to the SRIO network through the SRIO interface, and its data is processed locally by the FMQL-1 processing unit, while reporting the link management function for system management and performing discrete control of some link functions through the low-speed interface.

[0052] In this embodiment, see Figure 3 , Functional module 2 is interconnected with the FMQL-2 processing unit through the GTX interface and is processed by it. At the same time, the FMQL-2 processing unit converts the GTX data into SRIO data and reports it to the link management software for system management.

[0053] In this embodiment, the storage unit records the data of the SRIO, GTX and CAN buses in real time.

[0054] Figure 4 Based on the interconnection architecture of this embodiment, a data processing resource pool architecture is provided to meet the needs of higher processing capabilities in the future, which consists of n Figure 3The data processing module shown in the figure, after being connected to the SRIO network, can form a data processing resource consisting of 2n FT processing units and 2n FMQL processing units, further expanding the data processing capability of the system, enabling the interconnection of more functions and data, and improving the battlefield situation awareness capability of the equipment.

Claims

1. An airborne data processing unit architecture based on CPU and SOPC, characterized by: The architecture includes a CPU processing unit group and a SOPC processing unit group, both of which are connected to an external system Ethernet network through a connector; the CPU processing unit group and the SOPC processing unit group together constitute a data processing channel of the architecture, and the data processing channel is used for data processing and data management of data link functions within the airborne platform; each CPU processing unit in the CPU processing unit group is connected to the SOPC processing unit group; each SOPC processing unit in the SOPC processing unit group is connected to the SRIO switching unit, and the SRIO switching unit is used to provide the SOPC processing unit group with data exchange capabilities and node expansion capabilities under the SRIO network.

2. The airborne data processing unit architecture according to claim 1, characterized in that: The CPU processing unit group includes 2 CPU processing units, each of which includes a CPU processor, DDR, FLASH and RS232 interface; the CPU processor is used for processing SRIO network service data, DDR is used to provide a cache for software operation, FLASH is used to provide storage for embedded software, and the RS232 interface is used as a debugging port.

3. The airborne data processing unit architecture according to claim 2, characterized in that: The main frequency and DDR capacity of the CPU processing unit group are higher than those of the SOPC processing unit group; the two CPU processing units have a symmetrical circuit structure, and the power supply and clock of the two CPU processing units are independent of each other; the two CPU processing units are connected to the external system Ethernet network through a connector, which is used to simultaneously process SRIO network-type business data, or for hot backup of core link functions, that is, when one of the CPU processing units fails, the other CPU processing unit dynamically reconstructs the function of the failed CPU processing unit.

4. The airborne data processing unit architecture according to claim 1, characterized in that: The SOPC processing unit group is used to simultaneously complete the reception, sending and processing of SRIO network business data and GTX point-to-point business data. The SOPC processing unit group includes 2 SOPC processing units, each of which includes a SOPC chip, DDR, FLASH, EMMC and RS232 interface; DDR is used to provide cache for software operation, FLASH is used to provide storage for BOOT and OS in embedded software, EMMC is used to provide storage and capacity expansion for APP in embedded software, and the RS232 interface is used as a debugging port.

5. The airborne data processing unit architecture according to claim 4, characterized in that: The SOPC chip has a PS end and a PL end. The DDR, FLASH, EMMC and RS232 interfaces are all mounted on the PS end, which together provide the data processing capability of the SOPC processing unit. Among the two SOPC processing units, the PS end of one of the SOPC processing units is also connected to the SRIO switching unit through an I2C interface. The PL end of the SOPC chip in each SOPC processing unit realizes the expansion of SRIO, GTX, LVCMOS and RS485 interfaces through logic programming expansion, and exchanges data with other units in the architecture through these expansion interfaces.

6. The airborne data processing unit architecture according to claim 5, characterized in that: The two SOPC processing units are interconnected via a GTX interconnection port, and the GTX interconnection port is used to provide support for backup of business functions or direct data interaction in the SOPC processing unit.

7. The airborne data processing unit architecture according to claim 1, characterized in that: Both the CPU processing unit group and the SOPC processing unit group have corresponding SGMII Ethernet connections, and the implementation methods are all software implementation; wherein, each CPU processing unit in the CPU processing unit group is connected to one of the SOPC processing units in the SOPC processing unit group through the corresponding RGMII interface, and the SOPC processing unit implements the Ethernet protocol conversion from RGMII to SGMII through the PL end of its SOPC chip; each SOPC processing unit in the SOPC processing unit group independently implements the corresponding SGMII interface through the PL end of its own SOPC chip, and is connected to the external system Ethernet network through the SGMII interface.

8. The airborne data processing unit architecture according to claim 1, characterized in that: The SRIO switching unit has multiple SRIO ports. For each SOPC processing unit in the SOPC processing unit group, there is a corresponding SRIO port to establish a connection between it and the SRIO switching unit, and the remaining SRIO ports are connected to the external system Ethernet network. Under the joint action of multiple SRIO ports, the SRIO switching unit realizes the port expansion, data transmission and reception, and interaction functions of the SRIO network.

9. The airborne data processing unit architecture according to claim 1, characterized in that: The architecture also includes a storage unit, which is connected to the connector via SRIO, GTX, RS232 and CAN interfaces, and is used for real-time data storage of input digital signals of the external system Ethernet network and key data of each unit in the architecture; the storage unit is also used to provide offline download and unloading support for stored data through the Gigabit Ethernet port.

10. The airborne data processing unit architecture according to claim 9, characterized in that: The architecture also includes a health management unit, which is connected to the storage unit, the CPU processing unit group and the SOPC processing unit group through the UART serial port. The health management unit is used to monitor the status of the remaining units in the architecture, collect the corresponding temperature and voltage data, and collect discrete states through the GPIO interface and BIT information of the remaining units through the UART serial port. The health management unit is also connected to the connector through the CAN bus to realize communication and data interaction with the Ethernet network of the external system.

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