A near-memory computing system based on heterogeneous storage and a control method thereof

Abstract

The application discloses a near-memory computing system based on heterogeneous storage and a control method thereof. The system comprises a static random access memory, a magnetic random access memory, a control unit and a computing cluster module. The static random access memory and the magnetic random access memory constitute a heterogeneous memory, and the computing cluster module comprises a plurality of processing units, and the processing units adopt a circuit multiplexing design. The method comprises the following steps: determining a working mode of the near-memory computing system and obtaining input data and weight data from the heterogeneous memory; according to the working mode of the near-memory computing system, transmitting the input data and the weight data to the computing cluster; and based on the computing cluster, performing near-memory operation on the input data and the weight data to obtain a near-memory computing result. The embodiment of the application can avoid unnecessary data moving operation, thereby improving the computing efficiency of the system and reducing the power consumption, thereby saving the circuit resources. The application can be widely applied to the technical field of computer architecture.

Description

Technical Field

[0001] This application relates to the field of computer architecture technology, and in particular to a near-memory computing system based on heterogeneous storage and its control method. Background Technology

[0002] With the rapid development of information processing and artificial intelligence technologies, the demand for computing power is also growing rapidly. The von Neumann architecture, when performing calculations, requires constantly moving data from memory to the arithmetic logic unit (ALU) and then back to memory. This computing paradigm is not only inefficient but also consumes enormous amounts of power, making von Neumann-based processor systems unable to meet the increasing computing power demands. Near-memory computing, a new computing paradigm developed in recent years, places memory and computing units together at the chip layout and architecture level, greatly reducing data movement, lowering power consumption, and significantly improving computing efficiency. However, near-memory computing currently faces challenges such as limited computational types and difficulty in universalizing memory structures. Furthermore, current near-memory computing technologies are mostly circuit-level, requiring secondary optimization across different process nodes, making them difficult to universally apply. Meanwhile, FFT (Fast Fourier Transform) and CNN (Convolutional Neural Network), as core computational methods in signal processing and artificial intelligence respectively, are widely used in radar signal processing, target recognition, and text analysis. However, traditional scholars usually design and optimize the two computations separately. Their dedicated FFT or CNN accelerators usually occupy a lot of circuit resources in the chip, which will increase power consumption.

[0003] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the Invention

[0004] The main objective of this application is to propose a near-memory computing system and its control method based on heterogeneous storage, which can avoid unnecessary data transfer operations, thereby improving the system's computing efficiency and reducing power consumption, thus saving circuit resources.

[0005] To achieve the above objectives, one aspect of this application proposes a near-memory computing system based on heterogeneous storage. The system includes a static random access memory (SRAM), a magnetic random access memory (MRM), a control unit, and a computing cluster module. The SRAM and the MRM constitute a heterogeneous memory. The computing cluster module includes several processing units, which employ a circuit multiplexing design. The output terminal of the SRAM is connected to a first input terminal of the computing cluster module, and the first output terminal of the computing cluster module is connected to the input terminal of the SRAM. The second output terminal of the computing cluster module is connected to a first input terminal of the control unit, and the first output terminal of the control unit is connected to a second input terminal of the computing cluster module. The second output terminal of the control unit is connected to an input terminal of the MRAM, and the output terminal of the MRAM is connected to a second input terminal of the control unit. Wherein:

[0006] The static random access memory is used to store the input data of the computing cluster module;

[0007] The magnetic random access memory is used to store the weight data of the computing cluster module;

[0008] The control unit is used to control the data transmission between the magnetic random access memory and the computing cluster module;

[0009] The computing cluster module is used to perform three-level operations based on the input data and the weight data to obtain near-memory computing results, thereby realizing the acceleration function of the accelerator.

[0010] In some embodiments, the equivalent circuit model of the computing cluster module includes a first-stage multiplication unit, a second-stage addition unit, a third-stage butterfly unit, a first multiplexer, and a second multiplexer, wherein:

[0011] The first-level multiplication unit is used to perform multiplication operations;

[0012] The second-level addition unit is used to perform addition operations;

[0013] The third-level butterfly operation unit is used to perform butterfly operation;

[0014] The first multiplexer and the second multiplexer are used to select corresponding data according to different calculation modes.

[0015] In some embodiments, the first-level multiplication unit includes a first multiplier, a second multiplier, a third multiplier, and a fourth multiplier; the second-level addition unit includes a first adder and a second adder; and the third-level butterfly operation unit includes a third adder, a fourth adder, a fifth adder, and a sixth adder.

[0016] In some embodiments, the outputs of the first multiplier and the second multiplier are both connected to the input of the first adder; the outputs of the third multiplier and the fourth multiplier are both connected to the input of the second adder; the output of the first adder is connected to the first input of the third adder and the first input of the fourth adder, respectively; the output of the first multiplexer is connected to the second input of the third adder and the second input of the fourth adder, respectively; the output of the fourth adder is connected to the input of the first multiplexer; the output of the second adder is connected to the first input of the fifth adder and the first input of the sixth adder, respectively; the output of the first multiplexer is connected to the second input of the fifth adder and the second input of the sixth adder, respectively; and the output of the fifth adder is connected to the input of the second multiplexer.

[0017] To achieve the above objectives, another aspect of this application proposes a control method for a near-memory computing system based on heterogeneous storage, the control method comprising the following steps:

[0018] Determine the operating mode of the near-memory computing system and obtain input data and weight data from heterogeneous memory;

[0019] According to the working mode of the near-memory computing system, the input data and the weight data are transmitted to the computing cluster;

[0020] Based on the computation cluster, a near-memory operation is performed on the input data and the weight data to obtain the near-memory computation result.

[0021] In some embodiments, the operating modes of the near-memory computing system include a fast Fourier transform operating mode and a convolutional neural network operating mode.

[0022] In some embodiments, the step of performing a near-memory operation on the input data and the weight data based on the computing cluster to obtain a near-memory computation result includes:

[0023] Based on the computing cluster, a first-level multiplication operation is performed on the input data and the weight data to obtain the product operation result;

[0024] Perform a second-level addition operation on the product result to obtain the sum of the addition operations;

[0025] The third-level butterfly operation is performed on the sum of the addition operations to obtain the near-memory calculation result.

[0026] In some embodiments, the first multiplication operation includes:

[0027] If the near-memory computing system operates in Fast Fourier Transform mode, then the input data is represented as first sampled signal data and second sampled signal data, and the weight data is represented as a rotation factor.

[0028] The real part of the second sampled signal data is multiplied by the real part of the rotation factor using the first multiplier to obtain the first multiplication result;

[0029] The imaginary part of the second sampled signal data is multiplied by the imaginary part of the rotation factor using the second multiplier to obtain the second multiplication result.

[0030] The imaginary part of the second sampled signal data is multiplied by the real part of the rotation factor using a third multiplier to obtain the third multiplication result.

[0031] The real part of the second sampled signal data is multiplied by the imaginary part of the rotation factor using the fourth multiplier to obtain the fourth multiplication result;

[0032] By combining the first multiplication result, the second multiplication result, the third multiplication result, and the fourth multiplication result, the product operation result of the fast Fourier transform working mode is obtained;

[0033] If the working mode of the near-memory computing system is a convolutional neural network working mode, then the input data is represented as the first operand, the second operand, the third operand, and the fourth operand, and the weight data is represented as the fifth operand, the sixth operand, the seventh operand, and the eighth operand.

[0034] The first multiplier performs a multiplication calculation on the first operand and the fifth operand to obtain the fifth multiplication result;

[0035] The second multiplier performs a multiplication calculation on the second operand and the sixth operand to obtain the sixth multiplication result;

[0036] The third multiplier multiplies the third operand and the seventh operand to obtain the seventh multiplication result.

[0037] The fourth multiplier multiplies the fourth operand and the eighth operand to obtain the eighth multiplication result.

[0038] By combining the results of the fifth, sixth, seventh, and eighth multiplication operations, the product operation result of the convolutional neural network working mode is obtained.

[0039] In some embodiments, the second-level addition operation includes:

[0040] If the operating mode of the near-memory computing system is Fast Fourier Transform (FST) mode;

[0041] The first adder subtracts the first multiplication result from the second multiplication result to obtain the first addition result.

[0042] The second adder adds the third multiplication result to the fourth multiplication result to obtain the second addition result.

[0043] By combining the first addition result with the second addition result, the addition result of the fast Fourier transform operating mode is obtained;

[0044] If the working mode of the near-memory computing system is the convolutional neural network working mode;

[0045] The first adder adds the fifth multiplication result to the sixth multiplication result to obtain the third addition result.

[0046] The result of the seventh multiplication is added to the result of the eighth multiplication by the second adder to obtain the result of the fourth addition operation;

[0047] By combining the result of the third addition operation with the result of the fourth addition operation, the addition operation result of the working mode of the convolutional neural network is obtained.

[0048] In some embodiments, the third-level butterfly operation includes:

[0049] If the near-memory computing system operates in Fast Fourier Transform mode, the first sampled signal data is obtained through the first multiplexer and the second multiplexer.

[0050] The real part of the first sampled signal data is obtained by subtracting the result of the first addition operation from the real part of the first sampled signal data through the third adder.

[0051] The real part of the first sampled signal data is added to the first sum by the fourth adder to obtain the real part of the sum.

[0052] The imaginary part of the first sampled signal data is added to the result of the second addition operation by the fifth adder to obtain the imaginary part of the subtraction operation result;

[0053] The imaginary part of the sum is obtained by subtracting the result of the second addition operation from the imaginary part of the first sampled signal data using the sixth adder.

[0054] By combining the real part of the subtraction result, the imaginary part of the subtraction result, the real part of the addition result, and the imaginary part of the addition result, the calculation result of the accelerator in the Fast Fourier Transform operating mode is obtained.

[0055] If the working mode of the near-memory computing system is the convolutional neural network working mode, then the output data of the fourth adder is selected by the first multiplexer, and the output data of the fifth adder is selected by the second multiplexer.

[0056] The first addition result is accumulated with the output data of the fourth adder by the fourth adder to obtain the first accumulation result;

[0057] The second addition result is accumulated with the output data of the fifth adder to obtain the second accumulation result;

[0058] By combining the first accumulation result and the second accumulation result, the calculation result of the accelerator in the working mode of the convolutional neural network is obtained.

[0059] The embodiments of this application include at least the following beneficial effects: This application provides a near-memory computing system and its control method based on heterogeneous storage. This scheme uses static random access memory and magnetic random access memory to form a heterogeneous memory. Through heterogeneous storage, not only can SRAM be used to meet the fast update requirements of input data in FFT / CNN calculation, but MRAM can also be used to significantly reduce the power consumption and area occupation of the circuit. Input data and weight data are acquired and the working mode of the near-memory computing system is determined. The input data and weight data are mapped to the computing cluster. The processing units in the computing cluster are connected by multiplexing. Data in SRAM and MRAM is directly transferred from memory to PE for calculation without writing to registers, eliminating a large number of data transfer operations, thereby improving computing efficiency and reducing power consumption, thus saving circuit resources. Finally, the input data and weight data are accumulated, thereby improving the operating efficiency of the system. Attached Figure Description

[0060] Figure 1 This is a schematic diagram of the structure of a near-memory computing system based on heterogeneous storage provided in an embodiment of this application;

[0061] Figure 2 This is a flowchart illustrating the steps of a control method for a near-memory computing system based on heterogeneous storage, provided in an embodiment of this application.

[0062] Figure 3 This is a schematic diagram of the circuit model structure of the PE in the computing cluster module provided in the embodiments of this application;

[0063] Figure 4 This is a schematic diagram of a three-level operation model in the Fast Fourier Transform working mode provided in the embodiments of this application;

[0064] Figure 5 This is a schematic diagram of a three-level operation model in the working mode of a convolutional neural network provided in this application embodiment;

[0065] Figure 6 This is a schematic diagram of a reusable PE production line provided in an embodiment of this application;

[0066] Figure 7 This is a schematic diagram of the three-level operation steps of the processing unit provided in the embodiments of this application. Detailed Implementation

[0067] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of systems and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0068] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various concepts, but unless otherwise stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words “if,” “when,” or “in response to a determination” as used herein may be interpreted as “when…” or “when…” or “in response to a determination.”

[0069] As used in this application, the terms "at least one", "multiple", "each", "any", etc., "at least one" includes one, two or more, "multiple" includes two or more, "each" refers to each of the corresponding multiples, and "any" refers to any one of the multiples.

[0070] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0071] Reference Figure 1 , Figure 1 This is a schematic diagram of a near-memory computing system based on heterogeneous storage provided in an embodiment of the present invention, referring to... Figure 1 The system includes a static random access memory (SRAM), a magnetic random access memory (MRM), a control unit, and a computing cluster module. The SRAM and MRM constitute a heterogeneous memory. The computing cluster module includes several processing units connected via multiplexing. The output of the SRAM is connected to the first input of the computing cluster module, and the first output of the computing cluster module is connected to the input of the SRAM. The second output of the computing cluster module is connected to the first input of the control unit, and the first output of the control unit is connected to the second input of the computing cluster module. The second output of the control unit is connected to the input of the MRM, and the output of the MRM is connected to the second input of the control unit. Wherein:

[0072] Static random access memory is used to store the input data of the computing cluster module;

[0073] Magnetic random access memory is used to store the weight data of the computation cluster module;

[0074] The control unit is used to control the data transmission between the magnetic random access memory and the computing cluster module;

[0075] The computation cluster module is used to perform three-level operations based on the input data and weight data to obtain near-in-memory computation results, thereby realizing the acceleration function of the accelerator.

[0076] In some specific embodiments, it should be noted that, in order to improve computational efficiency, a near-memory computing system based on heterogeneous storage was first designed, such as... Figure 1As shown, this system uses Static Random-Access Memory (SRAM) and Magnetic Random-Access Memory (MRAM) to form a heterogeneous memory. SRAM offers higher read / write flexibility and faster read / write speed, while MRAM is non-volatile, has high storage density, and low static power consumption. Meanwhile, the input data in FFT / CNN computation needs constant updating, while the weights are not updated or updated at a low frequency. Therefore, SRAM is used to store the input for FFT / CNN computation, and MRAM is used to store the weights. Through heterogeneous storage, not only can SRAM meet the need for rapid updates of input data in FFT / CNN computation, but MRAM can also significantly reduce circuit power consumption and area footprint. The near-memory computing system consists of four computation clusters, each containing 32 processing elements (PEs). Data in SRAM and MRAM is directly transferred from memory to the PEs for computation, eliminating the need to write to registers and avoiding numerous data transfer operations, thereby improving computational efficiency and reducing power consumption. Each computing cluster has a private data SRAM corresponding to it, while the MRAM is shared between clusters.

[0077] Furthermore, it should be noted that the equivalent circuit model of the computing cluster module includes a first-level multiplication unit, a second-level addition unit, a third-level butterfly operation unit, a first multiplexer, and a second multiplexer. The first-level multiplication unit is used to perform multiplication operations; the second-level addition unit is used to perform addition operations; the third-level butterfly operation unit is used to perform butterfly operations; and the first and second multiplexers are used to select the corresponding data according to different computing modes.

[0078] Furthermore, it should be noted that the first-level multiplication unit includes a first multiplier, a second multiplier, a third multiplier, and a fourth multiplier; the second-level addition unit includes a first adder and a second adder; and the third-level butterfly operation unit includes a third adder, a fourth adder, a fifth adder, and a sixth adder. The outputs of the first and second multipliers are connected to the input of the first adder; the outputs of the third and fourth multipliers are connected to the input of the second adder; and the output of the first adder is connected to the input of the third adder. The first input terminal of the first adder and the first input terminal of the fourth adder are connected. The output terminal of the first multiplexer is connected to the second input terminal of the third adder and the second input terminal of the fourth adder, respectively. The output terminal of the fourth adder is connected to the input terminal of the first multiplexer. The output terminal of the second adder is connected to the first input terminal of the fifth adder and the first input terminal of the sixth adder, respectively. The output terminal of the first multiplexer is connected to the second input terminal of the fifth adder and the second input terminal of the sixth adder, respectively. The output terminal of the fifth adder is connected to the input terminal of the second multiplexer.

[0079] The near-memory computing system includes the design of a physical process unit (PE), specifically a reusable PE design for FFT / CNN. FFT and CNN computations share significant commonalities, and most of their circuit structures can be reused through design, thus saving circuit resources. The designed FFT / CNN reusable processing unit is as follows: Figure 3 As shown, the circuit consists of three levels of arithmetic operations and two multiplexers (MUX). The three levels of arithmetic operations are multiplication, addition, and butterfly operations. In the first level of multiplication, there are four signed multipliers, each capable of multiplying two factors: the input data and the weight data. The input comes from SRAM, and the weights come from MRAM. The four multipliers output four products, which are then passed to the second level of arithmetic operations. In the second level of addition, there are two adders that add the results of the first level operations pairwise. The two adders output two sums, which are then passed to the third level of butterfly operations. In the third level of butterfly operations, there are four adders that add the results of the second level operations and the outputs of the MUX a second time. Depending on the computation mode, the MUX selects different data. In FFT mode, the MUX selects the external input operands; in CNN mode, the MUX selects the result of the butterfly operation. With pipeline support, accumulation operations can be achieved. Through the third-stage butterfly operation, the final FFT / CNN calculation result is output. In this design, negative numbers are represented using two's complement, thus enabling subtraction operations to be performed using adders.

[0080] Please see Figure 2 and Figure 7This application also provides a control method for a near-memory computing system based on heterogeneous storage, which can implement the above-mentioned near-memory computing system based on heterogeneous storage. The system includes:

[0081] S100: Determine the operating mode of the near-memory computing system and obtain input data and weight data from heterogeneous memory;

[0082] It should be noted that in some embodiments, the operating modes of the near-memory computing system include Fast Fourier Transform mode and Convolutional Neural Network mode.

[0083] In some specific embodiments, the instructions in the instruction SRAM are read out, and the input data and weight data are retrieved from the data SRAM and MRAM respectively according to the instructions and sent to the PE of the computing cluster to further determine the working mode of the near-memory computing system, which is divided into FFT mode and CNN mode.

[0084] S200: Based on the working mode of the near-memory computing system, the input data and weight data are transmitted to the computing cluster;

[0085] It should be noted that in some embodiments, the data transmitted to the PE is mapped according to different working modes.

[0086] S300: Based on the computing cluster, perform near-memory operations on the input data and weight data to obtain near-memory computation results.

[0087] It should be noted that in some embodiments, step S300 may include steps S310 to S330;

[0088] S310. Based on the computing cluster, perform the first-level multiplication operation on the input data and the weight data to obtain the product operation result;

[0089] Specifically, such as Figure 4 As shown, if the near-in-memory computing system operates in Fast Fourier Transform (FFT) mode, the input data is represented as first sampled signal data and second sampled signal data, and the weight data is represented as a rotation factor. The first multiplier multiplies the real part of the second sampled signal data with the real part of the rotation factor to obtain the first multiplication result. The second multiplier multiplies the imaginary part of the second sampled signal data with the imaginary part of the rotation factor to obtain the second multiplication result. The third multiplier multiplies the imaginary part of the second sampled signal data with the real part of the rotation factor to obtain the third multiplication result. The fourth multiplier multiplies the real part of the second sampled signal data with the imaginary part of the rotation factor to obtain the fourth multiplication result. Combining the first, second, third, and fourth multiplication results yields the product operation result in FFT mode.

[0090] In this embodiment, in FFT mode, the input data is a sampled signal, divided into real and imaginary parts; the weight data is a rotation factor, also divided into real and imaginary parts. Figure 4 In the diagram, X1 and X2 are sampled data, where X1 is the first sampled signal data and X2 is the second sampled signal data, and W is the rotation factor. In the multiplication operation, the real and imaginary parts of X2 are multiplied pairwise with the real and imaginary parts of W through a multiplier to obtain four products.

[0091] like Figure 5 As shown, if the near-in-memory computing system operates in convolutional neural network mode, the input data is represented as the first operand, the second operand, the third operand, and the fourth operand, and the weight data is represented as the fifth operand, the sixth operand, the seventh operand, and the eighth operand. The first multiplier multiplies the first operand and the fifth operand to obtain the fifth multiplication result; the second multiplier multiplies the second operand and the sixth operand to obtain the sixth multiplication result; the third multiplier multiplies the third operand and the seventh operand to obtain the seventh multiplication result; the fourth multiplier multiplies the fourth operand and the eighth operand to obtain the eighth multiplication result; combining the fifth, sixth, seventh, and eighth multiplication results yields the product operation result of the convolutional neural network operating mode.

[0092] In this embodiment, under CNN mode, the input data consists of four operands A1-A4, and the weight data consists of four operands W1-W4, where A1 represents the first operand, A2 represents the second operand, A3 represents the third operand, A4 represents the fourth operand, W1 represents the fifth operand, W2 represents the sixth operand, W3 represents the seventh operand, and W4 represents the eighth operand. In the multiplication operation, A1 is multiplied pairwise with W1, A2 with W2, A3 with W3, and A4 with W4, resulting in four products.

[0093] S320. Perform a second-level addition operation on the product result to obtain the sum of the addition operations;

[0094] Specifically, such as Figure 4 As shown, if the near-in-memory computing system operates in Fast Fourier Transform mode; the first adder subtracts the first multiplication result from the second multiplication result to obtain the first sum operation result; the second adder adds the third multiplication result from the fourth multiplication result to obtain the second sum operation result; combining the first sum operation result and the second sum operation result, the sum operation result of Fast Fourier Transform mode is obtained.

[0095] In this embodiment, in FFT mode, the first adder is used as a subtractor to subtract the second product from the first product; the second adder is used to add the third and fourth products.

[0096] like Figure 5 As shown, if the near-memory computing system operates in convolutional neural network mode; the first adder adds the result of the fifth multiplication calculation to the result of the sixth multiplication calculation to obtain the result of the third addition operation; the second adder adds the result of the seventh multiplication calculation to the result of the eighth multiplication calculation to obtain the result of the fourth addition operation; combining the result of the third addition operation and the result of the fourth addition operation, the result of the addition operation in convolutional neural network mode is obtained.

[0097] In this embodiment, in CNN mode, the four products are added pairwise.

[0098] S330. Perform the third-level butterfly operation on the addition and sum operation results to obtain the near-store calculation result.

[0099] Specifically, such as Figure 4 As shown, if the near-in-memory computing system operates in Fast Fourier Transform (FFT) mode, the first sampled signal data is acquired through a first multiplexer and a second multiplexer; the real part of the first sampled signal data is subtracted from the first sum operation result by a third adder to obtain the real part of the subtraction result; the real part of the first sum operation result is added to the real part of the first sampled signal data by a fourth adder to obtain the real part of the addition result; the imaginary part of the first sampled signal data is added to the second sum operation result by a fifth adder to obtain the imaginary part of the subtraction result; the imaginary part of the second sum operation result is subtracted from the imaginary part of the first sampled signal data by a sixth adder to obtain the imaginary part of the addition result; combining the real part of the subtraction result, the imaginary part of the subtraction result, the real part of the addition result, and the imaginary part of the addition result, the computation result of the accelerator in FFT mode is obtained.

[0100] In this embodiment, in FFT mode, MUX is used to select X1 and send it along with the result of the addition operation into the butterfly operation. The result of the addition operation is cross-added (subtracted) with X1 to obtain the final results Y1 and Y2, where Y1 represents the real part and imaginary part of the addition operation result, and Y2 represents the real part and imaginary part of the subtraction operation result.

[0101] like Figure 5As shown, if the near-memory computing system operates in convolutional neural network mode, the output data of the fourth adder is selected by the first multiplexer, and the output data of the fifth adder is selected by the second multiplexer. The first sum operation result is accumulated with the output data of the fourth adder to obtain the first accumulated operation result. The second sum operation result is accumulated with the output data of the fifth adder to obtain the second accumulated operation result. The first accumulated operation result and the second accumulated operation result are combined to obtain the computing result of the accelerator in convolutional neural network mode.

[0102] In this embodiment, in CNN mode, the MUX no longer selects the external input, but instead selects the output of the butterfly operation and retransmits it to the input of the butterfly operation. The current butterfly operation result is continuously added to the result of the next level addition operation, such as... Figure 6 As shown, with the support of the pipeline, the accumulation function is finally realized, and the accumulation results B1 and B2 are obtained, where B1 represents the first accumulation operation result and B2 represents the second accumulation operation result.

[0103] In summary, the computing system constructed in this embodiment of the invention can accelerate FFT and CNN calculations and can be applied to the field of radar signal processing. In radar signal processing stages such as clutter suppression and coherent accumulation, a large number of FFT calculations are required. After obtaining the range-Doppler image, CNN can be used for target recognition and tracking. Therefore, the computing system constructed in this invention can accelerate the core calculations in radar signal processing, improving the system's operating efficiency.

[0104] It is understood that the content of the above method embodiments is applicable to this system embodiment. The specific functions implemented in this system embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0105] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A near-memory computing system based on heterogeneous storage, characterized in that, The system includes a static random access memory (SRAM), a magnetic random access memory (MRM), a control unit, and a computing cluster module. The SRAM and the MRM constitute a heterogeneous memory. The computing cluster module includes several processing units, which employ a circuit multiplexing design. The output terminal of the SRAM is connected to the first input terminal of the computing cluster module, and the first output terminal of the computing cluster module is connected to the input terminal of the SRAM. The second output terminal of the computing cluster module is connected to the first input terminal of the control unit, and the first output terminal of the control unit is connected to the second input terminal of the computing cluster module. The second output terminal of the control unit is connected to the input terminal of the MRAM, and the output terminal of the MRAM is connected to the second input terminal of the control unit. Wherein: The static random access memory is used to store the input data of the computing cluster module; The magnetic random access memory is used to store the weight data of the computing cluster module; The control unit is used to control the data transmission between the magnetic random access memory and the computing cluster module; The computing cluster module is used to perform three-level operations based on the input data and the weight data to obtain near-memory computing results, thereby realizing the acceleration function of the accelerator. The equivalent circuit model of the computing cluster module includes a first-level multiplication unit, a second-level addition unit, a third-level butterfly operation unit, a first multiplexer, and a second multiplexer, wherein: The first-level multiplication unit is used to perform multiplication operations; The second-level addition unit is used to perform addition operations; The third-level butterfly operation unit is used to perform butterfly operation; The first multiplexer and the second multiplexer are used to select corresponding data according to different calculation modes, including fast Fourier transform mode and convolutional neural network mode.

2. The system according to claim 1, characterized in that, The first-level multiplication unit includes a first multiplier, a second multiplier, a third multiplier, and a fourth multiplier; the second-level addition unit includes a first adder and a second adder; and the third-level butterfly operation unit includes a third adder, a fourth adder, a fifth adder, and a sixth adder.

3. The system according to claim 2, characterized in that, The outputs of the first multiplier and the second multiplier are both connected to the input of the first adder. The outputs of the third multiplier and the fourth multiplier are both connected to the input of the second adder. The output of the first adder is connected to the first input of the third adder and the first input of the fourth adder, respectively. The output of the first multiplexer is connected to the second input of the third adder and the second input of the fourth adder, respectively. The output of the fourth adder is connected to the input of the first multiplexer. The output of the second adder is connected to the first input of the fifth adder and the first input of the sixth adder, respectively. The output of the second multiplexer is connected to the second input of the fifth adder and the second input of the sixth adder, respectively. The output of the fifth adder is connected to the input of the second multiplexer.

4. A control method for a near-memory computing system based on heterogeneous storage, applied to the system described in any one of claims 1 to 3, characterized in that, The control method includes the following steps: The operating mode of the near-memory computing system is determined and input data and weight data are obtained from heterogeneous memory. The operating modes of the near-memory computing system include a fast Fourier transform operating mode and a convolutional neural network operating mode. According to the working mode of the near-memory computing system, the input data and the weight data are transmitted to the computing cluster; Based on the computational cluster, a near-memory operation is performed on the input data and the weight data to obtain the near-memory computation result, including: Based on the computing cluster, a first-level multiplication operation is performed on the input data and the weight data to obtain the product operation result; Perform a second-level addition operation on the product result to obtain the sum of the addition operations; The third-level butterfly operation is performed on the sum of the addition operations to obtain the near-memory calculation result.

5. The method according to claim 4, characterized in that, The first-level multiplication operation includes: If the near-memory computing system operates in Fast Fourier Transform mode, then the input data is represented as first sampled signal data and second sampled signal data, and the weight data is represented as a rotation factor. The real part of the second sampled signal data is multiplied by the real part of the rotation factor using the first multiplier to obtain the first multiplication result; The imaginary part of the second sampled signal data is multiplied by the imaginary part of the rotation factor using the second multiplier to obtain the second multiplication result. The imaginary part of the second sampled signal data is multiplied by the real part of the rotation factor using a third multiplier to obtain the third multiplication result. The real part of the second sampled signal data is multiplied by the imaginary part of the rotation factor using the fourth multiplier to obtain the fourth multiplication result; By combining the first multiplication result, the second multiplication result, the third multiplication result, and the fourth multiplication result, the product operation result of the fast Fourier transform working mode is obtained; If the working mode of the near-memory computing system is a convolutional neural network working mode, then the input data is represented as the first operand, the second operand, the third operand, and the fourth operand, and the weight data is represented as the fifth operand, the sixth operand, the seventh operand, and the eighth operand. The first multiplier performs a multiplication calculation on the first operand and the fifth operand to obtain the fifth multiplication result; The second multiplier performs a multiplication calculation on the second operand and the sixth operand to obtain the sixth multiplication result; The third multiplier multiplies the third operand and the seventh operand to obtain the seventh multiplication result. The fourth multiplier multiplies the fourth operand and the eighth operand to obtain the eighth multiplication result. By combining the results of the fifth, sixth, seventh, and eighth multiplication operations, the product operation result of the convolutional neural network working mode is obtained.

6. The method according to claim 5, characterized in that, The second-level addition operation includes: If the operating mode of the near-memory computing system is Fast Fourier Transform (FSFT) mode; The first adder subtracts the first multiplication result from the second multiplication result to obtain the first addition result. The second adder adds the third multiplication result to the fourth multiplication result to obtain the second addition result. By combining the first addition result with the second addition result, the addition result of the fast Fourier transform operating mode is obtained; If the working mode of the near-memory computing system is the convolutional neural network working mode; The first adder adds the fifth multiplication result to the sixth multiplication result to obtain the third addition result. The result of the seventh multiplication is added to the result of the eighth multiplication by the second adder to obtain the result of the fourth addition operation; By combining the result of the third addition operation with the result of the fourth addition operation, the addition operation result of the working mode of the convolutional neural network is obtained.

7. The method according to claim 6, characterized in that, The third-level butterfly operation includes: If the near-memory computing system operates in Fast Fourier Transform mode, the first sampled signal data is obtained through the first multiplexer and the second multiplexer. The real part of the first sampled signal data is obtained by subtracting the result of the first addition operation from the real part of the first sampled signal data through the third adder. The real part of the first sampled signal data is added to the first sum by the fourth adder to obtain the real part of the sum. The imaginary part of the first sampled signal data is added to the result of the second addition operation by the fifth adder to obtain the imaginary part of the subtraction operation result; The imaginary part of the sum is obtained by subtracting the result of the second addition operation from the imaginary part of the first sampled signal data using the sixth adder. By combining the real part of the subtraction result, the imaginary part of the subtraction result, the real part of the addition result, and the imaginary part of the addition result, the calculation result of the accelerator in the Fast Fourier Transform operating mode is obtained. If the working mode of the near-memory computing system is the convolutional neural network working mode, then the output data of the fourth adder is selected by the first multiplexer, and the output data of the fifth adder is selected by the second multiplexer. The first addition result is accumulated with the output data of the fourth adder by the fourth adder to obtain the first accumulation result; The second addition result is accumulated with the output data of the fifth adder to obtain the second accumulation result; By combining the first accumulation result and the second accumulation result, the calculation result of the accelerator in the working mode of the convolutional neural network is obtained.

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