Simulation layout performance prediction and layout method for graph isomorphic network optimization

Abstract

The invention discloses a graph isomorphic network optimized simulation layout performance prediction and layout method, which comprises the following steps of: performing feature extraction on nodes and devices in different circuits according to a topological structure feature extraction method, and constructing an original graph data set according to the extracted features; preprocessing the original graph data set by adopting a graph filtering technology; building an improved graph isomorphic network model, wherein the model comprises two improved GIN convolution layers, a pooling layer and a predictor; performing end-to-end iterative training on the improved graph isomorphic network model until a maximum iteration standard is reached; and outputting an optimized circuit layout by using a simulated annealing framework as a layout method and taking the performance, the area and the line length of the performance prediction model as cost functions. Through the improved graph isomorphic network model, rapid and accurate prediction of layout performance after a circuit layout scheme is simulated is realized by using a machine learning technology, the method is used for simulating an annealing layout optimization process, and the quality and reliability of a final layout are improved.

Description

Technical Field

[0001] The present invention relates to the field of electronic design automation, and in particular to a simulation layout performance prediction and layout method for graph isomorphic network optimization. Background Art

[0002] With the continuous development of electronic devices and the increase in application demand, the design of analog integrated circuits (ICs) has become increasingly complex. Compared with digital IC design, the layout design of analog ICs is more flexible, with complex constraints, and the final design effect is significantly affected by factors such as geometric constraints and parasitic constraints, which usually requires higher technical requirements and experience accumulation in the design process of analog ICs. Therefore, it is difficult to directly apply the traditional automated design tools used for digital circuits to analog circuits, resulting in the current analog IC design still relying on a large amount of manual intervention, which not only increases the design cycle and cost, but also makes the design quality more uncertain. In order to improve the efficiency and automation level of analog IC design, the industry is exploring the use of advanced technologies such as artificial intelligence and machine learning, which can shorten the design cycle, reduce design costs, and improve the quality and reliability of the final layout without sacrificing circuit performance.

[0003] In the layout design of analog ICs, layout is usually a time-consuming and laborious process, and the effect of layout directly affects the key performance of analog ICs such as common-mode rejection ratio, gain, bandwidth and phase margin. Traditional layout optimization is mainly aimed at minimizing area and line length, and the evaluation of circuit performance depends on post-layout circuit simulation, including parasitic parameter extraction and simulation. Unsatisfactory performance will lead to iterative adjustments and return to the layout stage, while satisfactory performance will ultimately determine the layout results. This iterative process is time-consuming and depends on wiring, simulation settings and layout characteristics. The present invention is a method for predicting the impact of layout results on analog IC performance, bypassing the complex and time-consuming wiring, parameter extraction and simulation processes, directly predicting the post-simulation performance of various analog circuit layout schemes, and providing information for optimizers in analog layout design. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a simulation layout performance prediction and layout method for graph isomorphic network optimization in view of the defects in the prior art.

[0005] The technical solution adopted by the present invention to solve its technical problem is:

[0006] The present invention provides a method for predicting performance and layout of a simulated layout of a graph isomorphic network optimization, the method comprising the following steps:

[0007] Step 1: Extract features of nodes and devices in different circuits based on the method of extracting features from the topological structure, and construct the original graph dataset based on the extracted features;

[0008] Step 2: Use graph filtering technology to preprocess the original graph dataset, apply mathematical operators on the graph structure of the original graph dataset to modify its spectral characteristics, enhance specific features and filter outliers in the original graph dataset through graph filters, and obtain a special graph dataset;

[0009] Step 3: Build an improved graph isomorphism network model, which includes two improved GIN convolutional layers, a pooling layer and a predictor, and input the preprocessed special graph dataset into the improved graph isomorphism network model;

[0010] Step 4: Perform end-to-end iterative training on the improved graph isomorphic network model until the maximum iteration standard is reached to obtain a trained graph isomorphic network model;

[0011] Step 5: Use the simulated annealing framework as the layout method, use the trained graph isomorphism network model as the performance prediction, and use the performance of the performance prediction model as well as the area and line length as the cost function to output the optimized circuit layout.

[0012] Furthermore, the method of step 1 of the present invention specifically comprises:

[0013] Step 1.1: Calculate the feature vectors of nodes and devices. For each node feature, the device type and device position result are included; the device position result is defined as follows:

[0014]

[0015] For the edge from node j to node i, its features include the horizontal and vertical distances between the pins connecting the nodes, the pin type, and the net weight. The horizontal / vertical relative position (x i ,y i ) and the location result of device i (X i ,Y i ) Calculate the connected device d ij It is described by the horizontal / vertical distance between the pins;

[0016] Step 1.2: Perform independent hot encoding on the pin types of the devices in the circuit;

[0017] Step 1.3: Represent the hot encoding as a graph structure. The graph structure of the circuit G = (V, E) is defined by a set of vertices V and a set of edges E = {(v,u)|v,u∈V}. Each node V i ∈V represents each device and IO pin of the circuit, while the edge E represents the connection between devices;

[0018] Step 1.4: Formulate a multi-objective regression performance prediction problem; the formula for the multi-objective regression performance prediction problem is:

[0019]

[0020] Among them, the learning function θ(·) learns the representation vector that helps performance prediction Prediction performance of the entire circuit diagram Specified by the function ⊙, the parameter w is an adjustable parameter used to indicate the importance of different types of performance indicators.

[0021] Furthermore, in step 1.1 of the present invention, for each node, extracting its features also includes:

[0022] Device types, including PMOS, NMOS, resistors, and capacitors;

[0023] Pin types, including gate, drain, source, and substrate;

[0024] The subcircuit to which the device belongs, including differential pairs and loads;

[0025] Device location results.

[0026] Furthermore, the method of step 2 of the present invention specifically includes:

[0027] Mathematical operators are applied on the graph structure to modify its spectral characteristics, enhance specific features and filter outliers in the original graph data. The methods used include box plot method; graph filters are used to filter out pin nodes and retain device nodes to obtain a special graph dataset for the next step of network training.

[0028] Furthermore, the method of step 3 of the present invention specifically includes:

[0029] Step 3.1: The graph isomorphism network model includes two improved GIN convolutional layers, a pooling layer and a predictor;

[0030] Step 3.2: Learn device node features and edge features as graph-level embeddings and send them to the trainable predictor;

[0031] Step 3.3: An attention mechanism is used in the graph isomorphic network model to refine node features so that it can focus on important nodes; the output of the GIN convolutional layer is then concatenated and transformed, followed by global mean pooling to obtain a comprehensive graph-level representation;

[0032] Step 3.4: The predictor of the model includes a multi-layer perceptron MLP and a LeakyRelu layer.

[0033] Furthermore, in step 3.1 of the present invention, the improved GIN convolutional layer is specifically:

[0034] When node features are aggregated from the neighborhood of the node, the connection features are used to mine the topological information of the circuit. The feature vector of the connection features can be defined as:

[0035]

[0036] in, is a reducible linear transformation, F uv Refers to the edge e connecting device nodes u and v uv For each layer of the GIN convolutional layer, the feature vector z v The feature vector h of the neighbors connected to the central device node c superior;

[0037] The improved GIN weights multiple loss functions by considering the equal variance uncertainty of each task, and derives a multi-task loss function based on Gaussian likelihood maximization based on uniform uncertainty; let f W (x) is the output of a neural network with weight W for input x, and the following probability model is defined:

[0038]

[0039] Among them, σ is a trainable parameter representing the observation noise. In the case of multiple model outputs, the following multi-task likelihood values ​​are obtained:

[0040]

[0041] in, represents the loss of the kth output variable; σ k is a trainable parameter representing the k-th observation noise.

[0042] Furthermore, the method of step 4 of the present invention specifically includes:

[0043] Step 4.1: Use the preprocessed special graph dataset as the training set. First, give the training set {(X i ,Y i )|N=|X|,1≤i≤N}, where X i and Y i are the circuit diagram of the i-th circuit in the training data and the true value of the input data;

[0044] Step 4.2: The model is trained in an end-to-end iterative manner until the maximum number of iterations is reached; during each iteration, the output of the training set is calculated by the model in the feedforward direction;

[0045] Step 4.3: In performance evaluation, the loss function L(·) is defined as:

[0046]

[0047] Where m and n are the number of tasks and the mini-batch size;

[0048] Step 4.4: Adjust the trainable parameters of the model through supervised back-propagation to minimize the loss function L(·).

[0049] Furthermore, the method of step 5 of the present invention specifically includes:

[0050] Step 5.1: Initialize the simulated annealing framework and set the simulated annealing parameters, including temperature T and cooling rate α;

[0051] Step 5.2: Load the trained graph isomorphic network model to predict the performance of the circuit and calculate the cost function F of the layout result:

[0052] F=Area+Wirelength+G

[0053] Among them, Area is the area of ​​the circuit layout, Wirelength is the total length, and G is the performance prediction item;

[0054] Step 5.3: Evaluate whether the current layout scheme is accepted: If not, reduce the temperature T and disturb the circuit layout result, and return to step 5.2; if accepted, output the layout result.

[0055] The present invention provides a simulation layout performance prediction and layout system for graph isomorphic network optimization, comprising:

[0056] a memory for storing executable computer programs;

[0057] The processor is used to implement the above-mentioned simulation layout performance prediction and layout method for graph isomorphic network optimization when executing an executable computer program stored in the memory.

[0058] The present invention provides a computer-readable storage medium storing a computer program for implementing the above-mentioned simulation layout performance prediction and layout method for graph isomorphic network optimization when executed by a processor.

[0059] The beneficial effects produced by the present invention are:

[0060] 1. Improve design efficiency and accuracy, and directly predict performance. By introducing connection feature splicing and adaptive loss weighting mechanism, MGIN can directly predict the post-simulation performance under different layout schemes without actual layout and simulation. This bypasses the complex and time-consuming traditional wiring, parameter extraction and simulation steps, which not only improves the prediction accuracy, but also shortens the design cycle.

[0061] 2. Enhance the design quality and reliability. Considering the different performance requirements of different types of circuits, the present invention adopts a multi-task loss function based on Gaussian likelihood maximization with uniform uncertainty, which can simultaneously handle multiple regression targets with different units and scales. This feature ensures accurate prediction of various key performance indicators (such as common mode rejection ratio, phase margin, etc.), thereby improving the quality and reliability of the final product.

[0062] 3. Save costs and resources, and reduce manual intervention. Traditional analog IC design is highly dependent on engineers’ experience and technical accumulation, and is often accompanied by high uncertainty. The present invention reduces the requirements for professional skills and the degree of manual participation through the application of automated performance prediction and layout optimization tools, thus effectively controlling labor costs.

[0063] 4. Easy operation, easy integration and expansion. The method provided by the present invention can be easily integrated into the existing EDA tool chain, providing users with a friendly interface and support. At the same time, the technical framework has good versatility and flexibility, and can be applied to more types of circuit designs in the future, and even supports transfer learning to adapt to different application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] The present invention will be further described below with reference to the accompanying drawings and embodiments, in which:

[0065] Figure 1 An example of a circuit diagram of an embodiment of the present invention, (a) OTA circuit, (b) corresponding graph encoding, (c) adjacency matrix;

[0066] Figure 2 A graphic filter for data preprocessing according to an embodiment of the present invention;

[0067] Figure 3 This is a schematic diagram of the MGIN model according to an embodiment of the present invention;

[0068] Figure 4 This is the MGIN model training process of an embodiment of the present invention;

[0069] Figure 5 The present invention provides a process for post-layout performance prediction based on MGIN according to an embodiment of the present invention;

[0070] Figure 6is a box plot of the raw performance of four types of OTAs according to an embodiment of the present invention;

[0071] Figure 7 : The training loss (a) and validation loss (b) of each model in the embodiments of the present invention. DETAILED DESCRIPTION

[0072] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0073] Embodiment 1:

[0074] The technical solution provided by the embodiment of the present invention includes:

[0075] (1) Methods for extracting features based on different circuit topologies:

[0076] The post-layout performance of the circuit is affected by the layout position and circuit topology. In order to leverage the success of the improved network in the regression task, this method extracts the following features based on different circuit topologies and is able to encode effective layout information, such as Figure 1 By calculating the feature vectors of nodes and devices, for each node, its features are extracted including device type (PMOS, NMOS, resistor, capacitor), pin type (drain, source, gate), subcircuit to which the device belongs (such as differential pair and load), and device location results.

[0077] (2) An improved graph isomorphic network model is used to predict the post-layout performance of various analog circuit layout schemes:

[0078] The present invention constructs an improved graph isomorphic network model (MGIN), such as Figure 3 , the model mainly consists of two improved graph isomorphic networks (GIN) convolutional layers and a predictor. Device node features and edge features can be learned as graph-level embeddings and sent to the trainable predictor.

[0079] (3) A simulated annealing framework was used as the layout method, and the performance of the prediction model as well as the area and line length were used as cost functions to optimize the layout.

[0080] As a further solution of the present invention: the original circuit data set is converted into an original graph data set by extracting the features of the circuit topology structure described. Then, the graph filter is used to obtain the required graph data set. Next, the model is constructed and trained, such as Figure 4A trained improved GIN model is implemented to predict the post-layout performance of circuits, such as Figure 5 .

[0081] As a further solution of the present invention: before using the improved GIN model for prediction, the present invention uses a graph filtering technology to preprocess the original graph dataset to improve its quality and information content for subsequent analysis or modeling tasks, such as Figure 2 Graph filtering refers to applying mathematical operators on the graph structure to modify its spectral characteristics, enhance specific features and filter out outliers in the original graph data. Use graph filters to filter out pin nodes and retain device nodes to obtain a special graph dataset that is beneficial to the next step of network training.

[0082] As a further solution of the present invention: In the improved GIN network model, the GIN of the circuit diagram is improved by splicing connection features, and the connection features are used to mine the topological information of the circuit when aggregating the features of adjacent nodes. In addition, different types of circuits have different performance indicators, and the problem can be defined as multi-task learning with multiple regression targets of different units and scales. The present invention adopts an effective method of weighting multiple loss functions by considering the equal variance uncertainty of each task, directly predicting the post-simulation performance of various analog circuit layout schemes, and providing information for the optimizer in the analog layout design, thereby accelerating the optimization iterative layout process.

[0083] Example 2

[0084] Based on Example 1, the embodiment of the present invention provides a simulation layout performance prediction and layout method for graph isomorphic network optimization, and the method includes the following steps:

[0085] Step 1: Extract features of nodes and devices in different circuits based on the method of extracting features from the topological structure, and construct the original graph dataset based on the extracted features;

[0086] Reference Figure 1 , the method for extracting features from the circuit topology structure mentioned above first calculates the feature vectors of nodes and devices. For the i-th node, the d feature includes the device type (PMOS, NMOS, resistor, capacitor), the pin type (drain, source, gate), the subcircuit to which the device belongs (such as differential pair and load), and the device position result. For the edge from node j to node i, the p feature includes the horizontal and vertical distances between the pins connecting the nodes, the pin type (such as gate, drain, source), and the wire net weight. Use the horizontal / vertical relative position of the pin (x i ,y i ) and the location result of device i (X i ,Y i ) Calculate the connected device d ijThe horizontal / vertical distance between the pins of , which is calculated using the Euclidean distance formula.

[0087]

[0088] The features of pin types are independent-hot encoded as shown in Table 1.

[0089] Table 1 Independent hot coding of pin types

[0090] Pin type One-hot encoding G [1,0,0] S [0,1,0] D [0,0,1] B / BULK [0,1,1] PLUS [1,1,0] MINUS [0,0,0]

[0091] The weight of a net is the importance of a particular connection in the circuit layout. Higher weights indicate that the net is critical to the performance of the design, prompting priority to reduce its wire length. This ensures that basic design criteria such as timing and signal integrity are met. Conversely, lower weights indicate that the net is less important, and resources can be focused on more important connections. Adjusting these weights helps optimize the layout and improve overall design efficiency. The graph structure effectively captures the spatial topology of the circuit, making it an ideal representation for circuit analysis and design. Typically, a circuit graph G = (V, E) is defined by a set of vertices V and a set of edges E = {(v,u)|v,u∈V}. Each node v i ∈V represents each device and IO pin of the circuit, while the edge E represents the connection between devices. The circuit is encoded as Figure 1 The graphic shown in .

[0092] The task can be viewed as a multi-task regression problem in machine learning, which can be formalized as follows: Given a set of circuit graphs G = {G 1 ,G 2 ,…,G n}, each device in the circuit diagram has an attribute vector, a, a∈A, and each attribute vector is z, z∈Z. For each graph G i , with performance list Y i ={y 1 ,y 2 ,…,y m The goal is to obtain the predicted performance of each circuit diagram To approximate the actual performance value Y as much as possible i ={y 1 ,y 2 ,…,y m}. The multi-objective regression performance prediction problem can be described as formula (2):

[0093]

[0094] The learning function θ(·) learns a representation vector that helps predict performance Prediction performance of the entire circuit diagram Specified by the function ⊙. The parameter w is an adjustable parameter used to indicate the importance of different types of performance indicators.

[0095] Step 2: Use graph filtering technology to preprocess the original graph dataset, apply mathematical operators on the graph structure of the original graph dataset to modify its spectral characteristics, enhance specific features and filter outliers in the original graph dataset through graph filters, and obtain a special graph dataset;

[0096] Reference Figure 2 , graph filtering technology is used to preprocess the original graph data set to improve its quality and information content for subsequent analysis or modeling tasks. In the present invention, graph filtering refers to the application of mathematical operators on the graph structure to modify its spectral characteristics, which involves the application of graph filters to enhance specific features and filter outliers in the original graph data, thereby improving its applicability to subsequent analysis or modeling tasks. On the one hand, the present invention uses the box plot method invented by American mathematician John W. Turkey to detect outliers by filtering out abnormal data and obtaining a data distribution that conforms to the standard normal distribution. The outlier judgment range is outside Q3+1.5IQR and Q1-1.5IQR; on the other hand, a graph filter is used to filter out pin nodes and retain device nodes to obtain a special graph data set that is beneficial to the next step of network training.

[0097] Step 3: Build an improved graph isomorphism network model, which includes two GIN convolutional layers and a predictor, and input the preprocessed special graph dataset into the improved graph isomorphism network model;

[0098] Reference Figure 3 ,The improved graph isomorphism network model mainly consists of two GIN convolutional layers and a predictor.,Device node features and edge features can be learned as graph-level embeddings and sent to the trainable predictor, and,MLP and LeakyRelu layers are used as predictors for performance regression.

[0099] The present invention improves the GIN of the circuit diagram by splicing the connection features. When the node features are aggregated from the neighborhood of the node, the connection features are used to mine the topological information of the circuit to represent the edges connected to the device in the circuit. v N v E v z v The eigenvector of can be defined as follows:

[0100]

[0101] In the work, it can be simplified to a linear transformation. F uv Refers to the edge e connecting device nodes u and v uvFor each layer of the GIN aggregator, the feature vector z v The feature vector h of the neighbors connected to the central device node v Therefore, the following formula can be used instead:

[0102]

[0103] Here, || represents a connection. Therefore, this model can aggregate the information of device neighborhood and edges and encode the subcircuit topology as a hidden vector.

[0104] Since different types of circuits have different performance metrics, the problem can be formulated as multi-task learning with multiple regression objectives of different units and scales. However, previous methods have been laborious and time-consuming to manually tune the optimal weighted loss function.

[0105] This paper adopts an effective method to weight multiple loss functions by considering the equal variance uncertainty of each task, and derives a multi-task loss function based on Gaussian likelihood maximization based on uniform uncertainty. Let f W (x) is the output of a neural network with weight W for input x, and the following probability model is defined:

[0106]

[0107] σ is a trainable parameter representing the observation noise. In the case of multiple model outputs, the following multi-task likelihood values ​​can be obtained:

[0108]

[0109] Detailed forward propagation algorithm of MGIN: Initializing node features where X represents the input features. For each layer l, the model performs several operations. First, for each node v, it calculates the set of connected edges E v , and use linear transformations to capture the topological structure of the graph to compute the edge eigenvector z v . The GIN model then updates the node features by concatenating, combining node and edge features to enrich the representation. This is achieved by applying a multi-layer perceptron (MLP) to the concatenated features. In addition, the model employs an attention mechanism to refine the node features, enabling it to focus on important neighbors. The outputs of the GIN and GAT processes are then concatenated and transformed, followed by global mean pooling to obtain a comprehensive graph-level representation. Finally, this merged feature vector is passed through a fully connected layer to produce the final output. This process effectively integrates node and edge information, leveraging the structure of the graph to improve performance.

[0110] Step 4: Perform end-to-end iterative training on the improved graph isomorphic network model until the maximum iteration standard is reached to obtain a trained graph isomorphic network model;

[0111] Reference Figure 4 MGIN training process is as follows: Given a training set {(X i ,Y i )|N=|X|,1≤i≤N}, where X i and Y i are the circuit diagram of the i-th circuit in the training data and the true value of the input data, respectively. The MGIN model is trained end-to-end until the maximum iteration criterion is reached. In each iteration, the model calculates the output of the training set in the feedforward direction. Then, the trainable parameters of the model are adjusted through supervised backpropagation to minimize the loss function.

[0112] Step 5: Use the simulated annealing framework as the layout method, use the trained graph isomorphism network model as the performance prediction, and use the performance of the performance prediction model as well as the area and line length as the cost function to output the optimized circuit layout.

[0113] Reference Figure 5 , showing the process of post-layout performance prediction using MGIN. First, the original circuit dataset is converted into a raw graph dataset through feature calculation and feature encoding described by circuit topology extraction. Then, the required graph dataset is obtained using graph filters. Next, a trained MGIN model is implemented to predict the post-layout performance of the circuit through improved graph isomorphism network model construction and training.

[0114] In summary, compared with the prior art, the present invention has significant technical advantages and beneficial effects in many aspects, as follows:

[0115] 1. Improve design efficiency and accuracy

[0116] Fast convergence and efficient optimization: The improved graph isomorphic network (MGIN) model shows faster convergence and lower verification loss during training. For example, MGIN only needs about 15 iterations to achieve convergence, while other models such as PEA require 50 cycles and GIN requires 25 cycles. This efficient training process makes the prediction results faster and more accurate, reduces the number of trial and error in analog IC design, and thus greatly improves the overall design efficiency.

[0117] Direct performance prediction: By introducing connection feature splicing and adaptive loss weighting mechanism, MGIN can directly predict the post-simulation performance under different layout schemes without actual layout and simulation. This bypasses the complex and time-consuming traditional wiring, parameter extraction and simulation steps, not only improving the prediction accuracy, but also shortening the design cycle.

[0118] 2. Enhance design quality and reliability

[0119] Multi-task learning capability: Considering the different performance requirements of different types of circuits, the present invention adopts a multi-task loss function based on Gaussian likelihood maximization with uniform uncertainty, which can simultaneously handle multiple regression targets with different units and scales. This feature ensures accurate prediction of various key performance indicators (such as common mode rejection ratio, phase margin, etc.), thereby improving the quality and reliability of the final product.

[0120] Intelligent layout optimization: Utilize the simulated annealing framework combined with the results of the prediction model to optimize the layout, and incorporate the prediction performance evaluation into the cost function. This method not only considers traditional factors such as area and line length, but more importantly, incorporates the impact on circuit performance, thereby achieving a better layout solution selection and ensuring the consistency and stability of the design.

[0121] 3. Save costs and resources

[0122] Reduce manual intervention: Traditional analog IC design is highly dependent on engineers’ experience and technical accumulation, and is often accompanied by high uncertainty. The present invention reduces the requirements for professional skills and the degree of manual intervention through the application of automated performance prediction and layout optimization tools, effectively controlling labor costs.

[0123] Reduce material consumption: By pre-evaluating the layout plan, unnecessary physical prototyping and repeated modifications are avoided, saving raw materials and manufacturing costs. In addition, the optimized layout also helps to reduce the chip size, further saving the use of silicon wafers.

[0124] 4. Ease of operation

[0125] Easy to integrate and expand: The method provided by the present invention can be easily integrated into the existing EDA tool chain, providing users with a friendly interface and support. At the same time, the technical framework has good versatility and flexibility, and can be applied to more types of circuit designs in the future, and even supports transfer learning to adapt to different application scenarios.

[0126] 5. Environmentally friendly design

[0127] Reduced energy consumption: By reducing the need for multiple simulations and iterative adjustments, the computing resources required for the entire design process are significantly reduced, indirectly reducing power consumption and other environmental impacts.

[0128] Example 3: Test Example

[0129] Referring to Table 2, in order to verify the effect of the present invention, the data set used includes OTA circuit design, but with different topology and compensation. The summary performance data statistics of the data set are shown in Table 2. Note that OTA1 and OTA2 are in the same schematic diagram, but with different sizes.

[0130] Table 2 Data statistics

[0131]

[0132]

[0133] Different from previous works, the layout performance is evaluated by several metrics, and the box plot method is used to obtain the data distribution of the performance metrics of four OTA circuits, such as Figure 6 As shown, this is the prediction target. All layouts were generated using TSMC 40nm technology, parasitic effects were extracted using Calibre PEX, and simulated using Cadence Spectre. For all experiments, 20% of the data (about 3200 layouts) were selected as the test set, which was never observed during the training process. 20% of the data was selected as the validation set, which is independent of the training set and provides information to help tune each parameter, especially to test the robustness of the model. 60% of the data was selected for training. The machine learning model was implemented in Python. The entire search process was run on an NVIDIA GeForce RTX 4090 equipped with a 13th Generation Intel(R) Core(TM) i9-13900KF CPU.

[0134] Table 3 summarizes the configuration of the GCN network used in the experiment. The hyperparameter settings of GCN follow the hyperparameter settings of the above work. During the model building process, holdout validation was performed to adjust the model hyperparameters.

[0135] Table 3 Parameter settings

[0136] Hyperparameters Number Learning rate 0.0001 Batch size 128 Epoch 400 Dropout ratio 0.5 MLP layers 1 Hidden units 8 Model layers 2

[0137] Figure 7The evolution of the training and validation loss of the baseline model is shown, evaluating the effectiveness of the present invention in constructing a graph neural network to learn OTA circuit representations from circuit data. It is compared with the replication model NN and PEA in previous studies to highlight the performance improvement of the work. In addition, it is compared with GCN, GAT, and GIN to demonstrate the superiority of the selected and constructed models. MGIN shows fast initial convergence, and its loss value decreases significantly in the first few epochs, indicating that early learning is effective and the loss value is minimal after convergence. This height highlights its excellent ability to learn quickly and maintain high performance. Based on the graph analysis, it is obvious that the models show different convergence speeds. NN converges in about 400 iterations, while GCN and GAT converge in about 250 iterations. The PEA model converges in about 50 epochs, and the graph isomorphic network GIN converges in about 25 epochs. It is worth noting that MGIN shows the fastest convergence speed, achieving convergence in about 15 epochs. In addition, it is worth noting that MGIN shows the fastest convergence speed, achieving convergence in about 15 epochs. Furthermore, when comparing the loss values ​​after convergence, MGIN shows the smallest loss, highlighting its superior performance. Therefore, considering the convergence speed and the loss value after convergence, MGIN clearly has a significant advantage.

[0138] The proposed GIN model is compared with the baseline model according to the metrics of the four OTAs detailed in Table 2. Tables 4-7 show the performance comparison results, including the relative error rate, the number of test sets with a relative error rate below 10%, and the RMSE between the proposed GIN and the baseline model on the regression datasets of the four OTA datasets.

[0139] Table 4 OTA1 circuit results comparison

[0140]

[0141] Table 5 OTA2 circuit results comparison

[0142]

[0143] Table 6 OTA3 circuit results comparison

[0144]

[0145] Table 7 OTA4 circuit results comparison

[0146]

[0147]

[0148] Its results 880 show that the proposed modified GIN outperforms all baseline models on the OTA dataset. In addition, considering all performance indicators of all four regression datasets, the proposed GIN model is the only one among the compared models that satisfies the condition that the average relative error of 70% of the test sets is less than 10%.

[0149] The present invention proposes a method for extracting features based on different circuit topologies, introduces an improved graph isomorphism network (GIN) model, which integrates edge-aware attention mechanism and adaptive loss weighting, can accurately predict the post-layout simulation performance of analog ICs based on layout results, uses simulated annealing framework for layout, and optimizes with reference to the predicted post-layout simulation performance. Experimental results show that the present invention is able to predict various performance indicators, such as common-mode rejection ratio, phase margin, and unit gain bandwidth, with an average error rate significantly lower than 10% in four different OTA designs. It is worth noting that the average root mean square error of the model when predicting multiple performance indicators is 3.549. By achieving post-layout performance prediction without the need for simulation, the present invention has made significant progress in simplifying the automated design process of analog ICs, and future work may involve the application of transfer learning to expand the applicability of the model from OTA to various circuit types.

[0150] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0151] It should be understood that those skilled in the art can make improvements or changes based on the above description, and all these improvements and changes should fall within the scope of protection of the appended claims of the present invention.

Claims

1. A simulation layout performance prediction and layout method for graph isomorphic network optimization, characterized in that: The method comprises the following steps: Step 1: Extract features of nodes and devices in different circuits based on the method of extracting features from the topological structure, and construct the original graph dataset based on the extracted features; Step 2: Use graph filtering technology to preprocess the original graph dataset, apply mathematical operators on the graph structure of the original graph dataset to modify its spectral characteristics, enhance specific features and filter outliers in the original graph dataset through graph filters, and obtain a special graph dataset; Step 3: Build an improved graph isomorphism network model, which includes two improved GIN convolutional layers, a pooling layer and a predictor, and input the preprocessed special graph dataset into the improved graph isomorphism network model; Step 4: Perform end-to-end iterative training on the improved graph isomorphic network model until the maximum iteration standard is reached to obtain a trained graph isomorphic network model; Step 5: Use the simulated annealing framework as the layout method, use the trained graph isomorphism network model as the performance prediction, and use the performance of the performance prediction model as well as the area and line length as the cost function to output the optimized circuit layout.

2. The method for predicting and laying out the simulated layout performance of a graph isomorphic network optimization according to claim 1, characterized in that: The method of step 1 specifically includes: Step 1.1: Calculate the feature vectors of nodes and devices. For each node feature, the device type and device position result are included. The device position result is defined as follows: For the edge from node j to node i, its features include the horizontal and vertical distances between the pins connecting the nodes, the pin type, and the net weight. The horizontal / vertical relative position (x i ,y i ) and the location result of device i (X i ,Y i ) Calculate the connected device d ij It is described by the horizontal / vertical distance between the pins; Step 1.2: Perform independent hot encoding on the pin types of the devices in the circuit; Step 1.3: Represent the hot encoding as a graph structure. The graph structure of the circuit G = (V, E) is defined by a set of vertices V and a set of edges E = {(v,u)|v,u∈V}. Each node v i ∈V represents each device and IO pin of the circuit, while the edge E represents the connection between devices; Step 1.4: Formulate a multi-objective regression performance prediction problem; the formula for the multi-objective regression performance prediction problem is: Among them, the learning function θ(·) learns the representation vector that helps performance prediction Prediction performance of the entire circuit diagram Specified by the function ⊙, the parameter w is an adjustable parameter used to indicate the importance of different types of performance indicators.

3. The method for predicting the performance and layout of a simulated layout of a graph isomorphic network optimization according to claim 2, characterized in that: In step 1.1, for each node, extracting its features further includes: Device types, including PMOS, NMOS, resistors, and capacitors; Pin types, including gate, drain, source, and substrate; The subcircuit to which the device belongs, including differential pairs and loads; Device location results.

4. The method for predicting the performance of a simulated layout and layout of a graph isomorphic network optimization according to claim 1, characterized in that: The method of step 2 specifically includes: Mathematical operators are applied on the graph structure to modify its spectral characteristics, enhance specific features and filter outliers in the original graph data. The methods used include box plot method; graph filters are used to filter out pin nodes and retain device nodes to obtain a special graph dataset for the next step of network training.

5. The method for predicting the performance of a simulated layout and layout of a graph isomorphic network optimization according to claim 1, characterized in that: The method of step 3 specifically includes: Step 3.1: The graph isomorphism network model includes two improved GIN convolutional layers, a pooling layer and a predictor; Step 3.2: Learn device node features and edge features as graph-level embeddings and send them to the trainable predictor; Step 3.3: An attention mechanism is used in the graph isomorphism network model to refine node features so that it can focus on important nodes; the output of the GIN convolutional layer is concatenated and transformed, and then globally averaged pooled to obtain a comprehensive graph-level representation; Step 3.4: The predictor of the model includes a multi-layer perceptron MLP and a LeakyRelu layer.

6. The method for predicting the performance of a simulated layout and layout of a graph isomorphic network optimization according to claim 5, characterized in that: In step 3.1, the improved GIN convolutional layer is specifically: When node features are aggregated from the neighborhood of the node, the connection features are used to mine the topological information of the circuit. The feature vector of the connection features can be defined as: in, is a reducible linear transformation, F uv Refers to the edge e connecting device nodes u and v uv For each layer of the GIN convolutional layer, the feature vector z v The feature vector h of the neighbors connected to the central device node v superior; The improved GIN weights multiple loss functions by considering the equal variance uncertainty of each task, and derives a multi-task loss function based on Gaussian likelihood maximization based on uniform uncertainty; let f W (x) is the output of a neural network with weight W for input x, and the following probability model is defined: Among them, σ is a trainable parameter representing the observation noise. In the case of multiple model outputs, the following multi-task likelihood values ​​are obtained: in, represents the loss of the kth output variable; σ k is a trainable parameter representing the k-th observation noise.

7. The method for predicting the performance of a simulated layout and layout of a graph isomorphic network optimization according to claim 6, characterized in that: The method of step 4 specifically includes: Step 4.1: Use the preprocessed special graph dataset as the training set. First, give the training set {(X i ,Y i )|N=|X|,1≤i≤N}, where X i and Y i are the circuit diagram of the i-th circuit in the training data and the true value of the input data; Step 4.2: The model is trained in an end-to-end iterative manner until the maximum number of iterations is reached; during each iteration, the output of the training set is calculated by the model in the feedforward direction; Step 4.3: In performance evaluation, the loss function L(·) is defined as: Where m and n are the number of tasks and the mini-batch size; Step 4.4: Adjust the trainable parameters of the model through supervised back-propagation to minimize the loss function L(·).

8. The method for predicting the performance of a simulated layout and layout of a graph isomorphic network optimization according to claim 1, characterized in that: The method of step 5 specifically includes: Step 5.1: Initialize the simulated annealing framework and set the simulated annealing parameters, including temperature T and cooling rate α; Step 5.2: Load the trained graph isomorphic network model to predict the performance of the circuit and calculate the cost function F of the layout result: F=Area+Wirelength+G Among them, Area is the area of ​​the circuit layout, Wirelength is the total length, and G is the performance prediction item; Step 5.3: Evaluate whether the current layout scheme is accepted: If not, reduce the temperature T and disturb the circuit layout result, and return to step 5.2; if accepted, output the layout result.

9. A simulation layout performance prediction and layout system for graph isomorphic network optimization, characterized in that: include: a memory for storing executable computer programs; A processor, for implementing the simulation layout performance prediction and layout method for graph isomorphic network optimization as described in any one of claims 1 to 8 when executing an executable computer program stored in a memory.

10. A computer-readable storage medium, characterized in that: A computer program is stored, which is used to implement the simulation layout performance prediction and layout method for graph isomorphic network optimization as described in any one of claims 1 to 8 when executed by a processor.

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