Integrated circuit layout design teaching auxiliary method

Abstract

The invention discloses an integrated circuit layout design teaching assistance method, and relates to the field of integrated circuits, and the method comprises the steps: receiving a circuit diagram creation instruction, and generating a circuit diagram drawing interface according to the circuit diagram creation instruction; identifying types and connection relations of circuit devices in the circuit diagram drawing interface; according to the identified circuit device type and the connection relation, generating a corresponding circuit schematic diagram data structure by adopting a graph neural network GNN algorithm based on message passing; converting the schematic circuit diagram data structure into a layout data structure; the layout data structure comprises geometric parameters and layout position data of layout elements; and according to the layout data structure, generating a circuit layout by using a reinforcement learning algorithm based on a graph neural network. In view of low integrated circuit layout design efficiency in the prior art, the design efficiency is improved by constructing a multi-objective optimized Markov decision process, utilizing deep learning and reinforcement learning algorithms and the like.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to an integrated circuit layout design teaching auxiliary method. Background Art

[0002] With the continuous evolution of integrated circuit manufacturing technology and the continuous increase in chip design complexity, layout design has become one of the most critical and time-consuming links in the integrated circuit design process. The quality of layout design directly affects key indicators such as chip area, power consumption, speed and yield, and plays a decisive role in the performance and cost of integrated circuits. However, traditional layout design methods mainly rely on manual drawing and repeated adjustments by designers, which is difficult to cope with the growing design complexity and optimization needs, resulting in low efficiency of layout design, long design cycle, delayed product launch time and reduced competitiveness.

[0003] In order to improve the efficiency and quality of layout design, the industry has proposed a variety of design automation and optimization methods. Rule-based automatic layout tools can automatically generate layouts according to predefined design rules and layout strategies, reducing the workload of manual drawing. Optimization-based layout algorithms, such as simulated annealing and genetic algorithms, improve the quality and convergence speed of layout to a certain extent through mathematical modeling and heuristic search. Machine learning-based methods, such as support vector machines and decision trees, achieve automatic prediction and optimization of layout parameters by extracting features from layout data and learning mapping relationships.

[0004] In addition, in the teaching of integrated circuit layout design, traditional theoretical explanations and manual drawing exercises make it difficult to cultivate students' engineering intuition and optimization awareness, which is not conducive to the rapid improvement of design capabilities. Students find it difficult to understand the design challenges and optimization strategies under complex processes, lack experience in layout quality assessment and debugging, and find it difficult to adapt to the talent needs of the rapidly developing integrated circuit industry. Summary of the invention

[0005] In response to the problem of low efficiency in integrated circuit layout design in the prior art, the present application provides an integrated circuit layout design teaching assistance method, which improves the design efficiency by constructing a multi-objective optimized Markov decision process and utilizing deep learning and reinforcement learning algorithms.

[0006] The purpose of this application is achieved through the following technical solutions.

[0007] The present application provides an integrated circuit layout design teaching auxiliary method, including: S1, receiving a circuit diagram creation instruction, and generating a circuit diagram drawing interface according to the circuit diagram creation instruction; S2, identifying the circuit device type and connection relationship in the circuit diagram drawing interface; S3, according to the identified circuit device type and connection relationship, using a message-passing-based graph neural network GNN algorithm to generate a corresponding circuit schematic data structure; the circuit schematic data structure includes the type, parameters and topological connection data of the circuit device; S4, converting the circuit schematic data structure into a layout data structure; the layout data structure includes geometric parameters and layout position data of the layout elements; S5, according to the layout data structure, using a reinforcement learning algorithm based on a graph neural network to generate a circuit layout; the reinforcement learning algorithm generates a circuit layout by modeling the layout design as a Markov decision process, using a graph neural network to encode and make decisions on the layout state and action space.

[0008] Furthermore, S2 identifies the types of circuit devices and connection relationships in the circuit diagram drawing interface, including: S21, according to the circuit diagram drawing interface, uses a deep convolutional neural network to perform image processing and feature extraction on the circuit diagram to obtain circuit diagram serialization data; wherein, circuit diagram serialization data: a digital representation obtained by performing image processing and feature extraction on the circuit diagram through a deep convolutional neural network. The pixel information of the circuit diagram is converted into a one-dimensional sequence, and each element corresponds to an area or component in the circuit diagram. The serialization data retains the spatial structure and topological relationship of the circuit diagram, which facilitates subsequent sequence modeling and analysis. Example: If the circuit diagram is divided into n areas, the serialization data can be represented as [ x 1 , x 2 ,......, x n ] ,in Represents the feature vector of the i-th region.

[0009] S22, encode the circuit diagram serialization data to obtain an encoded feature vector sequence; wherein, the feature vector sequence is a feature representation sequence obtained by encoding the circuit diagram serialization data. The discrete serialization data is mapped into continuous feature vectors through an encoder (such as word embedding), and each vector represents the characteristics of a region or component. The feature vector sequence retains the order information of the serialization data and provides a more semantic feature representation. Example: If the serialization data is [ x 1 , x 2 ,......, x n ] , the encoded feature vector sequence can be expressed as [ e 1 , e 2 ,......, e n ] ,in is the eigenvector of the ith region.

[0010] S23, use the bidirectional long short-term memory network Bi-LSTM to perform sequence modeling on the encoded feature vector sequence to obtain the encoded hidden state sequence; where the hidden state sequence: the hidden state representation sequence obtained by performing sequence modeling on the encoded feature vector sequence through the bidirectional LSTM. The hidden state sequence captures the contextual information at different positions in the sequence, including forward and backward dependencies. Each hidden state vector represents a summary of the sequence information up to the current position. Example: Suppose the encoded feature vector sequence is [ e 1 , e 2 ,......, e n ] , the hidden state sequence can be expressed as [ h 1 , h 2 ,......, h n ] ,in is the hidden state vector at the ith position.

[0011] S24, according to the encoded hidden state sequence, the attention weights between different positions are calculated through the attention mechanism, and a weighted context vector is generated according to the attention weights; wherein, the weighted context vector: according to the hidden state sequence, the correlation between different positions is calculated through the attention mechanism, and the weighted context representation is obtained. The attention weight represents the degree of dependence between the current position and other positions, and the larger the weight, the stronger the correlation. The weighted context vector is the weighted sum of the hidden state sequence, highlighting the context information related to the current position. Example: Let the hidden state sequence be [ h 1 , h 2 ,......, h n ] , the attention weight is [ a 1 , a 2 ,......, a n ] , then the weighted context vector of the i-th position ,in represents the attention weight of the i-th position to the j-th position.

[0012] S25, based on the weighted context vector, sequence labeling is performed using conditional random field (CRF) to generate a prediction sequence of circuit device types and connection attributes; wherein, prediction sequence: the prediction result of circuit device types and connection attributes obtained by sequence labeling using conditional random field based on the weighted context vector. The prediction sequence has the same length as the input circuit diagram serialization data, and each element represents the circuit device type or connection attribute at the corresponding position. The prediction sequence is the result of the model's understanding and recognition of the circuit diagram, and can be used for subsequent circuit analysis and simulation. Example: Assume that the circuit diagram serialization data is [ x 1 , x 2 ,......, x n ] , the prediction sequence can be expressed as [ y 1 , y 2 ,......, y n ] ,in Represents the predicted category of the i-th region, such as resistor, capacitor, connecting line, etc.

[0013] S26, determining the type and connection relationship of the circuit components according to the prediction sequence by setting a threshold or selecting the category with the highest probability.

[0014] Furthermore, S3, according to the identified circuit device types and connection relationships, a graph neural network (GNN) algorithm based on message passing is used to generate a corresponding circuit schematic data structure, including: S31, according to the identified circuit device types and connection relationships, a graph structure of the circuit schematic is constructed, the circuit devices are represented as nodes of the graph, and the connection relationships between the circuit devices are represented as edges of the graph; S32, at each node of the graph, a message vector is generated through a gated recurrent unit (GRU) according to the feature vector of the current node and the feature vectors of adjacent nodes; S33, the generated message vectors are aggregated through attention weighted averaging to obtain an aggregated message vector; S34, the feature vector of the current node and the aggregated message vector are concatenated to obtain a concatenated vector.

[0015] S35. Update the feature vector of the current node by performing a non-linear transformation on the concatenated vector, including: inputting the concatenated vector into a Gated Convolutional Neural Network (GCNN), which consists of multiple convolutional layers, a gating mechanism, and a pooling layer, and can effectively process the grid structure and local features of layout data; in each convolutional layer of the Gated Convolutional Neural Network, perform a convolution operation on the input feature map, that is, obtain the convolved feature map by convolving with a convolutional kernel, and the weight parameters of the convolutional kernel are obtained through training and learning; perform a non-linear transformation and information control on the convolved feature map through the gating mechanism, which includes an Update Gate and a Reset Gate. The Update Gate controls the proportion of information flowing from the previous layer to the current layer, and the Reset Gate controls the degree to which the current layer receives information from the previous layer. The gating mechanism can enhance the model's ability to capture important features and model long-term dependencies; perform a max-pooling operation on the gated feature map to downsample and reduce the dimension of the feature map by taking the maximum value in the local neighborhood, which not only retains significant features but also reduces the computational complexity; repeat until the last layer of the Gated Convolutional Neural Network to obtain the transformed feature vector, which fuses the multi-scale and hierarchical features of the layout data; perform Feature Fusion on the transformed feature vector and the feature vector of the current node, and use the gating mechanism to adaptively control the fusion ratio of the two feature vectors to obtain the fused feature vector; perform Instance Normalization on the fused feature vector by independently performing a normalization operation on each feature channel to reduce the style differences between different layout data and improve the generalization ability of the model; use the normalized feature vector as the updated feature vector of the current node.

[0016] S36. Generate a circuit schematic data structure containing circuit device types, parameters, and topological connection relationships according to the updated graph structure.

[0017] Further, S4, converts the circuit schematic data structure into a layout data structure; the layout data structure contains geometric parameters and layout position data of layout elements, including: S41, constructs a constraint relationship diagram between layout elements according to the circuit schematic data structure, the constraint relationship diagram represents the geometric constraints and topological relationships between layout elements; S42, uses the constraint relationship diagram as input, and uses the graph convolutional neural network GCN to extract and encode the features of the layout elements to obtain feature vectors of the layout elements; S43, uses the attention mechanism to perform weighted aggregation on the feature vectors of the layout elements to obtain the association features between the layout elements; wherein, the association features between the layout elements, in the process of converting the circuit schematic into the layout data structure, the association features between the layout elements represent the correlation and dependency between different layout elements. It is obtained by weighted aggregation of the feature vectors of the layout elements through the attention mechanism. The feature vectors of the layout elements are weighted summed according to the attention weights to obtain the association features between the layout elements. For layout element i, its association features It can be expressed as: ,in, is the attention weight of component i to component j, is the feature vector of component j, and n is the total number of components in the layout. It aggregates the information of other components related to component i, reflecting the interaction and dependency between components. The association features between layout components provide important contextual information for subsequent sequence modeling and layout generation. Through the association features, the model can capture the relative position, connection relationship, constraints, etc. between layout components, thereby generating a more reasonable and optimized layout. After the association features are concatenated with the feature vector of the layout component, they are used as the input of the gated recurrent unit (GRU) to generate the position and size sequence of the layout component. The concatenated feature vector contains the attribute information of the layout component itself and the association information with other components, which can more comprehensively represent the characteristics of the layout component.

[0018] S44, concatenating the feature vectors and associated features of the layout elements, and performing sequence modeling on the concatenated feature vectors using a gated recurrent unit (GRU) to obtain a position and size sequence of the layout elements; S45, generating a layout data structure based on the position and size sequence of the layout elements in combination with layout design rules; the layout design rules include a minimum width, a minimum spacing, and layout constraints of the layout elements.

[0019] Further, S41, based on the circuit schematic data structure, construct a constraint relationship diagram between layout elements, the constraint relationship diagram represents the geometric constraints and topological relationships between layout elements, including: extracting the type, parameters and topological connection relationship of circuit devices based on the circuit schematic data structure; using object-oriented modeling methods to abstract circuit devices into layout element classes, and establishing a mapping relationship between circuit devices and layout elements through inheritance and combination mechanisms; based on the parameters of circuit devices, using parametric modeling to determine the geometric constraints of layout elements, and encapsulating the geometric constraints as attributes of layout elements; based on the topological connection relationship of circuit devices, using graph theory algorithms to obtain the interconnection constraints between layout elements, and representing the interconnection constraints as edge attributes between layout elements; the interconnection constraints include alignment, adjacent and distant position relationships between layout elements; using the data structure of the attribute graph to construct a constraint relationship diagram between layout elements, representing layout elements as nodes of the graph, representing the attributes of the layout elements as attributes of the nodes, representing the geometric constraints and topological relationships between layout elements as edges of the graph, and representing the interconnection constraints as attributes of the edges.

[0020] Further, S5, according to the layout data structure, using the reinforcement learning algorithm based on the graph neural network, generating the circuit layout, including: S51, modeling the layout design as a multi-objective optimized Markov decision process, taking the layout data structure as the state, the layout operation of the layout element as the action, the layout quality evaluation function as the reward, setting the design constraint penalty item, and constructing a multi-objective reinforcement learning environment; S52, using the graph neural network to extract and encode the layout data structure, obtaining the local structural features of the layout elements through graph convolution, obtaining the global dependency between the layout elements through graph attention, and obtaining the feature representation of the layout state; S53, according to the layout design rules and design constraints, defining the layout operation set of the layout elements, constructing Construct a layout action space; S54, input the feature representation of the layout state and the layout action space into the strategy network, extract layout features at different levels through a multi-layer graph neural network, and generate a probability distribution of layout component layout operations; S55, sample and generate a layout operation sequence based on the probability distribution of layout component layout operations, and update the layout data structure based on the layout operation sequence; S56, calculate the design index of the layout state according to the layout quality evaluation function, and calculate the immediate reward vector of reinforcement learning according to the design index; S57, use the immediate reward vector and the state value function estimated based on the feature representation of the layout state, update the parameters of the strategy network through a multi-objective temporal difference algorithm, generate a multi-objective layout component layout strategy, and obtain the optimal circuit layout.

[0021] Further, S54, generating a probability distribution of layout operations of layout components, including: inputting the feature representation of the layout state and the layout action space into the strategy network, the strategy network adopts an encoder-decoder architecture, the encoder extracts the layout features of the layout state, and the decoder generates the probability distribution of the layout operations of the layout components; in the encoder, a multi-layer graph convolutional neural network is used to extract the multi-scale layout features of the layout state, each layer of graph convolution aggregates the node neighborhood information of different hops to obtain the local structural features of the layout components; in the last layer of the encoder, the global information of the aggregated nodes is adjusted by the attention weight to obtain the global dependency between the layout components; the local features and global dependencies extracted by the encoder are used as the input features of the decoder; in the decoder, a multi-layer fully connected neural network is used to map the layout features of the layout state to the layout action space; in the last layer of the decoder, the Musk attention mechanism is used to generate the probability distribution of layout operations of the layout components according to the geometric properties and topological relationships of the layout components.

[0022] Further, S56, calculates the design indicators of the layout state according to the layout quality evaluation function, and calculates the immediate reward vector of reinforcement learning according to the design indicators, including: extracting the area utilization and power consumption indicators of the layout state according to the layout data structure, the area utilization indicator is obtained by calculating the ratio of the area occupied by the layout elements to the total area of ​​the layout, and the power consumption indicator is obtained by calculating the dynamic power consumption and static power consumption of the layout elements; taking the area utilization indicator and the power consumption indicator as input, and using the layout quality evaluation function to calculate the quality score of the layout state through weighted summation; and calculating the immediate reward vector of reinforcement learning according to the quality score of the layout state through the immediate reward function.

[0023] Furthermore, the expression of the immediate reward function is: , where reward represents the immediate reward vector, and is a positive weight coefficient used to balance the optimization goals of area utilization and power consumption; represents the area utilization index, which is defined as: ,in, Indicates the area occupied by the layout components. Indicates the total area of ​​the territory; Represents the power consumption indicator, defined as: ,in, Represents the dynamic power consumption of the layout components, Represents the static power consumption of the layout components, represents the power budget of the design; represents the design constraint penalty term, which is used to penalize layout operations that violate the design specifications and is defined as: ,in, is the penalty coefficient, Indicates the number of times the layout operation violated the design specifications.

[0024] Further, S57, obtaining the optimal circuit layout, including: according to the feature representation of the layout state extracted by the encoder, calculating the value function of the current layout state through the state value network, the state value function adopts the same architecture as the policy network encoder, through a multi-layer graph convolutional neural network and an attention mechanism, extracting the layout features of the layout state and the global dependencies between the layout elements, and outputting the state value estimate through a fully connected layer; using the immediate reward vector and the state value estimate of the next time step, calculating the timing difference error of the current time step, and constructing the loss function of the policy network and the state value network according to the timing difference error and the multi-objective weight vector, and updating the network parameters through the gradient descent algorithm; repeating the above updating steps until the preset number of training rounds or convergence conditions are reached, and obtaining the optimal policy network parameters and state value network parameters; using the optimal policy network obtained by training, generating a probability distribution of layout element layout operations, and generating a layout operation sequence according to the probability distribution sampling to obtain the optimal circuit layout.

[0025] Compared with the prior art, the advantages of this application are:

[0026] Using a graph neural network based on message passing, through graph convolution and attention mechanism, we extract multi-scale local features and global dependencies of circuit schematics and layouts to form information-rich feature representations. Compared with traditional rule-based or heuristic algorithms, graph neural networks can adaptively learn key features under different circuits and processes, have stronger generalization capabilities, and can cope with complex and changing design requirements. At the same time, graph neural networks can also mine implicit information and optimization directions in layouts, guide subsequent layout decisions and parameter adjustments, and improve the accuracy and convergence speed of layout optimization.

[0027] The layout design is modeled as a Markov decision process. The immediate reward function is used to balance multiple design indicators such as area utilization and power consumption. The strategy network is used to generate layout operations, and the value network is used to evaluate the layout status. Through the interactive learning and optimization of the two networks, the global optimal layout design is finally obtained. Compared with traditional rule-based or single-objective optimization methods, reinforcement learning can search for the optimal solution in a larger design space, comprehensively weigh multiple design constraints and goals, and generate a more balanced and excellent layout solution. At the same time, by designing reasonable reward functions and penalty terms, reinforcement learning can also guide the layout strategy to avoid violating design specifications, thereby improving the robustness and manufacturability of the layout design. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The present application will be further described in the form of exemplary embodiments, which will be described in detail by the accompanying drawings. These embodiments are not restrictive, and in these embodiments, the same number represents the same structure, wherein:

[0029] Figure 1 is an exemplary flow chart of an integrated circuit layout design teaching auxiliary method according to some embodiments of the present application;

[0030] Figure 2 is an exemplary flow chart for determining circuit device types and connection relationships according to some embodiments of the present application;

[0031] Figure 3 is an exemplary flow chart of generating a layout data structure according to some embodiments of the present application;

[0032] Figure 4 This is an exemplary flow chart for generating an optimal circuit layout according to some embodiments of the present application. DETAILED DESCRIPTION

[0033] The method and system provided in the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0034] like Figure 1 As shown, S1, receiving a circuit diagram creation instruction, and generating a circuit diagram drawing interface according to the circuit diagram creation instruction; S2, identifying the circuit device type and connection relationship in the circuit diagram drawing interface; S3, using a graph neural network GNN algorithm based on message passing to generate a corresponding circuit schematic data structure according to the identified circuit device type and connection relationship; the circuit schematic data structure includes the type, parameters and topological connection data of the circuit device; S4, converting the circuit schematic data structure into a layout data structure; the layout data structure includes geometric parameters and layout position data of the layout elements; S5, generating a circuit layout according to the layout data structure using a reinforcement learning algorithm based on a graph neural network; the reinforcement learning algorithm generates a circuit layout by modeling the layout design as a Markov decision process, and using a graph neural network to encode and make decisions on the layout state and action space.

[0035] In S1, the system receives a circuit diagram creation instruction input by the user, which can be an event or command generated by the user selecting circuit devices and connecting lines through a graphical interface. According to the circuit diagram creation instruction, the system dynamically generates a corresponding circuit diagram drawing interface to provide users with a visual circuit design environment. At the data processing level, the circuit diagram creation instruction is converted into a data format recognizable by the interface rendering engine, such as UI layout parameters, control properties, etc., and an interactive circuit diagram drawing interface is generated by parsing and rendering these parameter data. At the same time, the user's drawing operations on the interface will also be converted into circuit diagram data in real time, such as device type, position coordinates, connection endpoints, etc., to form a data representation of the circuit diagram, providing input for subsequent recognition and processing.

[0036] like Figure 2 As shown, the goal of S2 is to identify the types of circuit devices and connection relationships in the circuit diagram drawing interface. A series of data-driven deep learning algorithms are used to perform feature extraction, sequence modeling and relationship prediction on the circuit diagram data. S21 Circuit diagram image processing and feature extraction: Image preprocessing: The screenshot of the circuit diagram drawing interface or the exported image file is uniformly scaled to a fixed size, such as (512, 512). This step can ensure the consistency of the input size of the subsequent CNN. The image is normalized and the pixel values ​​are scaled to the range of [0, 1]. Specifically, each pixel value is divided by 255 (for 8-bit RGB images). If the image is a grayscale image (C=1), it can be expanded to a three-channel RGB image (C=3) to accommodate the pre-trained CNN model. The format of the image data is (N, H, W, C), where N is the batch size, H and W are the image height and width, and C is the number of channels.

[0037] Feature extraction: Use pre-trained deep CNN models, such as ResNet-50 and Inception-v3, to extract features from circuit diagram images. The input of the CNN model is pre-processed image data, which is gradually extracted from local and global features of the image through multiple layers of convolution, pooling, activation functions, and other operations. Taking ResNet-50 as an example, its network structure consists of multiple residual blocks, each of which contains multiple convolution layers and skip connections. The convolution layer uses convolution kernels of different sizes and numbers to perform convolution operations on the input feature map to extract local features. For example, the first convolution layer may use 64 3x3 convolution kernels with a stride of 1 and a padding of 1. The pooling layer downsamples the convolution output to reduce the size of the feature map and increase the receptive field. Commonly used pooling operations include Max Pooling and Average Pooling. The activation function introduces nonlinear transformations to improve the expressiveness of the model. Commonly used activation functions include ReLU, Leaky ReLU, ELU, etc. After the last convolution block of ResNet-50, a feature map with a dimension of (N, h, w, d) is obtained, where h and w are the height and width of the feature map, and d is the number of feature channels (such as 2048). Feature serialization: Flatten the feature map output by CNN into a one-dimensional vector as the serialized feature data of the circuit diagram. Specifically, transform the dimension of the feature map from (N, h, w, d) to (N, L, d), where L=h*w is the flattened length of the feature map. The shape of the serialized feature data is (N, L, d), and each sample corresponds to a feature sequence with a length of L and a dimension of d.

[0038] S22 Circuit Diagram Serialized Data Encoding: Constructing a Feature Dictionary: For the serialized feature data, each feature vector is regarded as a "word" and a feature dictionary of size L is constructed. Each element in the dictionary corresponds to a unique feature vector, which can be represented by its position index in the sequence. The function of the feature dictionary is to discretize the continuous feature vector to facilitate the subsequent word embedding operation. Word Embedding: Use the word embedding technology to map discrete feature words into dense vectors of fixed length. Specifically, define an embedding matrix E with a shape of (L, D), where L is the feature dictionary size and D is the dimension of the embedding vector. For each feature word, by finding the corresponding row vector in the embedding matrix E, its D-dimensional embedding representation is obtained. Word embedding can be obtained by random initialization or pre-training. During the training process, the embedding matrix E is used as a learnable parameter of the model and is continuously updated and optimized through back propagation. The dimension D of the embedding vector is a hyperparameter that needs to be adjusted according to the complexity of the task and the size of the data. The value range is usually 64~512.

[0039] Sequence encoding: For each circuit diagram sample, each feature word in its feature sequence is replaced with the corresponding D-dimensional embedding vector. The shape of the sequence-encoded data is (N, L, D), and each sample corresponds to an embedding vector sequence of length L and dimension D. Through word embedding, the original high-dimensional discrete features can be converted into low-dimensional dense vectors while retaining the semantic relevance between features. The embedded vector sequence can be directly used as the input of subsequent sequence modeling modules (such as LSTM) for further feature learning and abstraction.

[0040] S23 Sequence Modeling: Use a bidirectional long short-term memory network (Bi-LSTM) to model the encoded feature sequence and capture the contextual information and long-distance dependencies of the sequence. Bi-LSTM consists of two LSTMs in opposite directions, one traversing the sequence from left to right and the other traversing the sequence from right to left, and finally concatenating the hidden states of the two directions. Suppose the encoded feature sequence is ,in is the embedding representation of the i-th feature vector. The calculation process of Bi-LSTM is as follows: Forward LSTM: ; Reverse LSTM: ; Splicing: h i = [ h i f , h i b ] ;in, and are the hidden states of the forward and backward LSTM at position i, with a dimension of H. is the concatenated hidden state with a dimension of 2H. Through Bi-LSTM, we can get a hidden state sequence with a length of L , each hidden state incorporates the bidirectional contextual information of the sequence.

[0041] S24 Attention Mechanism: Apply the attention mechanism to the hidden state sequence of Bi-LSTM, calculate the correlation between different positions, and generate a weighted context vector. Specifically, the Attention function is used to calculate the attention weight between the i-th position and all positions: ; ;in, Represents the attention score between positions i and j, which can be calculated using simple dot products, concatenation, or perceptrons. is the attention weight normalized by softmax. According to the attention weight, the weighted context vector of the i-th position is calculated: ; Context vector It is the weighted average of the hidden state sequence, integrating the information related to position i in the sequence.

[0042] S25 Sequence Labeling: Use conditional random fields (CRF) to label the hidden state sequence of Bi-LSTM and predict the circuit device type and connection properties at each position. CRF is a probabilistic graph model that can consider the transfer relationship and constraints between labels and is suitable for sequence labeling tasks. Suppose the label set of circuit device type is , the label set of the connection attribute is , where K and M are the number of types and attributes respectively. The feature function of CRF can be defined as: ;in, is the label of the ith position, is the label of the previous position, X is the input sequence, is the jth characteristic function, is the corresponding weight coefficient. The feature function can include: Transfer feature: characterizes the transition probability between labels, such as ; Emission features: characterize the correlation between labels and observations, such as ; Other custom features: such as context features, part-of-speech features, etc. Use CRF to decode the hidden state sequence to get the most likely label sequence: ; Among them, p(y|X) is the conditional probability distribution defined by CRF, is the predicted label at the i-th position.

[0043] S26 Type and connection relationship determination: According to the label sequence predicted by CRF, the circuit device type and connection attributes at each position are determined by setting a threshold or selecting the category with the highest probability. For the circuit device type, the label with the highest predicted probability can be selected as the final type: ; For connection attributes, a probability threshold τ can be set. When the predicted probability exceeds τ, the attribute is considered to exist: ;Through the above steps, the device type and connection relationship of each position in the circuit diagram can be obtained, and the recognition and analysis of the circuit diagram can be completed.

[0044] like Figure 3 As shown in Figure 1, the goal of S3 is to generate the corresponding circuit schematic data structure based on the identified circuit device types and connection relationships. This process uses a graph neural network (GNN) algorithm based on message passing to model the circuit schematic as a graph structure. Through message passing and feature updates between nodes, the semantic information of circuit devices is gradually extracted and integrated to form a complete data representation.

[0045] In S31, a graph structure of a circuit schematic is constructed according to the identified circuit device types and connection relationships. A corresponding node is created for each device according to the identified circuit device types. The feature vector of each node contains information such as the type and parameters of the device. For example, the feature vector of a resistor may contain properties such as resistance value and power. The feature vector of a node may be represented by a real number vector of a fixed length, such as (device_type, param1, param2, ...). In order to convert discrete device types into continuous feature representations, one-hot encoding or embedding techniques may be used.

[0046] Edge representation, according to the connection relationship between the identified circuit devices, add edges between the corresponding nodes. Edges can be directed or undirected, depending on the physical characteristics of the circuit connection. For example, the direction of current flow can be represented by a directed edge. The feature vector of the edge can contain information such as the type and attributes of the connection, such as (connection_type, attribute1, attribute2, ...). Similarly, one-hot encoding or embedding techniques can be used to convert discrete connection types into continuous feature representations.

[0047] The data structure of the graph, the graph structure of the circuit schematic can be represented by an adjacency matrix or an adjacency list. The adjacency matrix is ​​an N*N two-dimensional array (N is the number of nodes), where A[i][j]=1 means that there is an edge connecting node i and node j, and A[i][j]=0 means that they are not connected. The adjacency list is a list of length N, where each element corresponds to a node and stores all neighbor nodes connected to the node. The feature vector of a node can be stored in an N*D two-dimensional array (D is the dimension of the feature vector). The feature vector of an edge can be stored in an M*K two-dimensional array (M is the number of edges, K is the dimension of the feature vector of the edge).

[0048] In S32 to S35, a GNN algorithm based on message passing is used to extract and update the features of the graph structure. The core idea of ​​the algorithm is to aggregate local and global context information and update the feature representation of the node through message passing between nodes.

[0049] Specifically, in S32, at each node, a GRU unit is used to generate a message vector based on the feature vectors of the current node and adjacent nodes. This step implements information transmission and aggregation between nodes through GRU. For each node i in the graph, its feature vector is represented as , with dimension d. Use GRU unit to generate the message vector of node i , the input of GRU includes the current node feature and aggregate information of adjacent node features. GRU is a recurrent neural network unit that can control the flow and update of information and is suitable for processing sequence data. Through GRU, the current node can selectively receive and integrate information from adjacent nodes to form an updated message vector. Graph neural networks can simultaneously consider the type, parameters, and topological connection relationships of circuit devices to form an integrated data representation, providing a complete and high-quality input for subsequent layout design, reducing the loss and error of information transmission. The data representation based on the graph structure has good scalability and can flexibly handle circuit schematics of different sizes and complexities to adapt to changing design needs.

[0050] In S33, the attention mechanism is used to perform weighted averaging on the message vectors received by the node to obtain an aggregated message vector. Aggregated message vector: The attention mechanism is used to perform weighted averaging on all message vectors received by node i to obtain an aggregated message vector. The attention weight can be calculated based on the correlation between node i and its neighboring nodes to highlight important neighbor information. Calculate the attention weight. For node i and its neighboring node j, calculate the attention weight : e ij = Leaky Re LU ( W a × [ x i , m ij ]) , ,in, is a learnable parameter of the attention mechanism, LeakyReLU is the activation function, and softmax is used to normalize the attention weight. According to the attention weight, all message vectors of node i are weighted averaged: ,in, Represents the set of neighbor nodes of node i.

[0051] In S34 and S35, the original feature vector of node i is With the aggregated message Concatenate into a new vector : [ x i , m i '] . This vector contains the features of the node itself and the information of the local neighborhood, and can be used as the new features of the node for subsequent processing. The concatenation operation combines the features of the current node itself and the aggregated features of the neighborhood to form a more complete feature representation. Nonlinear transformations (such as ReLU, tanh, etc.) introduce the nonlinearity of the feature space and enhance the expressiveness of the feature representation. Through this feature update mechanism, the graph neural network can extract and fuse the hierarchical semantic features in the circuit schematic layer by layer.

[0052] In S36, node feature vector: After the GNN is updated, each node i has a corresponding feature vector , represents the latest feature representation of the node. Node feature vector It is usually a real vector of fixed length, such as , where d is the dimension of the feature vector. These feature vectors encode the attribute information of the node and the interaction information with other nodes.

[0053] Edge information: The edges in the graph structure represent the connection relationship between circuit components. Each edge can be represented by a triple To represent, where i and j are the indexes of the source node and the target node respectively, is the attribute information of the edge. It can include connection type, electrical parameters, etc., represented by a real number vector, such as , where k is the dimension of the edge attributes.

[0054] Adjacency matrix of the graph: Based on the updated node feature vectors and edge information, the adjacency matrix A of the graph can be constructed. The adjacency matrix A is an N*N two-dimensional array (N is the number of nodes), where A[i][j] represents the connection relationship between node i and node j. If there is an edge between node i and node j, then A[i][j]=1 (or the weight of the edge); otherwise A[i][j]=0. The adjacency matrix provides a compact representation of the graph structure, which facilitates subsequent graph analysis and processing.

[0055] Data structure generation: Node data structure: For each node i, a dictionary or class can be used to represent its attribute information. The node dictionary contains the following key-value pairs: "node_id": unique identifier of the node, such as integer index i. "device_type": type of circuit device, such as "resistor", "capacitor", etc. "parameters": parameter information of the device, such as resistance value, capacitance value, etc., represented by a dictionary or list. "features": feature vector of the node , represents the latest feature representation of the node.

[0056] Edge data structure: For each edge (i, j), a dictionary or class can be used to represent its attribute information. The edge dictionary contains the following key-value pairs: "source": the identifier of the source node, such as integer index i. "target": the identifier of the target node, such as integer index j. "connection_type": the type of connection, such as "series", "parallel", etc. "attributes": the attribute information of the edge , such as electrical parameters, etc., represented by a dictionary or list.

[0057] Schematic data structure: A schematic can be represented by a dictionary containing node and edge information. The schematic dictionary contains the following key-value pairs: "nodes": a list containing the dictionary representation of all nodes. "edges": a list containing the dictionary representation of all edges. The generated schematic data structure should be able to fully represent the topological structure and device attribute information of the circuit. The topological structure is represented by the connection relationship (edge) between nodes, describing the connection method of the circuit devices. The device attribute information is represented by the parameters and feature vectors of the nodes, describing the type, parameter value, etc. of each device. Through the dictionary representation of nodes and edges, the various components of the schematic can be easily accessed and operated.

[0058] S4, converts the circuit schematic data structure into a layout data structure; the layout data structure contains the geometric parameters and layout position data of the layout elements, including: The goal of S41 is to construct a constraint relationship diagram between layout elements based on the circuit schematic data structure, which is used to represent the geometric constraints and topological relationships between layout elements. This process converts the circuit schematic into a constraint relationship diagram for layout design through a series of data abstraction, mapping and graph construction technologies. First, the key information of the circuit device is extracted from the circuit schematic data structure, including device type, parameters and topological connection relationship. This information provides basic data for subsequent layout element mapping and constraint relationship construction.

[0059] Then, the object-oriented modeling method is used to abstract the circuit devices into layout component classes. Through inheritance and combination mechanisms, the mapping relationship between circuit devices and layout components is established. The inheritance mechanism allows the layout component class to inherit the common properties and behaviors of the circuit device class, realizing code reuse and unified management. The combination mechanism allows the layout component class to contain other layout component classes, forming a hierarchical layout structure to express complex circuit design patterns.

[0060] After determining the layout component class, the geometric constraints of the layout components are automatically generated based on the parameter information of the circuit device using the parametric modeling method. Parametric modeling allows the geometric properties of layout components (such as size, spacing, etc.) to be expressed in the form of parameters. Through the transfer and calculation of parameters, the geometric properties of layout components can be flexibly controlled and quickly generated. By encapsulating geometric constraints as attributes of layout components, the geometric features of layout components can be easily accessed and modified.

[0061] Next, based on the topological connection relationship of the circuit devices, the interconnection constraints between the layout components are obtained using graph theory algorithms. Interconnection constraints represent the relative positional relationship between layout components, such as alignment, proximity, and distance. By analyzing the connection topology of the circuit devices, the interconnection constraints between layout components are automatically inferred using graph theory algorithms such as the shortest path and minimum spanning tree. By expressing the interconnection constraints as edge attributes between layout components, the spatial relationship and layout requirements between layout components can be clearly described.

[0062] Finally, the data structure of the attribute graph is used to construct the constraint relationship graph between layout elements. The layout elements are represented as nodes of the graph, the attributes of the layout elements are represented as attributes of the nodes, the geometric constraints and topological relationships between the layout elements are represented as edges of the graph, and the interconnection constraints are represented as attributes of the edges. Through the attribute graph, the complex constraint relationships between the layout elements are organized in a data structure, which is convenient for subsequent layout optimization and constraint solving. The present application uses a graph theory algorithm to automatically infer the interconnection constraints between layout elements, avoiding the cumbersome process of manually specifying constraints, reducing the risk of errors, and speeding up the generation of constraints. The data structure of the attribute graph is used to uniformly represent the constraint relationships between layout elements, and the geometric constraints, topological relationships, and interconnection constraints are integrated in a graph model, which is convenient for subsequent analysis, optimization, and modification, and improves the efficiency of data processing.

[0063] In S42, the constraint relationship graph is used as input, and GCN is used to extract and encode the features of the layout elements. GCN is a deep learning model specifically used to process graph structure data. It aggregates the neighborhood information of nodes through convolution operations and extracts local and global features of nodes. By applying GCN on the constraint relationship graph, the feature representation of layout elements can be automatically learned, the geometric constraints and topological relationships between layout elements can be captured, and the low-dimensional feature vectors of layout elements can be obtained. Specifically, the constraint relationship graph G is used as input, and GCN is used to extract and encode the features of layout elements. GCN aggregates the neighborhood information of nodes by performing convolution operations on the graph structure to generate feature representations of nodes. The hierarchical structure of GCN can be expressed as: ,in, is the node feature matrix of the lth layer, A is the adjacency matrix of the graph, D is the node degree matrix, is the weight matrix of the lth layer, and σ is the activation function. By stacking multiple layers of GCN, high-level feature representations of layout components can be extracted. The output of GCN is the feature vector of each layout component. , represents the feature representation of node i. Feature vector It is usually a real vector of fixed length, such as , where d is the dimension of the feature vector. These feature vectors encode the geometric and topological properties of the layout elements, as well as the information about their association with other elements.

[0064] In S43, the feature vectors of the layout elements are weighted and aggregated using the attention mechanism to obtain the associated features between the layout elements. The attention mechanism can adaptively assign importance weights between different layout elements, highlighting key constraint relationships and layout dependencies. Through attention weighted aggregation, high-order interaction features between layout elements can be obtained, reflecting the relative importance and relevance of layout elements in the overall layout. Through the attention mechanism, each layout element i obtains an associated feature vector , indicating the association information with other components. It is usually also a real vector of fixed length, such as , where k is the dimension of the association feature. The association feature vector captures the correlation and context information between layout components, which helps to generate a more reasonable layout.

[0065] In S44, the feature vector of the layout element and the associated eigenvector Perform splicing to obtain the spliced ​​feature vector : p i = [ f i , c i ] , the concatenated feature vector Contains the features of the layout component itself and the association information with other components. GRU is used for sequence modeling to generate the position and size sequence of layout components. Based on the hidden state sequence generated by GRU, the position and size sequence of layout components is obtained. The position information can be expressed as coordinate values ​​(x, y), indicating the position of the layout component in the layout. The size information can be expressed as width and height (w, h), indicating the geometric size of the layout component. The length of the sequence is equal to the number of layout components, and each element corresponds to the position and size of a layout component.

[0066] In S45, the final layout data structure is generated according to the position and size sequence of the layout elements in combination with the layout design rules. Layout design rules: The position and size sequence of the layout elements are constrained and optimized in combination with the layout design rules. The layout design rules include: Minimum width: the minimum allowable width of the layout element. Minimum spacing: the minimum allowable distance between layout elements. Layout constraints: layout requirements such as alignment, symmetry, and boundaries. By applying the layout design rules, ensure that the generated layout meets the process and design requirements. Generate the final layout data structure based on the optimized layout element position and size sequence. The layout data structure generally includes: Component library: contains the geometric model and parameter information of the layout elements. Netlist: describes the connection relationship between the layout elements. Layout information: contains the position, size, and hierarchy information of the layout elements. The layout data structure can adopt industry standard formats, such as GDSII, OASIS, etc., to facilitate data exchange with other EDA tools.

[0067] like Figure 4 As shown, S5, generating a circuit layout, includes: in S51, modeling the layout design as a multi-objective optimization MDP. MDP is a mathematical framework for describing decision problems, which consists of states, actions, transition probabilities and reward functions. In the MDP modeling of layout design, the layout data structure is regarded as a state, which represents the layout information and constraints of the current layout. The layout operations of layout elements are regarded as actions, which represent possible behaviors for modifying and optimizing the layout. The layout quality evaluation function is regarded as a reward, which is used to measure the quality of the layout, such as area utilization, wiring length, timing performance, etc. At the same time, the design constraint penalty term is introduced to punish the layout operations that violate the design rules and constraints, and guide the optimization process in the direction of satisfying the constraints. Through this MDP modeling, the layout design is transformed into a multi-objective optimization problem, and the goal is to maximize the expected value of the layout quality evaluation function under the premise of satisfying the design constraints.

[0068] In S52, a graph neural network is used to extract and encode features of the layout data structure. The layout data structure naturally has the topological structure of a graph, and there are complex geometric constraints and connection relationships between layout elements. A graph neural network is a deep learning model specifically designed to process graph structure data, which can effectively capture the local and global features of nodes in the graph. Through graph convolution operations, the graph neural network can aggregate the local structural information of layout elements and extract features such as geometric properties and topological relationships of layout elements. Through the graph attention mechanism, the graph neural network can adaptively learn the global dependencies between layout elements and capture the relative importance and interactive influence of layout elements in the overall layout. Through the feature extraction and encoding of the graph neural network, the layout data structure is converted into a low-dimensional feature vector, which is used as a state representation in the MDP, providing rich contextual information for subsequent decision-making and optimization.

[0069] In S53, according to the layout design rules and design constraints, the layout operation set of the layout elements is defined, and the layout action space is constructed. The layout design rules and constraints specify the layout requirements and restrictions of the layout elements, such as minimum width, minimum spacing, alignment, symmetry, etc. According to these rules and constraints, a set of legal layout operations, such as moving, rotating, aligning, combining, etc., can be defined as the action space in the MDP. Each layout operation represents a possible behavior for modifying and optimizing the current layout state. By constructing the layout action space, the reinforcement learning algorithm can explore and optimize the layout within the legal operation range to avoid generating invalid layouts that violate the design rules and constraints. At the same time, by introducing the design constraint penalty term, the reinforcement learning algorithm can be further guided to optimize in the direction of satisfying the constraints, thereby improving the feasibility and reliability of the layout. This application provides a complete environment and state representation for subsequent reinforcement learning optimization by modeling the layout design as a multi-objective optimized MDP, using a graph neural network to extract and encode the layout data structure, and constructing the layout action space according to the design rules and constraints. This data-driven optimization method combines the advantages of deep learning and reinforcement learning. It can adaptively learn and optimize the layout, maximize the expected value of the layout quality evaluation function while meeting the design constraints, and provide new ideas and means to improve the efficiency and quality of integrated circuit design.

[0070] The goal of S54 is to design a policy network that takes the feature representation of the layout state and the layout action space as input, extracts layout features at different levels through a multi-layer graph neural network, generates the probability distribution of layout operations of layout components, and guides the reinforcement learning algorithm to explore and optimize in the layout action space. The policy network adopts an encoder-decoder architecture and consists of two main parts: the encoder is responsible for extracting the layout features of the layout state, and the decoder is responsible for generating the probability distribution of layout operations of layout components.

[0071] In the encoder, a multi-layer graph convolutional neural network (GCN) is used to process the feature representation of the layout state and extract layout features of different scales. Each layer of GCN aggregates node neighborhood information of different hops and captures the local structural features of layout components, such as geometric shape, relative position, etc., through convolution operations. By stacking GCN layer by layer, the encoder can extract multi-scale layout features of the layout state, capturing the hierarchical relationship between layout components from local to global. Multi-scale layout features of the layout state are extracted by multi-layer GCN, capturing the hierarchical relationship between layout components from local to global, providing rich contextual information for subsequent decision-making.

[0072] In the last layer of the encoder, the attention mechanism is introduced to adjust the global information of the aggregated nodes through the attention weights. The attention mechanism can adaptively learn the global dependencies between layout components and highlight the key constraints and layout patterns. Through the weighted summation of attention weights, the encoder can obtain the global interaction information between layout components and capture the overall characteristics of the layout. The introduction of the attention mechanism adaptively learns the global dependencies between layout components, highlights the key constraints and layout patterns, and improves the expressiveness of the policy network.

[0073] The local features and global dependencies extracted by the encoder are used as input features of the decoder and passed to the decoder for subsequent processing. In the decoder, a multi-layer fully connected neural network (FCN) is used to map the layout features of the layout state to the layout action space. FCN converts high-dimensional layout features into low-dimensional action representations through nonlinear transformation and feature combination, and adapts the dimension and structure of the layout action space. FCN is used to map layout features to the layout action space, adapt the dimension and structure of the action space, and ensure that the generated layout operations meet the design rules and constraints.

[0074] In the last layer of the decoder, the Musk attention mechanism is used to generate the probability distribution of layout component layout operations. The layout state feature vector: The local features and global dependencies of the layout state extracted by the encoder are represented as feature vectors , where d is the dimension of the feature vector. Layout action space: According to the layout design rules and constraints, a set of legal layout operations are defined, expressed as the action space , where n is the size of the action space. Calculate the Musk attention weight, for each layout operation , calculate its characteristic vector with the layout state The attention weight . Using the attention function Compute attention weights, such as dot-product attention or scaled dot-product attention: ,in For layout operations The embedding vector of can be obtained through learning.

[0075] Normalize the attention weights to meet the requirements of the probability distribution: . According to the geometric properties and topological relationships of the layout components, illegal or unreasonable layout operations are shielded. Define the mask vector ,in Represents a layout operation legitimate, Represents a layout operation Illegal.

[0076] Musk Vector It can be pre-defined based on layout design rules and constraints, or it can be learned. Vector with Musk Perform element-by-element multiplication to obtain the masked attention weights : , renormalize the masked attention weights to obtain the final layout operation probability distribution : The probability distribution of the decoder output layout operation , indicating the possibility of selecting different layout operations under the current layout state.

[0077] Reinforcement learning algorithms can be used to To select an action, use - Greedy strategy or random sampling strategy. Through the Musk attention mechanism, the decoder can assign different attention weights to different layout operations according to the geometric properties and topological relationships of the layout elements. Musk operations can block illegal or unreasonable layout operations to ensure that the generated layout operations meet the design rules and constraints. This mechanism effectively guides the reinforcement learning algorithm to explore and optimize within the legal operation space, improving the efficiency and quality of layout generation. Through Musk operations, this application can integrate layout design rules and constraints into the generation process of layout operations to ensure the legality and feasibility of the generated layout operations. By blocking illegal layout operations, the Musk attention mechanism can effectively reduce the size of the action space and accelerate the convergence speed of the reinforcement learning algorithm. The Musk attention mechanism can assign different attention weights to different layout operations according to the geometric properties and topological relationships of the layout elements, so that the decoder can pay more attention to important layout operations and improve the quality of layout generation.

[0078] Through the encoder-decoder architecture of the policy network, S54's technical solution realizes end-to-end mapping from layout state to layout operation probability distribution. The encoder extracts multi-scale layout features of the layout state through multi-layer GCN, capturing the local structure and global dependencies between layout elements. The decoder maps the layout features to the layout action space through FCN and Musk's attention mechanism, generating a layout operation probability distribution that meets the design rules and constraints. This data-driven approach combines the advantages of graph neural networks and attention mechanisms, can adaptively learn and optimize layout layout, provides effective strategy guidance for reinforcement learning algorithms, and improves the efficiency and quality of layout design.

[0079] S55: Sample and generate a layout operation sequence according to the probability distribution of layout operation of layout components, and update the layout data structure according to the layout operation sequence. First, sample the layout operation, and update the layout data structure according to the layout operation probability distribution generated by the decoder. , using random sampling to generate a sequence of layout operations , where T is the sequence length. Common sampling methods include -Greedy sampling and random sampling. - Greedy sampling The layout operation is randomly selected with probability The probability of selecting the layout operation with the highest probability is . Random sampling is based on the probability distribution Direct sampling layout operations.

[0080] Update the layout data structure according to the layout operation sequence obtained by sampling , and update the layout data structure in turn. For each layout operation , modify the position, direction, alignment and other properties of the layout element according to its corresponding operation type (such as move, rotate, align, etc.). The updated layout data structure should meet the design rules and constraints, such as minimum spacing, alignment requirements, etc. This application generates a layout operation sequence based on the probability distribution of layout element layout operations, and updates the layout data structure based on the sequence. This process allows the reinforcement learning algorithm to explore the layout action space and find the optimized layout solution.

[0081] S56: Calculate the design index of the layout state according to the layout quality evaluation function, and calculate the instant reward vector of reinforcement learning according to the design index. Extract design index: According to the updated layout data structure, extract the area utilization index and power consumption index of the layout state. The area utilization index area_util is obtained by calculating the ratio of the area used_area occupied by the layout components to the total area total_area of ​​the layout: The power consumption indicator power_util is obtained by calculating the dynamic power consumption dynamic_power and static power consumption static_power of the layout components: , where power_budget represents the power budget of the design.

[0082] Calculate the layout quality score: Take the area utilization index area_util and the power consumption index power_util as input and use the layout quality evaluation function The quality score of the layout state is calculated by weighted summation: , layout quality assessment function It can be customized according to design goals and requirements. Common forms include weighted summation, product, etc.

[0083] Calculate the instant reward vector: According to the quality score of the state of the map, the instant reward function Calculating the immediate reward vector for reinforcement learning : , the immediate reward function The expression is: ,in, and It is a positive weight coefficient used to balance the optimization goals of area utilization and power consumption; penalty represents the design constraint penalty item, which is used to penalize layout operations that violate the design specifications.

[0084] The calculation method of the design constraint penalty is: ,in, is the penalty coefficient, Indicates the number of times the layout operation violates the design specification. This application calculates the design indicators of the layout state through the layout quality evaluation function, including area utilization and power consumption indicators, and calculates the immediate reward vector of reinforcement learning based on these indicators. The immediate reward function comprehensively considers the area utilization, power consumption, and design constraint penalty items, and calculates the immediate reward by weighted summation. This reward design can guide the reinforcement learning algorithm to optimize area utilization and power consumption, while avoiding the generation of layout operations that violate the design specifications.

[0085] S57: Using the instant reward vector and the state value function estimated based on the layout state feature representation, the parameters of the strategy network are updated through the multi-objective temporal difference algorithm to generate a multi-objective layout component placement strategy to obtain the optimal circuit layout. State value network: Based on the feature representation of the layout state extracted by the encoder , through the state value network Calculate the value function of the current state of the board. The state value network uses the same architecture as the policy network encoder, and extracts the layout features of the board state and the global dependencies between board components through a multi-layer graph convolutional neural network (GCN) and attention mechanism.

[0086] The output of the state value network is passed through the fully connected layer to obtain the state value estimate , represents the expected value of the long-term cumulative reward of the current state of the board. Temporal difference error calculation: using the immediate reward vector and the state value estimate for the next time step , calculate the temporal difference error of the current time step : ,in, is a discount factor used to balance the importance of immediate rewards and future rewards. Represents the difference between the current state value estimate and the actual accumulated reward, which is used to guide the parameter update of the policy network and the state value network.

[0087] Loss function construction: based on time difference error and the multi-objective weight vector , build a policy network and state value network The loss function of the policy network is It takes the form of weighted time difference error: L π =− E ( v t , a t )~ π θ [ w T × δ t × log π θ ( a t | v t )] ,in, The feature vector of the layout state at time step t represents the current state of the layout; According to the policy network From the layout status The layout operation obtained by sampling in ; Represents the state of a given strategy network Then select Layout Operation probability.

[0088] Loss Function of State Value Network It takes the form of weighted mean square error: L V = E ( v t , r t , v t + 1 )~ D [ ( w T × δ t ) 2 ] , where D is the experience replay buffer, which is used to store past transfer data, including state , instant rewards , and the next state . Network parameter update: Through the gradient descent algorithm, according to the loss function of the policy network And the loss function of the state value network , for network parameters and Commonly used gradient descent algorithms include Adam and RMSprop, which continuously improve the performance of the policy network and state value network by calculating the gradient of the loss function to the network parameters and updating the parameters at a certain learning rate.

[0089] Training process: Repeat until the preset number of training rounds is reached or convergence conditions are met. During the training process, the transfer data is collected by continuously interacting with the environment. , and store it in the experience replay buffer In each training step, a batch of transfer data is randomly sampled from the experience replay buffer to calculate the loss function and update the network parameters. Through multiple iterations of training, the parameters of the policy network and the state value network are continuously optimized, and finally the optimal policy network parameters are obtained. and state-value network parameters .

[0090] Optimal circuit layout generation: using the trained optimal strategy network , according to the characteristic representation of the current layout state , generating the probability distribution of layout component placement operations According to the probability distribution Sampling Generates a Sequence of Layout Operations , and updates the layout data structure according to the layout operation sequence to obtain the optimal circuit layout.

[0091] In this application, the state value network extracts the layout features of the layout state and the global dependencies between the layout elements through the same architecture as the policy network encoder, and outputs the state value estimate. The temporal difference error is calculated based on the immediate reward vector and the state value estimate of the next time step, which represents the difference between the current state value estimate and the actual cumulative reward. In the construction of the loss function, the loss function of the policy network takes the form of weighted temporal difference error, and the loss function of the state value network takes the form of weighted mean square error. The network parameters are updated by the gradient descent algorithm, so that the performance of the policy network and the state value network is continuously improved. Through an end-to-end reinforcement learning method, the layout element layout strategy is automatically learned and optimized, taking into account multiple optimization objectives such as area utilization, power consumption, etc. Compared with traditional heuristic algorithms and rule-driven methods, this scheme has stronger adaptability and optimization capabilities, can automatically extract the key features of the layout state, learn the complex dependencies between layout elements, and generate high-quality circuit layout designs.

Claims

1. An integrated circuit layout design teaching auxiliary method, characterized in that: include: S1, receiving a circuit diagram creation instruction, and generating a circuit diagram drawing interface according to the circuit diagram creation instruction; S2, identifying the types and connection relationships of circuit components in the circuit diagram drawing interface; S3, according to the identified circuit device type and connection relationship, using a message-passing-based graph neural network (GNN) algorithm to generate a corresponding circuit schematic data structure; the circuit schematic data structure includes the type, parameters and topological connection data of the circuit device; S4, converting the circuit schematic data structure into a layout data structure; the layout data structure includes geometric parameters and layout position data of layout elements; S5, based on the layout data structure, using the reinforcement learning algorithm based on the graph neural network to generate the circuit layout; The reinforcement learning algorithm generates a circuit layout by modeling the layout design as a Markov decision process and using a graph neural network to encode and make decisions on the layout state and action space.

2. The integrated circuit layout design teaching auxiliary method according to claim 1, characterized in that: S2, identifying the types of circuit components and connection relationships in the circuit diagram drawing interface, including: S21, according to the circuit diagram drawing interface, using a deep convolutional neural network to perform image processing and feature extraction on the circuit diagram to obtain circuit diagram serialization data; S22, encoding the circuit diagram serialization data to obtain an encoded feature vector sequence; S23, using a bidirectional long short-term memory network Bi-LSTM to perform sequence modeling on the encoded feature vector sequence to obtain the encoded hidden state sequence; S24, according to the encoded hidden state sequence, calculate the attention weights between different positions through the attention mechanism, and generate a weighted context vector according to the attention weights; S25, according to the weighted context vector, a conditional random field (CRF) is used to perform sequence labeling to generate a prediction sequence of circuit device types and connection attributes; S26, determining the type and connection relationship of the circuit components according to the prediction sequence by setting a threshold or selecting the category with the highest probability.

3. The integrated circuit layout design teaching auxiliary method according to claim 2, characterized in that: S3, using the message passing-based graph neural network GNN algorithm to generate the corresponding circuit schematic data structure, including: S31, constructing a graph structure of a circuit schematic diagram according to the identified circuit device types and connection relationships, representing the circuit devices as nodes of the graph, and representing the connection relationships between the circuit devices as edges of the graph; S32, at each node of the graph, a message vector is generated through a gated recurrent unit GRU according to the feature vector of the current node and the feature vectors of the adjacent nodes; S33, aggregating the generated message vectors by attention weighted averaging to obtain an aggregated message vector; S34, concatenating the feature vector of the current node and the aggregated message vector to obtain a concatenated vector; S35, updating the feature vector of the current node by performing nonlinear transformation on the concatenated vector; S36, generating a circuit schematic diagram data structure including circuit device types, parameters and topological connection relationships according to the updated diagram structure.

4. The integrated circuit layout design teaching auxiliary method according to claim 3, characterized in that: S4, converting the circuit schematic data structure into a layout data structure, including: S41, constructing a constraint relationship diagram between layout elements according to the circuit schematic data structure, wherein the constraint relationship diagram represents geometric constraints and topological relationships between the layout elements; S42, taking the constraint relationship graph as input, using the graph convolutional neural network GCN to extract and encode the features of the layout components, and obtaining the feature vector of the layout components; S43, using the attention mechanism to perform weighted aggregation on the feature vectors of the layout elements to obtain the correlation features between the layout elements; S44, concatenating the feature vector and the associated feature of the layout element, and performing sequence modeling on the concatenated feature vector using a gated recurrent unit GRU to obtain a position and size sequence of the layout element; S45, generating a layout data structure according to the position and size sequence of the layout elements in combination with layout design rules; the layout design rules include the minimum width, minimum spacing and layout constraints of the layout elements.

5. The integrated circuit layout design teaching auxiliary method according to claim 4, characterized in that: S41, constructing a constraint relationship diagram between layout components according to the circuit schematic data structure, including: Extract the type, parameters and topological connection relationship of circuit components according to the circuit schematic data structure; By using object-oriented modeling methods, circuit devices are abstracted into layout component classes, and the mapping relationship between circuit devices and layout components is established through inheritance and combination mechanisms; According to the parameters of the circuit devices, the geometric constraints of the layout elements are determined by parametric modeling, and the geometric constraints are encapsulated as the attributes of the layout elements; According to the topological connection relationship of the circuit devices, the interconnection constraints between the layout elements are obtained by using the graph theory algorithm, and the interconnection constraints are expressed as edge attributes between the layout elements; the interconnection constraints include the alignment, adjacent and distant position relationships between the layout elements; Using the data structure of the property graph, a constraint relationship graph between layout elements is constructed. The layout elements are represented as nodes of the graph, the attributes of the layout elements are represented as attributes of the nodes, the geometric constraints and topological relationships between the layout elements are represented as edges of the graph, and the interconnection constraints are represented as attributes of the edges.

6. The integrated circuit layout design teaching auxiliary method according to any one of claims 2 to 5, characterized in that: S5, based on the layout data structure, uses the reinforcement learning algorithm based on the graph neural network to generate the circuit layout, including: S51, modeling layout design as a multi-objective optimization Markov decision process, taking the layout data structure as the state, the layout operation of the layout components as the action, the layout quality evaluation function as the reward, setting the design constraint penalty term, and constructing a multi-objective reinforcement learning environment; S52, using a graph neural network to extract and encode features of the layout data structure, obtaining local structural features of layout components through graph convolution, obtaining global dependencies between layout components through graph attention, and obtaining feature representation of the layout state; S53, defining a layout operation set of layout elements according to layout design rules and design constraints, and constructing a layout action space; S54, inputting the feature representation of the layout state and the layout action space into the strategy network, extracting layout features at different levels through a multi-layer graph neural network, and generating a probability distribution of layout operations of layout components; S55, sampling and generating a layout operation sequence according to the probability distribution of layout component layout operations, and updating the layout data structure according to the layout operation sequence; S56, calculating a design index of the layout state according to the layout quality evaluation function, and calculating an immediate reward vector of reinforcement learning according to the design index; S57, using the instant reward vector and the estimated state value function based on the layout state feature representation, the parameters of the strategy network are updated through a multi-objective temporal difference algorithm, a multi-objective layout component placement strategy is generated, and the optimal circuit layout is obtained.

7. The integrated circuit layout design teaching auxiliary method according to claim 6, characterized in that: S54, generating a probability distribution of layout component placement operations, including: The feature representation of the layout state and the layout action space are input into the strategy network. The strategy network adopts an encoder-decoder architecture. The encoder extracts the layout features of the layout state, and the decoder generates the probability distribution of the layout component layout operation. In the encoder, a multi-layer graph convolutional neural network is used to extract the multi-scale layout features of the layout state. Each layer of graph convolution aggregates the neighborhood information of nodes with different hops to obtain the local structural features of the layout components. In the last layer of the encoder, the global information of the aggregated nodes is adjusted through the attention weights to obtain the global dependencies between the layout components; The local features and global dependencies extracted by the encoder are used as input features of the decoder; In the decoder, a multi-layer fully connected neural network is used to map the layout features of the layout state to the layout action space; In the last layer of the decoder, the Musk attention mechanism is used to generate the probability distribution of layout element layout operations based on the geometric properties and topological relationships of the layout elements.

8. The integrated circuit layout design teaching auxiliary method according to claim 6, characterized in that: S56, calculating the design index of the layout state according to the layout quality evaluation function, and calculating the instant reward vector of the reinforcement learning according to the design index, including: According to the layout data structure, the area utilization and power consumption index of the layout state are extracted, wherein the area utilization index is obtained by calculating the ratio of the area occupied by the layout elements to the total area of ​​the layout, and the power consumption index is obtained by calculating the dynamic power consumption and static power consumption of the layout elements; Taking the area utilization index and the power consumption index as input, the quality score of the layout state is calculated by weighted summation using the layout quality evaluation function; According to the quality score of the board state, the immediate reward vector of reinforcement learning is calculated through the immediate reward function.

9. The integrated circuit layout design teaching auxiliary method according to claim 8, characterized in that: The expression of the immediate reward function is: ; Among them, reward represents the immediate reward vector, and is a positive weight coefficient used to balance the optimization goals of area utilization and power consumption; represents the area utilization index, which is defined as: ; in, Indicates the area occupied by the layout components. Indicates the total area of ​​the territory; Represents the power consumption indicator, defined as: ; in, Represents the dynamic power consumption of the layout components, Represents the static power consumption of the layout components, represents the power budget of the design; represents the design constraint penalty term, which is used to penalize layout operations that violate the design specifications and is defined as: ; in, is the penalty coefficient, Indicates the number of times the layout operation violated the design specifications.

10. The integrated circuit layout design teaching auxiliary method according to claim 6, characterized in that: S57, obtaining the optimal circuit layout, including: Based on the feature representation of the layout state extracted by the encoder, the value function of the current layout state is calculated through the state value network. The state value function adopts the same architecture as the policy network encoder, extracts the layout features of the layout state and the global dependencies between layout elements through a multi-layer graph convolutional neural network and an attention mechanism, and outputs the state value estimate through a fully connected layer; Using the immediate reward vector and the state value estimate of the next time step, the time difference error of the current time step is calculated. Based on the time difference error and the multi-objective weight vector, the loss function of the policy network and the state value network is constructed, and the network parameters are updated through the gradient descent algorithm. Repeat the above update steps until the preset number of training rounds or convergence conditions are reached, and the optimal policy network parameters and state value network parameters are obtained; The optimal strategy network obtained through training is used to generate the probability distribution of layout component layout operations, and the layout operation sequence is generated based on the probability distribution sampling to obtain the optimal circuit layout.

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