Interconnection and intercommunication system for printed circuit board

Abstract

The invention provides an interconnection and intercommunication system for a printed circuit board, and relates to the technical field of circuit boards, and the system comprises a design planning module which carries out the design of the interconnection and intercommunication of the printed circuit board according to the key demands of the printed circuit board, and obtains a preliminary design plan; the analogue simulation module is used for performing simulation and performance evaluation on interconnection and intercommunication of the printed circuit board according to the preliminary design plan to obtain a first performance evaluation result; the design optimization module is used for optimizing the preliminary design plan according to the first performance evaluation result to obtain an optimized design plan; and the manufacturing and fine tuning module is used for interconnection and intercommunication of the current printed circuit board based on optimization design planning. The method comprises the following steps of: simulating a preliminary design plan obtained by designing interconnection and intercommunication of the printed circuit board according to key requirements of the printed circuit board by utilizing set simulation software; interconnection and intercommunication of the printed circuit boards are achieved by optimizing the preliminary design plan, and the requirements for high-speed data transmission and high-reliability electrical connection of the printed circuit boards can be effectively met.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit boards, and particularly relates to an interconnection system for a printed circuit board. Background Art

[0002] In recent years, with the rapid development of electronic devices, as a core component in electronic devices, the performance requirements of printed circuit boards have been increasing day by day. However, when facing high-density and high-speed data transmission, traditional printed circuit board connection technologies often have insufficient connection reliability and are difficult to meet the requirements of modern electronic devices for high-speed data transmission and high reliability. Therefore, how to achieve high-speed data transmission and high-reliability electrical connection requirements for printed circuit boards has become one of the current research focuses.

[0003] Therefore, the present invention provides an interconnection system for a printed circuit board. Summary of the Invention

[0004] The present invention provides an interconnection system for a printed circuit board, which is used to simulate and evaluate the interconnection of a printed circuit board and obtain a first performance evaluation result by using a set simulation software according to a preliminary design plan obtained by designing the interconnection of the printed circuit board according to the key requirements of the printed circuit board; based on an optimized design plan obtained by optimizing the preliminary design plan according to the first performance evaluation result, the high-speed data transmission and high-reliability electrical connection requirements of the printed circuit board can be effectively achieved.

[0005] The present invention provides an interconnection system for a printed circuit board, including: A design plan module: used to design and plan the interconnection of a printed circuit board according to the key requirements of the current printed circuit board to obtain a preliminary design plan; A simulation module: used to use a set simulation software to simulate and evaluate the interconnection of the current printed circuit board according to the preliminary design plan to obtain a first performance evaluation result; A design optimization module: used to optimize the preliminary design plan according to the first performance evaluation result to obtain an optimized design plan; A production and fine-tuning module: used to produce a printed circuit board and perform fine-tuning based on the optimized design plan to realize the interconnection of the current printed circuit board.

[0006] Preferably, the design plan module includes: A scheme matching unit: obtaining the basic circuit board data and key requirements of the current printed circuit board; Inputting the obtained basic circuit board data and key requirements into a pre-established three-dimensional design plan matching model to obtain a first design plan; Scheme selection unit: if there is only a single first design plan scheme, generating a preliminary design plan based on the first design plan scheme; If there are multiple first design planning schemes, reliability analysis is performed on all the obtained first design planning schemes to obtain a design reliability coefficient; A preliminary design plan is generated based on the first design plan scheme with the largest design reliability coefficient.

[0007] Preferably, reliability analysis is performed on all the first design planning schemes obtained to obtain a design reliability coefficient, including: According to the application scenario of the current printed circuit board, matching the corresponding first evaluation indicator list; Based on the first evaluation indicator list, extracting associated indicator data corresponding to the first evaluation indicator from each first design planning scheme; Evaluate the associated indicator data according to the corresponding set indicator evaluation rules to obtain a first associated score for each first evaluation indicator; Comprehensively analyzing the obtained first correlation score and the influence weight of the first evaluation indicator in the current application scenario included in the first evaluation indicator list to obtain a design reliability coefficient of each first design planning scheme of the current printed circuit board in the current application scenario; The calculation formula of the design reliability coefficient is as follows: ; In the formula, It is expressed as the design reliability coefficient of the i-th first design planning scheme; It is expressed as the first correlation score of the jth first evaluation index corresponding to the i-th first design plan, where j=1, 2, 3, , m; m represents the total number of the first evaluation indicators; It is represented as the influence weight of the jth first evaluation index on the design reliability coefficient of the first design planning scheme in the current application scenario.

[0008] Preferably, the simulation module includes: Modeling and simulation unit: used to establish a three-dimensional model of a target circuit board according to a preliminary design plan by using a set simulation software, and simulate the three-dimensional model of the target circuit board; Monitoring the simulation process of the target circuit board three-dimensional model in real time to obtain first simulation data; A data partitioning unit: configured to partition the first simulation data according to a performance evaluation direction to obtain performance simulation data, and mark the performance evaluation direction on the performance simulation data; Performance evaluation unit: used to use a pre-established performance anomaly identification model to perform anomaly identification on the performance simulation data, and after determining the corresponding simulation performance evaluation results of different performance evaluation directions according to the anomaly identification results, output them as the first performance evaluation result.

[0009] Preferably, the performance evaluation directions include four directions: electrical performance, thermal performance, mechanical performance and electromagnetic compatibility performance.

[0010] Preferably, the performance evaluation unit further includes: If there is no abnormal-performance simulation data in the abnormal identification result, it is determined that the performance of the current printed circuit board is normal under the corresponding performance evaluation direction, and is output as the first performance evaluation result of the current performance evaluation direction; If there is abnormal-performance simulation data in the abnormal identification result, it is determined that the performance of the current printed circuit board is abnormal under the corresponding performance evaluation direction; Calculate the data anomaly coefficient of the current anomaly-performance simulation data according to the deviation value between the anomaly-performance simulation data in the anomaly identification result and the corresponding set threshold range; Determine the performance abnormality coefficient of the current performance evaluation direction by using the data abnormality coefficients of all abnormal-performance simulation data; The abnormality-performance simulation data, the data abnormality coefficient of the abnormality-performance simulation data, and the performance abnormality coefficient are outputted as the first performance evaluation result of the current performance evaluation direction.

[0011] Preferably, the design optimization module includes: A category item determination unit: used for marking the performance evaluation direction with abnormal performance as an abnormal evaluation direction according to the obtained first performance evaluation result; Using the abnormality-performance simulation data included in the first performance evaluation result corresponding to the abnormality evaluation direction as a matching condition, matching and obtaining a first optimization category item from a set optimization database; If the current abnormal-performance simulation data only matches a single first optimization category item, the current first optimization category item is used as the key optimization item; If the current abnormal performance simulation data matches multiple first optimization class items, all the first optimization class items currently obtained are marked as optimization class items to be selected; Obtaining the priority of each candidate optimization item, and grouping the candidate optimization items with the same priority to obtain a first candidate item set; Analyzing the first adaptation coefficient of each to-be-selected optimization category item in the first to-be-selected category item set based on the data anomaly coefficient of the current anomaly-performance simulation data; The calculation formula of the first adaptation coefficient is as follows: ; In the formula, It is represented as the first adaptation coefficient of the current optimization category item to be selected; The data anomaly coefficient of the corresponding anomaly-performance simulation data of the currently selected optimization class item is represented; It is represented as the average value of the data anomaly coefficient of all anomaly-performance simulation data under the current anomaly evaluation direction; It is expressed as the contribution weight of the influence of the current optimization item to be selected on the data anomaly to the calculation of the adaptation coefficient; It is expressed as the historical optimization success rate of the current optimization item to be selected within the preset time period; It is expressed as the average of the historical optimization success rates of all the candidate optimization items that belong to the same first candidate optimization item set as the current candidate optimization item; It is represented as the time interval between the last successful optimization moment of the current optimization item and the current moment; Indicates a preset time period; It is expressed as the contribution weight of the historical optimization status of the selected optimization item to the calculation of the adaptation coefficient; The candidate optimization category item with the largest first adaptation coefficient in the first candidate category item set is used as the corresponding selected optimization item of the current priority level; Comprehensively analyze the first adaptation coefficient of the currently selected optimization item and the priority coefficient of the corresponding priority level to obtain a comprehensive matching score; The selected optimization items whose comprehensive matching scores are greater than the set matching threshold are regarded as key optimization items; Optimization unit: used to summarize the corresponding key optimization items of all abnormal-performance simulation data under the abnormal evaluation direction, and obtain the optimization item list of each abnormal evaluation direction; Based on the list of optimization items, generate the target optimization task for each abnormal evaluation direction; According to the performance anomaly coefficient of the anomaly evaluation direction, all the acquired target optimization tasks are sorted from large to small to obtain a target task list; The preliminary design plan is optimized in sequence according to the target task list to obtain an optimized design plan.

[0012] Preferably, the production and fine-tuning module includes: A manufacturing unit is used to manufacture a printed circuit board according to the optimized design plan, and connect the set electronic components to the printed circuit board for processing and post-processing to form a target printed circuit board; Testing unit: used for performing performance tests in different performance evaluation directions on the target printed circuit board and real-time monitoring to obtain first test data in each performance evaluation direction; Comparing the first test data with a set test threshold range of the corresponding performance evaluation direction, obtaining first test data that does not belong to the set test threshold range, and marking it as adjustment test data; Fine-tuning unit: used to fine-tune the current target printed circuit board by matching corresponding fine-tuning measures according to the acquired adjustment test data as matching conditions; The fine-tuned target printed circuit board is tested again using a test unit until the performance of the target printed circuit board meets the set performance requirements.

[0013] Compared with the prior art, the present invention has the following beneficial effects: By using set simulation software to design the interconnection and interoperability of the printed circuit board according to the key requirements of the printed circuit board to obtain a preliminary design plan, the interconnection and interoperability of the printed circuit board is simulated and the performance is evaluated to obtain a first performance evaluation result; based on the optimized design plan obtained by optimizing the preliminary design plan according to the first performance evaluation result, the interconnection and interoperability of the printed circuit board can effectively achieve high-speed data transmission and high-reliability electrical connection requirements for the printed circuit board.

[0014] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description and the accompanying drawings.

[0015] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings: Figure 1 The figure is a structural diagram of an interconnection system for printed circuit boards according to an embodiment of the present invention. DETAILED DESCRIPTION

[0017] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0018] An embodiment of the present invention provides an interconnection system for a printed circuit board, such as Figure 1 As shown, including: Design planning module: used to design and plan the interconnection of printed circuit boards according to the key requirements of the current printed circuit boards, and obtain a preliminary design plan; Simulation module: used to simulate and evaluate the interconnection and intercommunication of the current printed circuit board according to the preliminary design plan by using the set simulation software to obtain a first performance evaluation result; Design optimization module: used to optimize the preliminary design plan according to the first performance evaluation result to obtain an optimized design plan; Production and fine-tuning module: used to produce and fine-tune printed circuit boards based on the optimized design plan to achieve interconnection and interoperability of the current printed circuit boards.

[0019] In this embodiment, the printed circuit board is one of the core components of the electronic device, provides electrical connections between electronic components, is widely used in computers, communication equipment, consumer electronics and other fields, and is an indispensable part of modern electronic equipment; key requirements include performance requirements, functional requirements, size restrictions and working conditions of the printed circuit board; the preliminary design plan includes design drawings, material lists, process instructions, etc., which are used to provide a data basis for the interconnection of the printed circuit board; the simulation software is set to be a predetermined software for simulating the three-dimensional interconnection of the printed circuit board, such as Altium Designer, Cadence Allegro; the first performance evaluation result includes the evaluation results of four performance evaluation directions of electrical performance, thermal performance, mechanical performance and electromagnetic compatibility performance; the optimized design plan is obtained by optimizing the preliminary design plan based on the first performance evaluation result.

[0020] The beneficial effects of the above technical solution are: by using the set simulation software to design the interconnection and intercommunication of the printed circuit board according to the key requirements of the printed circuit board to obtain a preliminary design plan, the interconnection and intercommunication of the printed circuit board is simulated and the performance is evaluated to obtain a first performance evaluation result; based on the optimized design plan obtained by optimizing the preliminary design plan according to the first performance evaluation result, the interconnection and intercommunication of the printed circuit board can effectively achieve high-speed data transmission and high-reliability electrical connection requirements for the printed circuit board.

[0021] An embodiment of the present invention provides an interconnection system for printed circuit boards, wherein the design planning module includes: Solution matching unit: obtain basic circuit board data and key requirements of the current printed circuit board; Input the acquired basic circuit board data and key requirements into a pre-established three-dimensional design planning matching model to obtain a first design planning solution; Scheme selection unit: if there is only a single first design plan scheme, generating a preliminary design plan based on the first design plan scheme; If there are multiple first design planning schemes, reliability analysis is performed on all the obtained first design planning schemes to obtain a design reliability coefficient; A preliminary design plan is generated based on the first design plan scheme with the largest design reliability coefficient.

[0022] In this embodiment, basic circuit board data refers to basic characteristic data of a printed circuit board, including the size, number of layers, component type, signal frequency, etc. of the circuit board; key requirements include performance requirements, functional requirements, size restrictions, and working conditions of the printed circuit board; a three-dimensional design planning matching model refers to a model constructed by training a neural network using a large amount of design experience and historical design planning data as training data, and is used to output a corresponding matching design scheme based on the input data and requirements; the first design planning scheme is to input the acquired basic circuit board data and key requirements into the three-dimensional design planning matching model, and the matching planning scheme is composed of the layout, wiring, material selection, and component placement of the circuit board; the design reliability coefficient is used to characterize the reliability of the first design planning scheme; the preliminary design plan is generated based on the first design planning scheme, including design drawings, a bill of materials, a process description, and the like.

[0023] The beneficial effect of the above technical solution is: by designing and planning the interconnection and interoperability of the printed circuit board according to the key requirements of the current printed circuit board, a preliminary design plan is obtained, which can provide data support for the interconnection and interoperability of the printed circuit board.

[0024] The embodiment of the present invention provides an interconnection system for a printed circuit board, which performs reliability analysis on all first design planning schemes obtained to obtain a design reliability coefficient, including: According to the application scenario of the current printed circuit board, matching the corresponding first evaluation indicator list; Based on the first evaluation indicator list, extracting associated indicator data corresponding to the first evaluation indicator from each first design planning scheme; Evaluate the associated indicator data according to the corresponding set indicator evaluation rules to obtain a first associated score for each first evaluation indicator; Comprehensively analyzing the obtained first correlation score and the influence weight of the first evaluation indicator in the current application scenario included in the first evaluation indicator list to obtain a design reliability coefficient of each first design planning scheme of the current printed circuit board in the current application scenario; The calculation formula of the design reliability coefficient is as follows: ; In the formula, It is expressed as the design reliability coefficient of the i-th first design planning scheme; It is represented as the first correlation score of the jth first evaluation index corresponding to the i-th first design plan, where j=1, 2, 3, , m; m represents the total number of the first evaluation indicators; It is represented as the influence weight of the jth first evaluation index on the design reliability coefficient of the first design planning scheme in the current application scenario.

[0025] In this embodiment, the application scenario refers to the specific environment or purpose for which the printed circuit board (PCB) is designed, such as a car navigation system, a smart home control center, a high-speed communication device, etc.; the first evaluation index list is composed of the application scenario, the evaluation index and the weight of the evaluation index, wherein the evaluation index includes the reliability data of the component, the layout and wiring information of the circuit board, the signal frequency and amplitude, etc.; the associated index data refers to the specific data extracted from each first design plan and corresponding to the evaluation index in the first evaluation index list, for example, for the reliability data of the component, the associated index data includes the operating temperature range and the expected life of the component; the set index evaluation rule refers to the pre-set criteria for evaluating whether the associated index data meets the requirements of the application scenario, and the specific content is as follows: 1. Obtain the corresponding benchmark scores of all the associated indicator data corresponding to the current first evaluation indicator (the benchmark scores are used to characterize the importance of the associated indicator data to the first evaluation indicator, and are obtained by solving the matrix constructed after pairwise comparison and relative importance scoring using the hierarchical analysis method); 2. If there is a certain correlation indicator data of the current first evaluation indicator that does not meet the corresponding set indicator threshold standard, then the first score is obtained by multiplying the proportion of the corresponding correlation indicator data exceeding the corresponding set indicator threshold with the corresponding benchmark score, and the first score is subtracted from the first correlation score corresponding to the current first evaluation indicator; 3. If there is a certain correlation indicator data that meets the corresponding set indicator threshold standard, then the benchmark score of the current correlation indicator data is added to the first correlation score corresponding to the current first evaluation indicator.

[0026] In this embodiment, the first correlation score refers to the score obtained after evaluating the correlation indicator data according to the set indicator evaluation rules, which is used to characterize the performance of the design planning scheme on the evaluation indicator; the design reliability coefficient is used to measure the reliability of the first design planning scheme in the current application scenario; the weight assigned to the first evaluation indicator is obtained by solving the matrix constructed after pairwise comparison and relative importance scoring using the hierarchical analysis method.

[0027] The beneficial effect of the above technical solution is: by performing reliability analysis on all the first design planning schemes obtained, the design reliability coefficient is obtained, which can provide a data basis for screening suitable planning schemes, thereby facilitating the accurate generation of preliminary design plans.

[0028] An embodiment of the present invention provides an interconnection system for a printed circuit board, wherein the simulation module comprises: Modeling and simulation unit: used to establish a three-dimensional model of a target circuit board according to a preliminary design plan by using a set simulation software, and simulate the three-dimensional model of the target circuit board; Monitoring the simulation process of the target circuit board three-dimensional model in real time to obtain first simulation data; A data partitioning unit: configured to partition the first simulation data according to a performance evaluation direction to obtain performance simulation data, and mark the performance evaluation direction on the performance simulation data; Performance evaluation unit: used to use a pre-established performance anomaly identification model to perform anomaly identification on the performance simulation data, and after determining the corresponding simulation performance evaluation results of different performance evaluation directions according to the anomaly identification results, output them as the first performance evaluation result.

[0029] In this embodiment, the simulation software is set to be a predetermined software for simulating the three-dimensional interconnection of printed circuit boards, such as Altium Designer and Cadence Allegro; the target circuit board three-dimensional model refers to a digital, three-dimensional circuit board representation, which includes all physical properties and electrical connections of the circuit board for subsequent simulation and analysis; the first simulation data is obtained by real-time monitoring of the simulation process of the target circuit board three-dimensional model, including current, voltage, temperature, signal integrity, power consumption, etc.; the performance evaluation direction includes electrical performance, thermal performance, mechanical performance and electromagnetic compatibility performance; the performance anomaly recognition model is used to analyze and identify the performance characteristics of the printed circuit board (PCB) that are not in line with expectations or abnormal during the simulation process based on the input first simulation data.

[0030] The beneficial effect of the above technical solution is that by establishing a three-dimensional model of the printed circuit board and performing simulation and performance evaluation, it can help improve the design accuracy of the interconnection of the printed circuit board, thereby avoiding unnecessary errors and costs in subsequent production and testing.

[0031] An embodiment of the present invention provides an interconnection system for a printed circuit board, wherein the performance evaluation unit further includes: If there is no abnormal-performance simulation data in the abnormal identification result, it is determined that the performance of the current printed circuit board is normal under the corresponding performance evaluation direction, and is output as the first performance evaluation result of the current performance evaluation direction; If there is abnormal-performance simulation data in the abnormal identification result, it is determined that the performance of the current printed circuit board is abnormal under the corresponding performance evaluation direction; Calculate the data anomaly coefficient of the current anomaly-performance simulation data according to the deviation value between the anomaly-performance simulation data in the anomaly identification result and the corresponding set threshold range; Determine the performance abnormality coefficient of the current performance evaluation direction by using the data abnormality coefficients of all abnormal-performance simulation data; The abnormality-performance simulation data, the data abnormality coefficient of the abnormality-performance simulation data, and the performance abnormality coefficient are outputted as the first performance evaluation result of the current performance evaluation direction.

[0032] In this embodiment, the abnormal-performance simulation data refers to data that does not conform to the corresponding set threshold range found by real-time monitoring of the performance parameters of the target circuit board three-dimensional model during the simulation process; the data abnormality coefficient is calculated based on the deviation value between the abnormal-performance simulation data and the corresponding set threshold range, and is used to quantify the severity of the performance abnormality. The formula is as follows: ; In the formula, The data anomaly coefficient expressed as current anomaly-performance simulation data; A data value represented as current abnormal-performance simulation data; It is represented as a set threshold upper limit within a corresponding set threshold range of the current abnormal-performance simulation data; It is expressed as the lower limit of the set threshold value within the corresponding set threshold range of the current abnormal-performance simulation data; the performance abnormality coefficient is expressed as the degree of performance abnormality used to comprehensively evaluate the current performance evaluation direction, and the formula is expressed as ,in, It is represented as the data anomaly coefficient of the cth abnormal-performance simulation data under the current performance evaluation direction, where c=1, 2, 3, , o; o represents the total number of abnormal-performance simulation data under the current performance evaluation direction; It is represented as the influence weight of the cth abnormal-performance simulation data on the analysis performance under the current performance evaluation direction; the weight assigned to the abnormal-performance simulation data is obtained by solving the matrix constructed after pairwise comparison and relative importance scoring using the hierarchical analysis method.

[0033] The beneficial effect of the above technical solution is that by determining the corresponding performance evaluation results of different performance evaluation directions according to the abnormality recognition results, a clear direction can be provided for subsequent optimization, thereby improving the optimization efficiency.

[0034] An embodiment of the present invention provides an interconnection system for a printed circuit board, wherein the design optimization module comprises: A category item determination unit: used for marking the performance evaluation direction with abnormal performance as an abnormal evaluation direction according to the obtained first performance evaluation result; Using the abnormality-performance simulation data included in the first performance evaluation result corresponding to the abnormality evaluation direction as a matching condition, matching and obtaining a first optimization category item from a set optimization database; If the current abnormal-performance simulation data only matches a single first optimization category item, the current first optimization category item is used as the key optimization item; If the current abnormal performance simulation data matches multiple first optimization class items, all the first optimization class items currently obtained are marked as optimization class items to be selected; Obtaining the priority of each candidate optimization item, and grouping the candidate optimization items with the same priority to obtain a first candidate item set; Analyzing the first adaptation coefficient of each to-be-selected optimization category item in the first to-be-selected category item set based on the data anomaly coefficient of the current anomaly-performance simulation data; The calculation formula of the first adaptation coefficient is as follows: ; In the formula, It is represented as the first adaptation coefficient of the current optimization category item to be selected; The data anomaly coefficient of the corresponding anomaly-performance simulation data of the currently selected optimization class item is represented; It is represented as the average value of the data anomaly coefficient of all anomaly-performance simulation data under the current anomaly evaluation direction; It is expressed as the contribution weight of the influence of the current optimization item to be selected on the data anomaly to the calculation of the adaptation coefficient; It is expressed as the historical optimization success rate of the current optimization item to be selected within the preset time period; It is expressed as the average of the historical optimization success rates of all the candidate optimization items that belong to the same first candidate optimization item set as the current candidate optimization item; It is represented as the time interval between the last successful optimization moment of the current optimization item and the current moment; Indicates a preset time period; It is expressed as the contribution weight of the historical optimization status of the selected optimization item to the calculation of the adaptation coefficient; The candidate optimization category item with the largest first adaptation coefficient in the first candidate category item set is used as the corresponding selected optimization item of the current priority level; Comprehensively analyze the first adaptation coefficient of the currently selected optimization item and the priority coefficient of the corresponding priority level to obtain a comprehensive matching score; The selected optimization items whose comprehensive matching scores are greater than the set matching threshold are regarded as key optimization items; Optimization unit: used to summarize the corresponding key optimization items of all abnormal-performance simulation data under the abnormal evaluation direction, and obtain the optimization item list of each abnormal evaluation direction; Based on the list of optimization items, generate the target optimization task for each abnormal evaluation direction; According to the performance anomaly coefficient of the anomaly evaluation direction, all the acquired target optimization tasks are sorted from large to small to obtain a target task list; The preliminary design plan is optimized in sequence according to the target task list to obtain an optimized design plan.

[0035] In this embodiment, the abnormal evaluation direction refers to the performance evaluation direction of the performance abnormality; the first optimization category item is an optimization category item obtained by matching the abnormal-performance simulation data contained in the corresponding first performance evaluation result of the abnormal evaluation direction from the set optimization database, such as adjusting component layout, changing components, etc.

[0036] In this embodiment, the selected optimization items refer to multiple first optimization items matched to the current abnormality-performance simulation data; the priority level is used to express the priority of each optimization item; the first set of selected items is obtained by the set of selected optimization items with the same priority level; the first adaptation coefficient is used to characterize the degree of adaptation between each selected optimization item in the same first set of selected items and the current abnormality-performance simulation data; the weights assigned to the influence of the selected optimization items on the data abnormality and the historical optimization status of the selected optimization items are obtained by solving the matrix constructed after pairwise comparison and relative importance scoring using the hierarchical analysis method; the selected optimization item refers to the selected optimization item with the largest first adaptation coefficient in the first set of selected items; the comprehensive matching score is used to characterize the degree of matching between the selected optimization item and the current abnormality-performance simulation data; the matching threshold is set in advance, generally 0.75; The calculation formula of the comprehensive matching score is as follows: ; In the formula, Z1 represents the comprehensive matching score of the currently selected optimization item; It is represented as the first adaptation coefficient of the currently selected optimization item; It is expressed as the priority coefficient of the priority level to which the currently selected optimization item belongs; Indicates the used time of the component associated with the currently selected optimization item; Represents the initial expected life of the component associated with the currently selected optimization item; It is expressed as the trend change coefficient of the priority level to which the currently selected optimization item belongs; It is expressed as a constant with a value of 2.7. The trend change coefficient is determined in advance based on the analysis of the success rate, application frequency and feedback effect of the optimization items included in each priority level in the past period of time to identify the development trends of different priority levels. It is used to reflect the development trends of all corresponding optimization items included in different priority levels in the future preset time. When the trend change coefficient is a positive number, it means that the priority coefficient of the corresponding priority level increases with time, and the feasibility of the corresponding priority item increases with time; when the trend change coefficient is a negative number, it means that the priority coefficient of the corresponding priority level decreases with time, and the feasibility of the corresponding priority item decreases with time. Among them, the priority coefficient is determined in advance based on the constraints of time, cost and human resources, and is used to express the available priority level of all corresponding optimization items included in each priority level.

[0037] In this embodiment, the optimization item list is a collection of key optimization items matched and screened from a set optimization database based on the abnormal evaluation direction and the corresponding abnormality-performance simulation data; the target optimization task is generated based on the optimization item list, and is a specific optimization step for different abnormal evaluation directions, such as adjusting component layout, changing component type, optimizing system parameters and other specific operation steps; the target task list is obtained by sorting all the acquired target optimization tasks from large to small according to the performance abnormality coefficient of the abnormal evaluation direction; the optimized design plan is obtained by sequentially optimizing the preliminary design plan according to the target task list.

[0038] The beneficial effect of the above technical solution is: by obtaining key optimization items according to the first performance evaluation result to optimize the preliminary design plan, an optimized design plan is obtained, which can ensure the targetedness and effectiveness of the optimization and improve the design optimization efficiency.

[0039] An embodiment of the present invention provides an interconnection system for printed circuit boards, wherein the manufacturing and fine-tuning module comprises: A manufacturing unit is used to manufacture a printed circuit board according to the optimized design plan, and connect the set electronic components to the printed circuit board for processing and post-processing to form a target printed circuit board; Testing unit: used for performing performance tests in different performance evaluation directions on the target printed circuit board and real-time monitoring to obtain first test data in each performance evaluation direction; Comparing the first test data with a set test threshold range of the corresponding performance evaluation direction, obtaining first test data that does not belong to the set test threshold range, and marking it as adjustment test data; Fine-tuning unit: used to fine-tune the current target printed circuit board by taking the adjustment test data as the matching condition and matching the corresponding fine-tuning measures; The fine-tuned target printed circuit board is tested again using a test unit until the performance of the target printed circuit board meets the set performance requirements.

[0040] In this embodiment, the target printed circuit board refers to a circuit board that is manufactured using a specific process and post-processed according to an optimized design plan, and the required electronic components have been connected; post-processing refers to the surface treatment and packaging protection of the circuit board; the performance evaluation direction includes electrical performance, thermal performance, mechanical performance and electromagnetic compatibility performance; the first test data refers to the data monitored and recorded in real time when the target printed circuit board is subjected to performance tests in different performance evaluation directions; setting the test threshold range is a predetermined standard for evaluating whether the target printed circuit board is qualified in each performance evaluation direction; the fine-tuning measures are targeted corrective measures taken according to the problems reflected by the adjustment test data (i.e., the first test data that exceeds the set test threshold range), including modifying the circuit board layout, adjusting the component position, replacing the component, optimizing the circuit parameters, etc.; setting the performance requirements refers to the expected performance requirements for the target printed circuit board in each performance evaluation direction.

[0041] The beneficial effect of the above technical solution is that by manufacturing and fine-tuning the printed circuit board based on the optimized design plan, it can be ensured that the target printed circuit board meets the set performance requirements in all performance evaluation directions, that is, effectively realizing the high-speed data transmission and high-reliability electrical connection requirements for the printed circuit board.

[0042] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. An interconnection system for printed circuit boards, characterized in that: include: Design planning module: used to design and plan the interconnection of printed circuit boards according to the key requirements of the current printed circuit boards, and obtain a preliminary design plan; Simulation module: used to simulate and evaluate the interconnection and intercommunication of the current printed circuit board according to the preliminary design plan by using the set simulation software to obtain a first performance evaluation result; Design optimization module: used to optimize the preliminary design plan according to the first performance evaluation result to obtain an optimized design plan; Production and fine-tuning module: used to produce and fine-tune printed circuit boards based on the optimized design plan to achieve interconnection and interoperability of the current printed circuit boards.

2. The interconnection system for printed circuit boards according to claim 1, characterized in that: The design planning module includes: Solution matching unit: obtain basic circuit board data and key requirements of the current printed circuit board; Input the acquired basic circuit board data and key requirements into a pre-established three-dimensional design planning matching model to obtain a first design planning solution; Scheme selection unit: if there is only a single first design plan scheme, generating a preliminary design plan based on the first design plan scheme; If there are multiple first design planning schemes, reliability analysis is performed on all the obtained first design planning schemes to obtain a design reliability coefficient; A preliminary design plan is generated based on the first design plan scheme with the largest design reliability coefficient.

3. The interconnection system for printed circuit boards according to claim 2, characterized in that: Reliability analysis is performed on all the first design planning schemes obtained to obtain the design reliability coefficient, including: According to the application scenario of the current printed circuit board, matching the corresponding first evaluation indicator list; Based on the first evaluation indicator list, extracting associated indicator data corresponding to the first evaluation indicator from each first design planning scheme; Evaluate the associated indicator data according to the corresponding set indicator evaluation rules to obtain a first associated score for each first evaluation indicator; Comprehensively analyzing the obtained first correlation score and the influence weight of the first evaluation indicator in the current application scenario included in the first evaluation indicator list to obtain a design reliability coefficient of each first design planning scheme of the current printed circuit board in the current application scenario; The calculation formula of the design reliability coefficient is as follows: ; In the formula, It is expressed as the design reliability coefficient of the i-th first design planning scheme; It is expressed as the first correlation score of the jth first evaluation index corresponding to the i-th first design plan, where j=1, 2, 3, , m; m represents the total number of the first evaluation indicators; It is represented as the influence weight of the jth first evaluation index on the design reliability coefficient of the first design planning scheme in the current application scenario.

4. The interconnection system for printed circuit boards according to claim 1, characterized in that: The simulation module comprises: Modeling and simulation unit: used to establish a three-dimensional model of a target circuit board according to a preliminary design plan by using a set simulation software, and simulate the three-dimensional model of the target circuit board; Monitoring the simulation process of the target circuit board three-dimensional model in real time to obtain first simulation data; A data partitioning unit: configured to partition the first simulation data according to a performance evaluation direction to obtain performance simulation data, and mark the performance evaluation direction on the performance simulation data; Performance evaluation unit: used to use a pre-established performance anomaly identification model to perform anomaly identification on the performance simulation data, and after determining the corresponding simulation performance evaluation results of different performance evaluation directions according to the anomaly identification results, output them as the first performance evaluation result.

5. The interconnection system for printed circuit boards according to claim 1, characterized in that: The performance evaluation directions include electrical performance, thermal performance, mechanical performance and electromagnetic compatibility performance.

6. The interconnection system for printed circuit boards according to claim 4, characterized in that: The performance evaluation unit further includes: If there is no abnormal-performance simulation data in the abnormal identification result, it is determined that the performance of the current printed circuit board is normal under the corresponding performance evaluation direction, and the result is output as the first performance evaluation result of the current performance evaluation direction; If there is abnormal-performance simulation data in the abnormal identification result, it is determined that the performance of the current printed circuit board is abnormal under the corresponding performance evaluation direction; Calculate the data anomaly coefficient of the current anomaly-performance simulation data according to the deviation value between the anomaly-performance simulation data in the anomaly identification result and the corresponding set threshold range; Determine the performance abnormality coefficient of the current performance evaluation direction by using the data abnormality coefficients of all abnormal-performance simulation data; The abnormality-performance simulation data, the data abnormality coefficient of the abnormality-performance simulation data, and the performance abnormality coefficient are outputted as the first performance evaluation result of the current performance evaluation direction.

7. The interconnection system for printed circuit boards according to claim 1, characterized in that: The design optimization module comprises: A category item determination unit: used for marking the performance evaluation direction with abnormal performance as an abnormal evaluation direction according to the obtained first performance evaluation result; Using the abnormality-performance simulation data included in the first performance evaluation result corresponding to the abnormality evaluation direction as a matching condition, matching and obtaining a first optimization category item from a set optimization database; If the current abnormal-performance simulation data only matches a single first optimization category item, the current first optimization category item is used as the key optimization item; If the current abnormal performance simulation data matches multiple first optimization class items, all the first optimization class items currently obtained are marked as optimization class items to be selected; Obtaining the priority of each candidate optimization item, and grouping the candidate optimization items with the same priority to obtain a first candidate item set; Analyzing the first adaptation coefficient of each to-be-selected optimization category item in the first to-be-selected category item set based on the data anomaly coefficient of the current anomaly-performance simulation data; The calculation formula of the first adaptation coefficient is as follows: ; In the formula, It is represented as the first adaptation coefficient of the current optimization category item to be selected; The data anomaly coefficient of the corresponding anomaly-performance simulation data of the currently selected optimization class item is represented; It is represented as the average value of the data anomaly coefficient of all anomaly-performance simulation data under the current anomaly evaluation direction; It is expressed as the contribution weight of the influence of the current optimization item to be selected on the data anomaly to the calculation of the adaptation coefficient; It is expressed as the historical optimization success rate of the current optimization item to be selected within the preset time period; It is expressed as the average of the historical optimization success rates of all the candidate optimization items that belong to the same first candidate optimization item set as the current candidate optimization item; It is represented as the time interval between the last successful optimization moment of the current optimization item and the current moment; Indicates a preset time period; It is expressed as the contribution weight of the historical optimization status of the selected optimization item to the calculation of the adaptation coefficient; The candidate optimization category item with the largest first adaptation coefficient in the first candidate category item set is used as the corresponding selected optimization item of the current priority level; Comprehensively analyze the first adaptation coefficient of the currently selected optimization item and the priority coefficient of the corresponding priority level to obtain a comprehensive matching score; Optimization unit: used to summarize the corresponding key optimization items of all abnormal-performance simulation data under the abnormal evaluation direction, and obtain the optimization item list of each abnormal evaluation direction; Based on the list of optimization items, generate the target optimization task for each abnormal evaluation direction; According to the performance anomaly coefficient of the anomaly evaluation direction, all the acquired target optimization tasks are sorted from large to small to obtain a target task list; The preliminary design plan is optimized in sequence according to the target task list to obtain an optimized design plan.

8. The interconnection system for printed circuit boards according to claim 1, characterized in that: The production and fine-tuning module includes: A manufacturing unit is used to manufacture a printed circuit board according to the optimized design plan, and connect the set electronic components to the printed circuit board for processing and post-processing to form a target printed circuit board; Testing unit: used for performing performance tests in different performance evaluation directions on the target printed circuit board and real-time monitoring to obtain first test data in each performance evaluation direction; Comparing the first test data with a set test threshold range of the corresponding performance evaluation direction, obtaining first test data that does not belong to the set test threshold range, and marking it as adjustment test data; Fine-tuning unit: used to fine-tune the current target printed circuit board by taking the adjustment test data as the matching condition and matching the corresponding fine-tuning measures; The fine-tuned target printed circuit board is tested again using a test unit until the performance of the target printed circuit board meets the set performance requirements.

Images