SRAM memory cell and layout thereof

Abstract

The invention provides an SRAM (Static Random Access Memory) storage unit. The SRAM storage unit comprises a 6-transistor SRAM structure and a 5-transistor aXNOR structure, source electrodes of the PM0 and the PM1 are connected with a storage unit working power supply VDD, and drain electrodes of the PM0 and the PM1 are respectively connected with drain electrodes of the NM0 and the NM1; the grid electrode of the PM0 is connected with the grid electrode of the NM0 to form a first storage node QB, and the grid electrode of the PM1 is connected with the grid electrode of the NM1 to form a second storage node Q; source electrodes of the NM0 and the NM1 are connected with a ground wire VSS; the drain electrode of the NM2 is connected with a signal BL, the source electrode is connected with a first storage node Q, and the grid electrode is connected with a signal WL; the source electrode of the NM3 is connected with a signal BLB, the drain electrode is connected with a second storage node QB, and the grid electrode is connected with a signal WL; source electrodes of the PM6 and the PM7 are connected, a grid electrode of the PM6 is connected with a first storage node Q, a grid electrode of the PM7 is connected with a second storage node QB, a drain electrode of the PM6 is connected with a characteristic data signal XIN (1), and a drain electrode of the PM7 is connected with a characteristic data signal XIN (0). Compared with a capacitance coupling type unit, the 11 transistor SRAM has more stable current driving capability, and 10% of layout area can be saved under the same function.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a SRAM memory cell and its layout. Background Art

[0002] With the development of technologies such as cloud computing and artificial intelligence, we have entered the big data era. In the past few decades, the development of memory and processors has been seriously unbalanced, and the improvement of the memory reading speed has far lagged behind the growth of processor performance. The performance bottleneck of the traditional von Neumann computing architecture in data-intensive computing has become increasingly obvious. The concept of the von Neumann bottleneck was first proposed by John Backus in 1977: Since the CPU and the memory share the same system bus, and there is a huge speed difference between the CPU and the memory, the CPU is constantly forced to wait for data to be read or written to the memory, thus curbing the throughput of the CPU.

[0003] In recent years, the computing-in-memory architecture has received increasing attention and is expected to become a new architecture to break through the von Neumann bottleneck. Computing-in-memory is to move part or all of the computing into the memory, enabling the memory cell to have computing functions (such as Figure 1 ). Such an architecture eliminates data access latency and power consumption, breaks through the von Neumann bottleneck, and is unanimously regarded by the industrial and academic circles as the future development trend.

[0004] SRAM is currently the only storage medium that is fully compatible with advanced CMOS processes and can be mass-produced on a large scale. The compatibility of SRAM with advanced processes makes its peripheral logic interface most meet the requirements of current efficient utilization of macro cells. The design technology of SRAM is very mature. Compared with new non-volatile memories, the manufacturing process, R & D tools, and CMOS integrated circuit models of SRAM are more mature and stable. At the same time, SRAM has a faster operation speed and durability, can refresh computing data in the computing-in-memory unit in real time, and provides an important guarantee for high computing power.

[0005] There are many types of SRAM memory cells used in current computing-in-memory circuits. Different SRAM structures are used according to different applications and different computing requirements. The layout of the existing dual 6-transistor dual-word-line SRAM Cell (such as Figure 2 ) is not a traditional symmetric structure. Coupled with the requirements of dual-word-line routing, the area of a single memory cell increases significantly, about twice that of a conventional 6-transistor SRAM. If a dual 6-transistor dual-word-line SRAM Cell is used, the area is 4 times that of a conventional 6T SRAM.

[0006] To solve the above problems, a new type of SRAM memory cell and its layout need to be proposed. Summary of the Invention

[0007] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide an SRAM storage cell and its layout, which is used to solve the problem that the layout of the dual 6-transistor dual-word line SRAM Cell in the prior art is not a traditional symmetrical structure, and the area of ​​a single storage cell is significantly increased due to the requirement of dual word line routing.

[0008] To achieve the above-mentioned and other related purposes, the present invention provides a SRAM storage cell and its layout, including:

[0009] A 6-transistor SRAM structure and a 5-transistor aXNOR structure;

[0010] The 6-transistor SRAM structure includes:

[0011] Transistors NM2, NM3, PM0, PM1 and transistors NM0, NM1; wherein,

[0012] NM0 and NM1 are pull-down tubes, PM0 and PM1 are riser tubes, and NM2 and NM3 are transmission tubes;

[0013] The sources of PM0 and PM1 are connected to the storage unit working power supply VDD, and the drains of PM0 and PM1 are connected to the drains of NM0 and NM1 respectively;

[0014] The gate of PM0 is connected to the gate of NM0 to form a first storage node QB, and the gate of PM1 is connected to the gate of NM1 to form a second storage node Q;

[0015] The source of NM0 and NM1 is connected to the ground line VSS;

[0016] The drain of NM2 is connected to the signal BL, the source is connected to the first storage node Q, and the gate is connected to the signal WL;

[0017] The source of NM3 is connected to the signal BLB, the drain is connected to the second storage node QB, and the gate is connected to the signal WL;

[0018] The 5-transistor aXNOR structure consists of:

[0019] Transistors PM6, PM7 and transistors NM7, NM8, NM59;

[0020] The sources of PM6 and PM7 are connected, the gate of PM6 is connected to the first storage node Q, the gate of PM7 is connected to the second storage node QB, the drain of PM6 is connected to the characteristic data signal XIN(1), and the drain of PM7 is connected to the characteristic data signal XIN(0);

[0021] The drain of NM59 is connected to the sources of PM6 and PM7, and the gate of NM59 is connected to the operation enable signal COM_EN;

[0022] The gates of NM7 and NM8 are connected to each other, the gate and drain of NM7 are short-circuited and then connected to the source of NM59, and the sources of NM7 and NM8 are connected to the voltage VSS.

[0023] Preferably, the transistors NM0 to NM3 and the transistors NM7, NM8, NM59 are all NMOS, and the transistors PM0, PM1, PM6, PM7 are all PMOS.

[0024] Preferably, the substrate electrodes of the PMOS are connected to a working power supply VDD, and the substrate electrodes of the NMOS are connected to a voltage VSS.

[0025] Preferably, the characteristic data signal XIN(0) and the characteristic data signal XIN(1) are used to characterize the characteristic data IN; if the characteristic data signal XIN(0) is 0 and the characteristic data signal XIN(1) is 1, the logic definition is 0; if the characteristic data signal XIN(0) is 1 and the characteristic data signal XIN(1) is 0, the logic definition is 1.

[0026] Preferably, the first storage node Q and the second storage node QB are used to characterize the weight parameter W; if the first storage node Q is 0 and the second storage node QB is 1, the logic definition is 0; if the first storage node Q is 1 and the second storage node QB is 0, the logic definition is 1.

[0027] Preferably, the sources of PM6 and PM7 are connected to form an XOR node; if the operation enable signal COM_EN is 1, the characteristic data IN is 0, and the weight parameter W is 0, then the operation truth value IXBL of the XOR node is 0, and the operation truth value IXNOR of the drain of NM8 is 0; if the operation enable signal COM_EN is 1, the characteristic data IN is 0, and the weight parameter W is 1, then the operation truth value IXBL of the XOR node is 1, and the operation truth value IXNOR of the drain of NM8 is 1; if the operation enable signal COM_EN is is 1, the characteristic data IN is 1, and the weight parameter W is 0, then the operation truth value IXBL of the XOR node is 1, and the operation truth value IXNOR of the drain of NM8 is 1; if the operation enable signal COM_EN is 1, the characteristic data IN is 1, and the weight parameter W is 1, then the operation truth value IXBL of the XOR node is 0, and the operation truth value IXNOR of the drain of NM8 is 0; if the operation enable signal COM_EN is 0, then the operation truth value IXBL of the XOR node is 0, and the operation truth value IXNOR of the drain of NM8 is 0.

[0028] Preferably, the SRAM storage unit is applied to a storage-computation-in-one circuit.

[0029] The present invention also provides a layout of the above-mentioned SRAM storage unit, including:

[0030] 6-transistor SRAM pattern and 5-transistor aXNOR pattern;

[0031] The 6-transistor SRAM pattern and the 5-transistor aXNOR pattern respectively include: an active area pattern and a polysilicon pattern spanning the active area pattern; a contact hole pattern located on the active area pattern and distributed on one side of the polysilicon pattern;

[0032] The 6-transistor SRAM graphics include:

[0033] Transistor NM2, NM3, PM0, PM1 graphics and transistor NM0, NM1 graphics; wherein,

[0034] The transistors NM0 and NM1 are shown as pull-down tubes, the transistors PM0 and PM1 are shown as riser tubes, and the transistors NM2 and NM3 are shown as transmission tubes.

[0035] The 5-transistor aXNOR pattern includes:

[0036] The graphs of transistors PM6 and PM7 and transistors NM7, NM8 and NM59;

[0037] Among them, the transistor PM6 and PM7 graphics are located between the transistor PM0 and PM1 graphics in the 6-transistor SRAM graphics, the transistor NM7, NM8, and NM59 graphics are located in the design area near the 6-transistor SRAM graphics, and the transistor NM7, NM8, and NM59 graphics are connected to the transistor PM6 and PM7 graphics through the metal layer graphics.

[0038] Preferably, the transistors PM6 and PM7 are graphically arranged symmetrically.

[0039] Preferably, the graphics of the transistors NM0 and NM3 are located on a first side close to the graphics of the transistor PM0, and the graphics of the transistors NM0, NM1, NM7, NM8 and NM59 are located on a second side close to the graphics of the transistor PM1.

[0040] As described above, the SRAM storage cell and its layout of the present invention have the following beneficial effects:

[0041] Compared with the capacitive coupling type unit, the 11-transistor SRAM of the present invention has a more robust current driving capability and can save 10% of the layout area under the same function. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A schematic diagram showing a comparison between the prior art von Neumann computing architecture and the storage-computing integrated computing architecture;

[0043] Figure 2Schematic diagram of a 12-transistor SRAM memory and computing integrated circuit structure shown as the prior art;

[0044] Figure 3 Schematic diagram of a 11-transistor SRAM memory and computing integrated circuit structure of the present invention;

[0045] Figure 4 Schematic layout diagram of a 11-transistor SRAM memory cell of the present invention;

[0046] Figure 5 Schematic diagram of the logical definition of the feature data IN and the weight parameter W of the present invention;

[0047] Figure 6 Schematic diagram of the truth table of the exclusive OR operation of the present invention. Detailed implementation manners

[0048] The following specific examples illustrate the implementation manners of the present invention. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0049] Please refer to Figure 3 , the present invention provides an SRAM memory cell and its layout, including:

[0050] A 6-transistor SRAM structure and a 5-transistor aXNOR structure;

[0051] The 6-transistor SRAM structure includes:

[0052] Transistors NM2, NM3, PM0, PM1 and transistors NM0, NM1; wherein,

[0053] NM0 and NM1 are pull-down transistors, PM0 and PM1 are pull-up transistors, and NM2 and NM3 are transfer transistors;

[0054] The sources of PM0 and PM1 are connected to the operating power supply VDD of the memory cell, and the drains of PM0 and PM1 are respectively connected to the drains of NM0 and NM1;

[0055] The gate of PM0 is connected to the gate of NM0 to form the first storage node QB, and the gate of PM1 is connected to the gate of NM1 to form the second storage node Q;

[0056] The sources of NM0 and NM1 are connected to the ground wire VSS;

[0057] The drain of NM2 is connected to the signal BL, the source is connected to the first storage node Q, and the gate is connected to the signal WL;

[0058] The source of NM3 is connected to the signal BLB, the drain is connected to the second storage node QB, and the gate is connected to the signal WL;

[0059] The 5-transistor aXNOR structure consists of:

[0060] Transistors PM6, PM7 and transistors NM7, NM8, NM59;

[0061] The sources of PM6 and PM7 are connected, the gate of PM6 is connected to the first storage node Q, the gate of PM7 is connected to the second storage node QB, the drain of PM6 is connected to the characteristic data signal XIN(1), and the drain of PM7 is connected to the characteristic data signal XIN(0);

[0062] The drain of NM59 is connected to the sources of PM6 and PM7, and the gate of NM59 is connected to the operation enable signal COM_EN;

[0063] The gates of NM7 and NM8 are connected to each other, the gate and drain of NM7 are short-circuited and then connected to the source of NM59, and the sources of NM7 and NM8 are connected to the voltage VSS.

[0064] The 5-transistor aXNOR structure has two feature data input ports Feature Port and operation enable signal input port COM_EN Port; the input feature data IN and weight parameter W are processed by the 5-transistor aXNOR structure to perform a single-bit XOR operation to obtain the analog current result, which is accumulated on the XBL bus. Compared with the capacitive coupling type unit, the main advantage of the 11-transistor SRAM is that it has a more robust current driving capability.

[0065] In the embodiment of the present invention, the transistors NM0 to NM3 and the transistors NM7 , NM8 , and NM59 are all NMOS, and the transistors PM0 , PM1 , PM6 , and PM7 are all PMOS.

[0066] In the embodiment of the present invention, the substrate electrodes of the PMOS are all connected to the working power supply VDD, and the substrate electrodes of the NMOS are all connected to the voltage VSS.

[0067] In the embodiments of the present invention, please refer to Figure 5, the characteristic data signal XIN(0) and the characteristic data signal XIN(1) are used to characterize the characteristic data IN; if the characteristic data signal XIN(0) is 0 and the characteristic data signal XIN(1) is 1, the logic definition is 0; if the characteristic data signal XIN(0) is 1 and the characteristic data signal XIN(1) is 0, the logic definition is 1. The first storage node Q and the second storage node QB are used to characterize the weight parameter W; if the first storage node Q is 0 and the second storage node QB is 1, the logic definition is 0; if the first storage node Q is 1 and the second storage node QB is 0, the logic definition is 1.

[0068] In the embodiments of the present invention, please refer to Figure 6 , the sources of PM6 and PM7 are connected to form an XOR node; if the operation enable signal COM_EN is 1, the characteristic data IN is 0, and the weight parameter W is 0, then the operation truth value IXBL of the XOR node is 0, and the operation truth value IXNOR of the drain of NM8 is 0; if the operation enable signal COM_EN is 1, the characteristic data IN is 0, and the weight parameter W is 1, then the operation truth value IXBL of the XOR node is 1, and the operation truth value IXNOR of the drain of NM8 is 1; if the operation enable signal COM_EN is 1 , the characteristic data IN is 1, and the weight parameter W is 0, then the operation truth value IXBL of the XOR node is 1, and the operation truth value IXNOR of the drain of NM8 is 1; if the operation enable signal COM_EN is 1, the characteristic data IN is 1, and the weight parameter W is 1, then the operation truth value IXBL of the XOR node is 0, and the operation truth value IXNOR of the drain of NM8 is 0; if the operation enable signal COM_EN is 0, then the operation truth value IXBL of the XOR node is 0, and the operation truth value IXNOR of the drain of NM8 is 0.

[0069] In an embodiment of the present invention, the SRAM storage unit is applied to a storage-computation-in-one circuit.

[0070] See also Figure 4 The present invention also provides a layout of the above-mentioned SRAM storage unit, including:

[0071] 6-transistor SRAM pattern and 5-transistor aXNOR pattern;

[0072] The 6-transistor SRAM pattern and the 5-transistor aXNOR pattern respectively include: an active region pattern and a polysilicon pattern spanning the active region pattern; a contact hole pattern located on the active region pattern and distributed on one side of the polysilicon pattern;

[0073] The 6-transistor SRAM graphics include:

[0074] Transistor NM2, NM3, PM0, PM1 graphics and transistor NM0, NM1 graphics; wherein,

[0075] The transistors NM0 and NM1 are shown as pull-down tubes, the transistors PM0 and PM1 are shown as riser tubes, and the transistors NM2 and NM3 are shown as transmission tubes.

[0076] The 5-transistor aXNOR pattern includes:

[0077] The graphs of transistors PM6 and PM7 and transistors NM7, NM8 and NM59;

[0078] Among them, the transistor PM6 and PM7 graphics are located between the transistor PM0 and PM1 graphics in the 6-transistor SRAM graphics, the transistor NM7, NM8, and NM59 graphics are located in the design area near the 6-transistor SRAM graphics, and the transistor NM7, NM8, and NM59 graphics are connected to the transistor PM6 and PM7 graphics through the metal layer graphics. This also saves the layout implementation. Only the area of ​​5 additional transistors needs to be added to the 6-transistor SRAM graphics, which can save 10% of the area with the same function.

[0079] In the embodiment of the present invention, transistors PM6 and PM7 are graphically arranged symmetrically.

[0080] In the embodiment of the present invention, the transistors NM0 and NM3 patterns are located on a first side close to the transistor PM0 pattern, and the transistors NM0, NM1, NM7, NM8, and NM59 patterns are located on a second side close to the transistor PM1 pattern.

[0081] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0082] In summary, compared with the capacitive coupling type unit, the 11-transistor SRAM of the present invention has a more robust current driving capability and can save 10% of the layout area under the same function. Therefore, the present invention effectively overcomes various shortcomings of the prior art and has a high industrial utilization value.

[0083] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A SRAM storage cell, characterized in that: include: A 6-transistor SRAM structure and a 5-transistor aXNOR structure; The 6-transistor SRAM structure includes: Transistors NM2, NM3, PM0, PM1 and transistors NM0, NM1; wherein, NM0 and NM1 are pull-down tubes, PM0 and PM1 are riser tubes, and NM2 and NM3 are transmission tubes; The sources of PM0 and PM1 are connected to the storage unit working power supply VDD, and the drains of PM0 and PM1 are connected to the drains of NM0 and NM1 respectively; The gate of PM0 is connected to the gate of NM0 to form a first storage node QB, and the gate of PM1 is connected to the gate of NM1 to form a second storage node Q; The source of NM0 and NM1 is connected to the ground line VSS; The drain of NM2 is connected to the signal BL, the source is connected to the first storage node Q, and the gate is connected to the signal WL; The source of NM3 is connected to the signal BLB, the drain is connected to the second storage node QB, and the gate is connected to the signal WL; The 5-transistor aXNOR structure consists of: Transistors PM6, PM7 and transistors NM7, NM8, NM59; The sources of PM6 and PM7 are connected, the gate of PM6 is connected to the first storage node Q, the gate of PM7 is connected to the second storage node QB, the drain of PM6 is connected to the characteristic data signal XIN(1), and the drain of PM7 is connected to the characteristic data signal XIN(0); The drain of NM59 is connected to the sources of PM6 and PM7, and the gate of NM59 is connected to the operation enable signal COM_EN; The gates of NM7 and NM8 are connected to each other, the gate and drain of NM7 are short-circuited and then connected to the source of NM59, and the sources of NM7 and NM8 are connected to the voltage VSS.

2. The SRAM storage cell according to claim 1, wherein: The transistors NM0 to NM3 and the transistors NM7, NM8, and NM59 are all NMOS, and the transistors PM0, PM1, PM6, and PM7 are all PMOS.

3. The SRAM storage cell according to claim 2, characterized in that: The substrate electrodes of the PMOS are all connected to a working power supply VDD, and the substrate electrodes of the NMOS are all connected to a voltage VSS.

4. The SRAM storage cell according to claim 1, wherein: The characteristic data signal XIN(0) and the characteristic data signal XIN(1) are used to represent the characteristic data IN; If the characteristic data signal XIN(0) is 0 and the characteristic data signal XIN(1) is 1, the logic definition is 0; if the characteristic data signal XIN(0) is 1 and the characteristic data signal XIN(1) is 0, the logic definition is 1.

5. The SRAM storage cell according to claim 4, characterized in that: The first storage node Q and the second storage node QB are used to represent the weight parameter W; if the first storage node Q is 0 and the second storage node QB is 1, the logic definition is 0; If the first storage node Q is 1 and the second storage node QB is 0, the logic is defined as 1.

6. The SRAM storage cell according to claim 5, characterized in that: The sources of PM6 and PM7 are connected to form an XOR node; if the operation enable signal COM_EN is 1, the characteristic data IN is 0, and the weight parameter W is 0, then the operation truth value IXBL of the XOR node is 0, and the operation truth value IXNOR of the drain of NM8 is 0; if the operation enable signal COM_EN is 1, the characteristic data IN is 0, and the weight parameter W is 1, then the operation truth value IXBL of the XOR node is 1, and the operation truth value IXNOR of the drain of NM8 is 1; if the operation enable signal COM_EN is 1 , the characteristic data IN is 1, and the weight parameter W is 0, then the operation truth value IXBL of the XOR node is 1, and the operation truth value IXNOR of the drain of NM8 is 1; if the operation enable signal COM_EN is 1, the characteristic data IN is 1, and the weight parameter W is 1, then the operation truth value IXBL of the XOR node is 0, and the operation truth value IXNOR of the drain of NM8 is 0; if the operation enable signal COM_EN is 0, then the operation truth value IXBL of the XOR node is 0, and the operation truth value IXNOR of the drain of NM8 is 0.

7. The SRAM memory cell according to claim 1, wherein: The SRAM storage unit is applied to a storage-computation-in-one circuit.

8. The layout of the SRAM storage cell according to any one of claims 1 to 7, characterized in that: include: 6-transistor SRAM pattern and 5-transistor aXNOR pattern; The 6-transistor SRAM pattern and the 5-transistor aXNOR pattern respectively include: an active area pattern and a polysilicon pattern spanning the active area pattern; a contact hole pattern located on the active area pattern and distributed on one side of the polysilicon pattern; The 6-transistor SRAM graphics include: Transistor NM2, NM3, PM0, PM1 graphics and transistor NM0, NM1 graphics; wherein, The transistors NM0 and NM1 are shown as pull-down tubes, the transistors PM0 and PM1 are shown as riser tubes, and the transistors NM2 and NM3 are shown as transmission tubes. The 5-transistor aXNOR pattern includes: The graphs of transistors PM6 and PM7 and transistors NM7, NM8 and NM59; Among them, the transistor PM6 and PM7 graphics are located between the transistor PM0 and PM1 graphics in the 6-transistor SRAM graphics, the transistor NM7, NM8, and NM59 graphics are located in the design area near the 6-transistor SRAM graphics, and the transistor NM7, NM8, and NM59 graphics are connected to the transistor PM6 and PM7 graphics through the metal layer graphics.

9. The layout of the SRAM storage unit according to claim 8, characterized in that: The transistors PM6 and PM7 are graphically arranged symmetrically.

10. The layout of the SRAM storage unit according to claim 8, characterized in that: The transistors NM0 and NM3 are located on a first side close to the transistor PM0 graphic, and the transistors NM0, NM1, NM7, NM8, and NM59 are located on a second side close to the transistor PM1 graphic.

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